Matt Arsenault
05e96f4444
R600: Try to convert BFE back to standard bit ops when possible.
...
This allows existing DAG combines to work on them, and then
we can re-match to BFE if necessary during instruction selection.
llvm-svn: 209462
2014-05-22 18:09:12 +00:00
Matt Arsenault
5565f65e13
R600: Add dag combine for BFE
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llvm-svn: 209461
2014-05-22 18:09:07 +00:00
Matt Arsenault
bf8694d36d
R600: Implement ComputeNumSignBitsForTargetNode for BFE
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llvm-svn: 209460
2014-05-22 18:09:03 +00:00
Jay Foad
a0653a3e6c
Rename ComputeMaskedBits to computeKnownBits. "Masked" has been
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inappropriate since it lost its Mask parameter in r154011.
llvm-svn: 208811
2014-05-14 21:14:37 +00:00
Matt Arsenault
5dbd5db518
R600: Make sign_extend_inreg legal.
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Don't know why I didn't just do this in the first place.
llvm-svn: 206862
2014-04-22 03:49:30 +00:00
Matt Arsenault
78b8670aac
R600/SI: Try to use scalar BFE.
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Use scalar BFE with constant shift and offset when possible.
This is complicated by the fact that the scalar version packs
the two operands of the vector version into one.
llvm-svn: 206558
2014-04-18 05:19:26 +00:00
Matt Arsenault
27cc958dff
R600/SI: Match sign_extend_inreg to s_sext_i32_i8 and s_sext_i32_i16
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llvm-svn: 206547
2014-04-18 01:53:18 +00:00
Matt Arsenault
4ef2588b65
R600: Extend r600 sign_extend_inreg tests for EG
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Patch by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 206349
2014-04-16 01:41:34 +00:00
Matt Arsenault
b517c8128e
R600: Implement isZExtFree.
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This allows 64-bit operations that are truncated to be reduced
to 32-bit ones.
llvm-svn: 204946
2014-03-27 17:23:31 +00:00
Matt Arsenault
d125d74a73
R600/SI: Fix unreachable with a sext_in_reg to an illegal type.
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llvm-svn: 204945
2014-03-27 17:23:24 +00:00
Matt Arsenault
90b733a3cf
R600: Add a testcase for sext_in_reg I missed.
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This sext_inreg i32 in i64 case was already handled, but not enabled.
llvm-svn: 204840
2014-03-26 18:31:06 +00:00
Matt Arsenault
fae02989b7
R600: Match sign_extend_inreg to BFE instructions
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llvm-svn: 204072
2014-03-17 18:58:11 +00:00