llvm-project

Commit Graph

Author	SHA1	Message	Date
Tom Stellard	50122a5890	R600: Match 24-bit arithmetic patterns in a Target DAGCombine Moving these patterns from TableGen files to PerformDAGCombine() should allow us to generate better code by eliminating unnecessary shifts and extensions earlier. This also fixes a bug where the MAD pattern was calling SimplifyDemandedBits with a 24-bit mask on the first operand even when the full pattern wasn't being matched. This occasionally resulted in some instructions being incorrectly deleted from the program. v2: - Fix bug with 64-bit mul llvm-svn: 205731	2014-04-07 19:45:41 +00:00
Tom Stellard	70f13dba15	R600/SI: Use -verify-machineinstrs for most tests We can't enable the verifier for tests with SI_IF and SI_ELSE, because these instructions are always followed by a COPY which copies their result to the next basic block. This violates the machine verifier's rule that non-terminators can not folow terminators. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 192366	2013-10-10 17:11:46 +00:00
Tom Stellard	5263948a7b	R600: Add support for 24-bit MAD instructions Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186923	2013-07-23 01:48:49 +00:00

Author

SHA1

Message

Date

Tom Stellard

50122a5890

R600: Match 24-bit arithmetic patterns in a Target DAGCombine

Moving these patterns from TableGen files to PerformDAGCombine()
should allow us to generate better code by eliminating unnecessary
shifts and extensions earlier.

This also fixes a bug where the MAD pattern was calling
SimplifyDemandedBits with a 24-bit mask on the first operand
even when the full pattern wasn't being matched.  This occasionally
resulted in some instructions being incorrectly deleted from the
program.

v2:
  - Fix bug with 64-bit mul

llvm-svn: 205731

2014-04-07 19:45:41 +00:00

Tom Stellard

70f13dba15

R600/SI: Use -verify-machineinstrs for most tests

We can't enable the verifier for tests with SI_IF and SI_ELSE, because
these instructions are always followed by a COPY which copies their
result to the next basic block.  This violates the machine verifier's
rule that non-terminators can not folow terminators.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 192366

2013-10-10 17:11:46 +00:00

Tom Stellard

5263948a7b

R600: Add support for 24-bit MAD instructions

Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186923

2013-07-23 01:48:49 +00:00

3 Commits