3 Commits

Author	SHA1	Message	Date
Craig Topper	bd16b11255	[X86] Consistently use double underscore at the beginning of the include guards in our intrinsic headers. ... Most files used double underscore, but a few used single. This converges them all to double. llvm-svn: 330743	2018-04-24 17:40:47 +00:00
Ekaterina Romanova	5a7f09c5af	Clean up: remove trailing spaces in x86 intrinsic headers. ... Differential Revision: http://reviews.llvm.org/D20614 llvm-svn: 271077	2016-05-28 00:18:59 +00:00
Ashutosh Nema	51c9dd0081	Add new intrinsic support for MONITORX and MWAITX instructions ... Summary: MONITORX/MWAITX instructions provide similar capability to the MONITOR/MWAIT pair while adding a timer function, such that another termination of the MWAITX instruction occurs when the timer expires. The presence of the MONITORX and MWAITX instructions is indicated by CPUID 8000_0001, ECX, bit 29. The MONITORX and MWAITX instructions are intercepted by the same bits that intercept MONITOR and MWAIT. MONITORX instruction establishes a range to be monitored. MWAITX instruction causes the processor to stop instruction execution and enter an implementation-dependent optimized state until occurrence of a class of events. Opcode of MONITORX instruction is "0F 01 FA". Opcode of MWAITX instruction is "0F 01 FB". These opcode information is used in adding tests for the disassembler. These instructions are enabled for AMD's bdver4 architecture. Patch by Ganesh Gopalasubramanian! Reviewers: echristo, craig.topper Subscribers: RKSimon, joker.eph, llvm-commits, cfe-commits Differential Revision: http://reviews.llvm.org/D19796 llvm-svn: 269907	2016-05-18 11:56:23 +00:00