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13 Commits

Author SHA1 Message Date
Akira Hatanaka d6af2c62b4 Implement N32/64 calling convention. Patch by Liu. 
llvm-svn: 140401
 2011-09-23 19:08:15 +00:00
Akira Hatanaka 27029885f0 Add A0 and A1 to the list of registers used for returning a value in order to 
handle functions with return type Complex long long.

llvm-svn: 133497
 2011-06-21 01:28:11 +00:00
Duncan Sands 56ca6292dc Fix comment typo. Noticed by Liu. 
llvm-svn: 130120
 2011-04-25 06:21:43 +00:00
Akira Hatanaka e24891251c Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. 
llvm-svn: 129612
 2011-04-15 21:51:11 +00:00
Akira Hatanaka aef55c8801 Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality. 
llvm-svn: 129606
 2011-04-15 21:00:26 +00:00
Bruno Cardoso Lopes ed874eff93 Remove (hopefully) all trailing whitespaces from the mips backend. Patch by Hatanaka, Akira 
llvm-svn: 127003
 2011-03-04 17:51:39 +00:00
Chris Lattner 72a364c107 fix emacs language spec's, patch by Edmund Grimley-Evans! 
llvm-svn: 111241
 2010-08-17 16:20:04 +00:00
Bruno Cardoso Lopes 2f5c8e3495 Fix return registers for mips eabi 
llvm-svn: 93875
 2010-01-19 12:37:35 +00:00
Bruno Cardoso Lopes 3b7b301a24 Added support for Mips O32 Calling Convention 
llvm-svn: 67280
 2009-03-19 02:12:28 +00:00
Bruno Cardoso Lopes 3e667cfe21 Fix PR2615 
llvm-svn: 54312
 2008-08-03 15:37:43 +00:00
Bruno Cardoso Lopes c9c3f49993 Several changes to Mips backend, experimental fp support being the most 
important.
- Cleanup in the Subtarget info with addition of new features, not all support
  yet, but they allow the future inclusion of features easier. Among new features,
  we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
  integer
  and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
  aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
  sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
  FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
  FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
  return copy, no homing location within EABI, non 32-bit stack objects
  arguments, and asm constraint for float.

llvm-svn: 53146
 2008-07-05 19:05:21 +00:00
Chris Lattner f3ebc3f3d2 Remove attribution from file headers, per discussion on llvmdev. 
llvm-svn: 45418
 2007-12-29 20:36:04 +00:00
Bruno Cardoso Lopes 35e43c49b0 Initial Mips support, here we go! =) 
- Modifications from the last patch included
  (issues pointed by Evan Cheng are now fixed).
- Added more MipsI instructions.
- Added more patterns to match branch instructions.

llvm-svn: 37461
 2007-06-06 07:42:06 +00:00