70aa8d0745
Fix pr6111: Avoid using the LR register for the target address of an indirect
...
branch in ARM v4 code, since it gets clobbered by the return address before
it is used. Instead of adding a new register class containing all the GPRs
except LR, just use the existing tGPR class.
llvm-svn: 96360
2010-02-16 17:24:15 +00:00
a945c64b5a
Put repeated empty pattern into the AQI instruction class.
...
We could almost use a multiclass for the signed/unsigned instructions, but
there are only 6 of them so I guess it's not worth it.
llvm-svn: 96297
2010-02-15 23:43:47 +00:00
ab663a0bfe
Move TLOF implementations to libCodegen to resolve layering violation.
...
llvm-svn: 96288
2010-02-15 22:37:53 +00:00
5e73ff2e3a
Split SelectionDAGISel::IsLegalAndProfitableToFold to
...
IsLegalToFold and IsProfitableToFold. The generic version of the later simply checks whether the folding candidate has a single use.
This allows the target isel routines more flexibility in deciding whether folding makes sense. The specific case we are interested in is folding constant pool loads with multiple uses.
llvm-svn: 96255
2010-02-15 19:41:07 +00:00
0d0149f5ac
Remove an assumption of default arguments. This is in anticipation of a
...
change to SelectionDAG build APIs.
llvm-svn: 96230
2010-02-15 16:55:24 +00:00
c95a814ec3
Try to factorize the specification of saturating add/subtract operations a bit,
...
as suggested by Bob Wilson.
llvm-svn: 96153
2010-02-14 06:32:20 +00:00
52a6ab3ba7
Add SETEND and BXJ instructions for disassembly only.
...
llvm-svn: 96075
2010-02-13 02:51:09 +00:00
3b065cdb64
Teach MachineFrameInfo to track maximum alignment while stack objects are being
...
created. This ensures it's updated at all time. It means targets which perform
dynamic stack alignment would know whether it is required and whether frame
pointer register cannot be made available register allocation.
This is a fix for rdar://7625239. Sorry, I can't create a reasonably sized test
case.
llvm-svn: 96069
2010-02-13 01:56:41 +00:00
b0208d2a06
Added a bunch of saturating add/subtract instructions for disassembly only.
...
llvm-svn: 96063
2010-02-13 01:21:01 +00:00
29a9103ee6
Add YIELD, WFE, WFI, and SEV instructions for disassembly only.
...
Plus add two formats: MiscFrm and ThumbMiscFrm. Some of the for disassembly
only instructions are changed from Pseudo Format to MiscFrm Format.
llvm-svn: 96032
2010-02-12 22:53:19 +00:00
439bda9d3f
Load / store multiple instructions cannot load / store sp. Sorry, can't come up with a reasonable test case.
...
llvm-svn: 96023
2010-02-12 22:17:21 +00:00
dc2051c802
Add halfword multiply accumulate long SMLALBB/BT/TB/TT for disassembly only.
...
llvm-svn: 96019
2010-02-12 21:59:23 +00:00
bdf1b9520c
Add SWP (Swap) and SWPB (Swap Byte) for disassembly only.
...
llvm-svn: 96010
2010-02-12 20:48:24 +00:00
cf20cbec49
Add CPS, MRS, MRSsys, MSR, MSRsys for disassembly only.
...
llvm-svn: 95999
2010-02-12 18:55:33 +00:00
905a2d7727
Added coprocessor Instructions CDP, CDP2, MCR, MCR2, MRC, MRC2, MCRR, MCRR2,
...
MRRC, MRRc2. For disassembly only.
llvm-svn: 95955
2010-02-12 01:44:23 +00:00
af88c0a84d
Added LDRT/LDRBT/STRT/STRBT for disassembly only.
...
llvm-svn: 95916
2010-02-11 20:31:08 +00:00
3964059a16
Forgot to also check in this file for vcvt (floating-point <-> fixed-point, VFP).
...
Sorry!
llvm-svn: 95892
2010-02-11 18:47:03 +00:00
2588efd071
Added VCVT (between floating-point and fixed-point, VFP) for disassembly.
...
A8.6.297
llvm-svn: 95885
2010-02-11 18:17:16 +00:00
f40b8e03fb
Added BKPT/tBKPT (breakpoint) to the instruction table for disassembly purpose.
...
llvm-svn: 95884
2010-02-11 18:12:29 +00:00
9c13dfb5dd
Add pseudo instruction TRAP for disassembly, which is encoded according to A5-21
...
as the "Permanently UNDEFINED" instruction.
llvm-svn: 95873
2010-02-11 17:14:31 +00:00
c7e14704d0
Added NOP, DBG, SVC to the instruction table for disassembly purpose.
...
llvm-svn: 95784
2010-02-10 18:02:25 +00:00
ff68a42121
print all the newlines at the end of instructions with
...
OutStreamer.AddBlankLine instead of textually.
llvm-svn: 95734
2010-02-10 00:36:00 +00:00
1215c774f2
Add VBIF/VBIT for disassembly only.
...
A8.6.279
llvm-svn: 95713
2010-02-09 23:05:23 +00:00
b618f66c5f
Added VMRS/VMSR for disassembly only.
...
A8.6.335 & A8.6.336
llvm-svn: 95703
2010-02-09 22:35:38 +00:00
b06015aa69
move target-independent opcodes out of TargetInstrInfo
...
into TargetOpcodes.h. #include the new TargetOpcodes.h
into MachineInstr. Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the
codebase.
llvm-svn: 95687
2010-02-09 19:54:29 +00:00
f7279bd10f
Radar 7417921
...
tMOVCCi pattern only valid for low registers, as the Thumb1 mov immediate to
register instruction only works with low registers. Allowing high registers
for the instruction resulted in the assembler choosing the wide (32-bit)
encoding for the mov, but LLVM though the instruction was only 16 bits wide,
so offset calculations for constant pools became incorrect, leading to
out of range constant pool entries.
llvm-svn: 95686
2010-02-09 19:51:37 +00:00
64e0ae8dd4
Added vcvtb/vcvtt (between half-precision and single-precision, VFP).
...
For disassembly only.
A8.6.300
llvm-svn: 95669
2010-02-09 17:21:56 +00:00
08297ad15d
this is done, tested by CodeGen/ARM/iabs.ll
...
llvm-svn: 95609
2010-02-08 23:48:10 +00:00
a570d05228
tighten up eh.setjmp sequence a bit.
...
llvm-svn: 95603
2010-02-08 23:22:00 +00:00
9e60686a83
Add VCVTR (between floating-point and integer, VFP) for disassembly purpose.
...
The 'R' suffix means the to-integer operations use the rounding mode specified
by the FPSCR, encoded as Inst{7} = 0.
A8.6.295
llvm-svn: 95584
2010-02-08 22:02:41 +00:00
beb1238a85
Add VCMP (VFP floating-point compare without 'E' bit set) for disassembly purpose.
...
llvm-svn: 95560
2010-02-08 19:41:48 +00:00
c7e606f132
Added VMOVRRS/VMOVSRR to ARMInstrVFP.td for disassembly purpose.
...
A8.6.331 VMOV (between two ARM core registers and two single-precision registers)
llvm-svn: 95548
2010-02-08 17:26:09 +00:00
5638c36efd
Handle AddrMode6 (for NEON load/stores) in Thumb2's rewriteT2FrameIndex.
...
Radar 7614112.
llvm-svn: 95456
2010-02-06 00:24:38 +00:00
a778db9a91
VMOVRRD and VMOVDRR both have Inst{7-6} = 0b00.
...
llvm-svn: 95397
2010-02-05 18:04:58 +00:00
082f484074
make MachineModuleInfoMachO hold non-const MCSymbol*'s instead
...
of const ones. non-const ones aren't very useful, because you can't
even, say, emit them.
llvm-svn: 95205
2010-02-03 06:18:30 +00:00
6f1f865fba
print instructions through the mcstreamer.
...
llvm-svn: 95181
2010-02-03 01:16:28 +00:00
996ec840d0
rejigger the world so that EmitInstruction prints the \n at
...
the end of the instruction instead of expecting the caller to
do it. This currently causes the asm-verbose instruction
comments to be on the next line.
llvm-svn: 95178
2010-02-03 01:09:55 +00:00
41ad1905c9
sink handling of target-independent machine instrs (other
...
than DEBUG_VALUE :( ) into the target indep AsmPrinter.cpp
file. This allows elimination of the
NO_ASM_WRITER_BOILERPLATE hack among other things.
llvm-svn: 95177
2010-02-03 01:00:52 +00:00
d0a2f52f8f
As of r79039, we still try to eliminate the frame pointer on leaf functions,
...
even when -disable-fp-elim is specified.
llvm-svn: 95161
2010-02-02 23:56:14 +00:00
6f36a083ef
Revert 95130.
...
llvm-svn: 95160
2010-02-02 23:55:14 +00:00
b0d44c3807
refactor code so that LLVMTargetMachine creates the asmstreamer and
...
mccontext instead of having AsmPrinter do it. This allows other
types of MCStreamer's to be passed in.
llvm-svn: 95155
2010-02-02 23:37:42 +00:00
f46359642f
tidy some targets.
...
llvm-svn: 95146
2010-02-02 22:13:21 +00:00
8d806876c0
detemplatize ARM code emitter.
...
llvm-svn: 95138
2010-02-02 21:48:51 +00:00
c83cfb9dfa
remove dead code.
...
llvm-svn: 95134
2010-02-02 21:38:59 +00:00
0cd6c2a047
eliminate all the dead addSimpleCodeEmitter implementations.
...
eliminate random "code emitter" stuff in Alpha, except for
the JIT path. Next up, remove the template cruft.
llvm-svn: 95131
2010-02-02 21:31:47 +00:00
c1b0116ff1
Pass callsite return type to TargetLowering::LowerCall and use that to check sibcall eligibility.
...
llvm-svn: 95130
2010-02-02 21:29:10 +00:00
8487d65ea2
Added t2BFI (Bitfield Insert) entry for disassembler, with blank pattern field.
...
llvm-svn: 95112
2010-02-02 19:31:58 +00:00
5b66b31774
MOVi16 should also be marked as a UnaryDP instruction, i.e., it doesn't have a
...
Rn operand.
llvm-svn: 95025
2010-02-01 23:06:04 +00:00
b3562f7cf6
For MVNr and MVNs, we need to set Inst{25} = 0 so as not to confuse the decoder.
...
llvm-svn: 94955
2010-01-31 11:22:28 +00:00
25df248382
Fix a gross typo: ARMv6+ may or may not support unaligned memory operations.
...
Even if they are suported by the core, they can be disabled
(this is just a configuration bit inside some register).
Allow unaligned memops on darwin and conservatively disallow them otherwise.
llvm-svn: 94889
2010-01-30 14:08:12 +00:00
Bob Wilson