Commit Graph

8405 Commits

Author SHA1 Message Date
Rafael Espindola 396b4a6b7b add ADDS and ADCS
llvm-svn: 30830
2006-10-09 17:18:28 +00:00
Rafael Espindola e4c3276afc expand ISD::SELECT
llvm-svn: 30829
2006-10-09 16:28:33 +00:00
Rafael Espindola c154dacb2f add a note
llvm-svn: 30828
2006-10-09 14:18:33 +00:00
Rafael Espindola 41730922bb expand ISD::EXTLOAD
llvm-svn: 30827
2006-10-09 14:13:40 +00:00
Rafael Espindola 78d6c2bf59 most ARM targets are little endian
llvm-svn: 30826
2006-10-09 14:12:15 +00:00
Rafael Espindola b50938866b implement FUITOS and FUITOD
llvm-svn: 30803
2006-10-07 14:24:52 +00:00
Rafael Espindola 58c368bc4f implement FLDD
llvm-svn: 30802
2006-10-07 14:03:39 +00:00
Rafael Espindola 40f5dd27f0 implement fadds, faddd, fmuls and fmuld
llvm-svn: 30801
2006-10-07 13:46:42 +00:00
Rafael Espindola aa2a12f1a2 add optional input flag to FMRRD
llvm-svn: 30774
2006-10-06 20:33:26 +00:00
Rafael Espindola 671f25281d add support for calling functions that return double
llvm-svn: 30771
2006-10-06 19:10:05 +00:00
Rafael Espindola ef01656ea4 fix some bugs affecting functions with no arguments
llvm-svn: 30767
2006-10-06 17:26:30 +00:00
Rafael Espindola 6024ea8383 fix the stack alignment
llvm-svn: 30766
2006-10-06 14:29:47 +00:00
Rafael Espindola 5fe7909e18 add support for calling functions that have double arguments
llvm-svn: 30765
2006-10-06 12:50:22 +00:00
Evan Cheng df9ac47e5e Make use of getStore().
llvm-svn: 30759
2006-10-05 23:01:46 +00:00
Rafael Espindola decfeca52d use a const ref for passing the vector to ArgumentLayout
llvm-svn: 30756
2006-10-05 17:46:48 +00:00
Rafael Espindola e04df41ca2 implement a ArgumentLayout class to factor code common to LowerFORMAL_ARGUMENTS and LowerCALL
implement FMDRR
add support for f64 function arguments

llvm-svn: 30754
2006-10-05 16:48:49 +00:00
Chris Lattner a6a570e02f Pass the MachineFunction into EmitJumpTableInfo.
llvm-svn: 30742
2006-10-05 03:01:21 +00:00
Chris Lattner 4431699187 Use getSectionForFunction.
llvm-svn: 30740
2006-10-05 02:49:23 +00:00
Rafael Espindola 68d238801c Implement floating point constants
llvm-svn: 30704
2006-10-03 17:27:58 +00:00
Rafael Espindola d55c0a41df fix the names of the 64bit fp register
initial support for returning 64bit floating point numbers

llvm-svn: 30692
2006-10-02 19:30:56 +00:00
Rafael Espindola 53f78be49e add floating point registers
implement SINT_TO_FP

llvm-svn: 30673
2006-09-29 21:20:16 +00:00
Rafael Espindola 72d4c070c0 add a note
llvm-svn: 30581
2006-09-22 11:36:17 +00:00
Rafael Espindola 7b700e517a more condition codes
llvm-svn: 30567
2006-09-21 13:06:26 +00:00
Rafael Espindola 0c71a5adc8 if a constant can't be an immediate, add it to the constant pool
llvm-svn: 30566
2006-09-21 11:29:52 +00:00
Rafael Espindola fa7217f970 fix header
add comments
untabify

llvm-svn: 30486
2006-09-19 16:41:40 +00:00
Rafael Espindola f7d4a9900c Implement a MachineFunctionPass to fix the mul instruction
llvm-svn: 30485
2006-09-19 15:49:25 +00:00
Rafael Espindola 3130a756ef add shifts to addressing mode 1
llvm-svn: 30291
2006-09-13 12:09:43 +00:00
Evan Cheng 9a083a4121 Reflects MachineConstantPoolEntry changes.
llvm-svn: 30279
2006-09-12 21:04:05 +00:00
Rafael Espindola c7829d62c0 implement SRL and MUL
llvm-svn: 30262
2006-09-11 19:24:19 +00:00
Rafael Espindola bccf9c2f1b add the correct fallback for ARMDAGToDAGISel::SelectAddrMode1
llvm-svn: 30261
2006-09-11 19:23:32 +00:00
Rafael Espindola e45a79a9e2 partial implementation of the ARM Addressing Mode 1
llvm-svn: 30252
2006-09-11 17:25:40 +00:00
Rafael Espindola ecb0d686f8 call AsmPrinter::doInitialization in ARMAsmPrinter::doInitialization
llvm-svn: 30246
2006-09-11 12:49:38 +00:00
Anton Korobeynikov fbee8bfe48 Removed unnecessary Mangler creation.
llvm-svn: 30239
2006-09-10 21:17:03 +00:00
Rafael Espindola d11fb5d13b implement shl and sra
llvm-svn: 30191
2006-09-08 17:36:23 +00:00
Rafael Espindola 4443c7d60a add the eor (xor) instruction
llvm-svn: 30189
2006-09-08 16:59:47 +00:00
Rafael Espindola 778769aafb implement unconditional branches
fix select.ll

llvm-svn: 30186
2006-09-08 12:47:03 +00:00
Jim Laskey ae92ce8798 1. Remove condition on delete.
2. Protect and outline createTargetAsmInfo.

3. Misc. kruft.

llvm-svn: 30169
2006-09-07 23:39:26 +00:00
Jim Laskey 261779bb45 Make target asm info a property of the target machine.
llvm-svn: 30162
2006-09-07 22:06:40 +00:00
Jim Laskey 0e83541f8b Break out target asm info into separate files.
llvm-svn: 30161
2006-09-07 22:05:02 +00:00
Jim Laskey a6211dcdad Separate target specific asm properties from the asm printers.
llvm-svn: 30126
2006-09-06 18:34:40 +00:00
Rafael Espindola abd8bcbe5e add the orr instruction
llvm-svn: 30125
2006-09-06 18:03:12 +00:00
Chris Lattner af23f9b5f6 Completely eliminate def&use operands. Now a register operand is EITHER a
def operand or a use operand.

llvm-svn: 30109
2006-09-05 02:31:13 +00:00
Rafael Espindola 8386105f3f add support for returning 64bit values
llvm-svn: 30103
2006-09-04 19:05:01 +00:00
Chris Lattner 12e97307a1 Completely rearchitect the interface between targets and the pass manager.
This pass:

1. Splits TargetMachine into TargetMachine (generic targets, can be implemented
any way, like the CBE) and LLVMTargetMachine (subclass of TM that is used by
things using libcodegen and other support).
2. Instead of having each target fully populate the passmgr for file or JIT
   output, move all this to common code, and give targets hooks they can
   implement.
3. Commonalize the target population stuff between file emission and JIT
   emission.
4. All (native code) codegen stuff now happens in a FunctionPassManager, which
   paves the way for "fast -O0" stuff in the CFE later, and now LLC could
   lazily stream .bc files from disk to use less memory.
5. There are now many fewer #includes and the targets don't depend on the
   scalar xforms or libanalysis anymore (but codegen does).
6. Changing common code generator pass ordering stuff no longer requires
   touching all targets.
7. The JIT now has the option of "-fast" codegen or normal optimized codegen,
   which is now orthogonal to the fact that JIT'ing is being done.

llvm-svn: 30081
2006-09-04 04:14:57 +00:00
Chris Lattner 0fc4541c67 Simplify target construction.
llvm-svn: 30070
2006-09-03 18:44:02 +00:00
Rafael Espindola 5328ba96e1 add the SETULT condition code
llvm-svn: 30067
2006-09-03 13:19:16 +00:00
Rafael Espindola c585b6919b add more condition codes
llvm-svn: 30056
2006-09-02 20:24:25 +00:00
Evan Cheng 61413a3d72 Select() no longer require Result operand by reference.
llvm-svn: 29898
2006-08-26 05:34:46 +00:00
Rafael Espindola 98dc23fd1f use @ for comments
store LR in an arbitrary stack slot
add support for writing varargs functions

llvm-svn: 29876
2006-08-25 17:55:16 +00:00
Rafael Espindola 29e4875f57 add the "eq" condition code
implement a movcond instruction

llvm-svn: 29857
2006-08-24 17:19:08 +00:00
Rafael Espindola fe03fe9bf4 create a generic bcond instruction that has a conditional code argument
llvm-svn: 29856
2006-08-24 16:13:15 +00:00
Rafael Espindola e08b9853cc initial support for branches
llvm-svn: 29854
2006-08-24 13:45:55 +00:00
Rafael Espindola ea500426d6 add a README.txt
llvm-svn: 29814
2006-08-22 12:22:46 +00:00
Rafael Espindola d0dee77718 initial support for select
llvm-svn: 29802
2006-08-21 22:00:32 +00:00
Rafael Espindola 9d77f9fd24 add the and instruction
llvm-svn: 29793
2006-08-21 13:58:59 +00:00
Rafael Espindola 8a675a5d09 call computeRegisterProperties
llvm-svn: 29780
2006-08-20 01:49:49 +00:00
Chris Lattner 60f1eecd3a Constify some methods. Patch provided by Anton Vayvod, thanks!
llvm-svn: 29756
2006-08-17 22:00:08 +00:00
Rafael Espindola c3ed77e1b9 add a "load effective address"
llvm-svn: 29748
2006-08-17 17:09:40 +00:00
Rafael Espindola bf8e751488 Declare the callee saved regs
Remove the hard coded store and load of the link register
Implement ARMFrameInfo

llvm-svn: 29727
2006-08-16 14:43:33 +00:00
Rafael Espindola 157971b04a select code like
ldr rx, [ry, #offset]

llvm-svn: 29664
2006-08-14 19:01:24 +00:00
Chris Lattner ed728e8dc9 Eliminate use of getNode that takes a vector.
llvm-svn: 29614
2006-08-11 17:38:39 +00:00
Chris Lattner c62914880f elimiante use of getNode that takes vector of operands.
llvm-svn: 29612
2006-08-11 17:22:35 +00:00
Evan Cheng bd1c5a8fb8 Match tablegen changes.
llvm-svn: 29604
2006-08-11 09:08:15 +00:00
Evan Cheng 81b645a76b CALLSEQ_* produces chain even if that's not needed.
llvm-svn: 29603
2006-08-11 09:03:33 +00:00
Rafael Espindola 1c41fc9b06 correctly set LocalAreaOffset of TargetFrameInfo
llvm-svn: 29589
2006-08-09 17:37:45 +00:00
Rafael Espindola f5ce475540 fix the spill code
llvm-svn: 29583
2006-08-09 16:41:12 +00:00
Rafael Espindola 58159b36a3 fix the loading of the link register in emitepilogue
llvm-svn: 29580
2006-08-09 13:15:47 +00:00
Rafael Espindola 8c41f99e6f change the addressing mode of the str instruction to reg+imm
llvm-svn: 29571
2006-08-08 20:35:03 +00:00
Rafael Espindola 39083e7836 initial support for variable number of arguments
llvm-svn: 29567
2006-08-08 13:02:29 +00:00
Evan Cheng b9d34bd098 Match tablegen isel changes.
llvm-svn: 29549
2006-08-07 22:28:20 +00:00
Rafael Espindola 2bcb8c0f05 use a 'register pressure reducing' scheduler
make sure only one move is used in a hello world

llvm-svn: 29520
2006-08-04 12:48:42 +00:00
Rafael Espindola e19f6fde2d Bug fix: always generate a RET_FLAG in LowerRET
fixes ret_null.ll and call.ll

llvm-svn: 29519
2006-08-03 22:50:11 +00:00
Rafael Espindola a94b9e33af add and use ARMISD::RET_FLAG
llvm-svn: 29499
2006-08-03 17:02:20 +00:00
Rafael Espindola 8b7bd8264b start comments with #
move the constant pool to .text
correctly print loads of labels
mark R0, R1, R2 and R3 as caller save

llvm-svn: 29451
2006-08-01 18:53:10 +00:00
Rafael Espindola 95035cf001 implement LowerConstantPool and LowerGlobalAddress
llvm-svn: 29433
2006-08-01 12:58:43 +00:00
Rafael Espindola 7cc2d19fc1 handle GlobalValue::InternalLinkage in doFinalization
llvm-svn: 29417
2006-07-31 20:38:13 +00:00
Evan Cheng b572401bea Remove InFlightSet hack. No longer needed.
llvm-svn: 29373
2006-07-28 00:47:19 +00:00
Rafael Espindola 89e5cbd897 emit global constants
llvm-svn: 29344
2006-07-27 11:38:51 +00:00
Rafael Espindola 8902fd702b implement function calling of functions with up to 4 arguments
llvm-svn: 29274
2006-07-25 20:17:20 +00:00
Rafael Espindola 976c93a110 implemented sub
correctly update the stack pointer in the prologue and epilogue

llvm-svn: 29244
2006-07-21 12:26:16 +00:00
Rafael Espindola bf3a17cd32 initial prologue and epilogue implementation. Need to define add and sub before finishing it :-)
llvm-svn: 29175
2006-07-18 17:00:30 +00:00
Rafael Espindola 75269be065 skeleton of a lowerCall implementation for ARM
llvm-svn: 29159
2006-07-16 01:02:57 +00:00
Rafael Espindola 185c5c2bdf add the memri memory operand
this makes it possible for ldr instructions with non-zero immediate

llvm-svn: 29103
2006-07-11 11:36:48 +00:00
Rafael Espindola e40a7e2aa2 create the raddr addressing mode that matches any register and the frame index
use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot

llvm-svn: 29079
2006-07-10 01:41:35 +00:00
Rafael Espindola f6f5aff038 handle the "mov reg1, reg2" case in isMoveInstr
llvm-svn: 28945
2006-06-27 21:52:45 +00:00
Rafael Espindola a88966fd5e initial implementation of ARMRegisterInfo::eliminateFrameIndex
fixes test/Regression/CodeGen/ARM/ret_arg5.ll

llvm-svn: 28854
2006-06-18 00:08:07 +00:00
Chris Lattner f3b5b92e58 Don't pass target name into TargetData anymore, it is never used or needed.
Remove explicit casts to std::string now that there is no overload resolution
issues in the TargetData ctors.

llvm-svn: 28830
2006-06-16 18:22:52 +00:00
Rafael Espindola 4e76015e0b lower more then 4 formal arguments. The offset is currently hard coded.
implement SelectFrameIndex

llvm-svn: 28751
2006-06-12 12:28:08 +00:00
Rafael Espindola 6306becc49 add R0 to liveout
expand "ret null" (implements test/Regression/CodeGen/ARM/ret_void.ll)
note that a Flag link is missing between the copy and the branch

llvm-svn: 28691
2006-06-05 22:26:14 +00:00
Rafael Espindola 5bc60da112 Expand ret into "CopyToReg;BRIND"
llvm-svn: 28559
2006-05-30 17:33:19 +00:00
Chris Lattner 64d8692dee Ignore generated files
llvm-svn: 28520
2006-05-27 01:23:30 +00:00
Evan Cheng a3add0fea8 Change RET node to include signness information of the return values. i.e.
RET chain, value1, sign1, value2, sign2, ...

llvm-svn: 28510
2006-05-26 23:10:12 +00:00
Rafael Espindola 87bc1a9b0b On ARM, alignment is in bits
Add lr as a hard coded operand of bx

llvm-svn: 28494
2006-05-26 10:56:17 +00:00
Rafael Espindola 91df1ef41f implement initial version of ARMAsmPrinter::printOperand
llvm-svn: 28470
2006-05-25 12:57:06 +00:00
Rafael Espindola 4781610886 port the ARM backend to use ISD::CALL instead of LowerCallTo
llvm-svn: 28469
2006-05-25 11:00:18 +00:00
Evan Cheng 4af59dac0b Assert if InflightSet is not cleared after instruction selecting a BB.
llvm-svn: 28459
2006-05-25 00:24:28 +00:00
Evan Cheng 1a8e74d113 Clear HandleMap and ReplaceMap after instruction selection. Or it may cause
non-deterministic behavior.

llvm-svn: 28454
2006-05-24 20:46:25 +00:00
Chris Lattner aa2372562e Patches to make the LLVM sources more -pedantic clean. Patch provided
by Anton Korobeynikov!  This is a step towards closing PR786.

llvm-svn: 28447
2006-05-24 17:04:05 +00:00
Rafael Espindola 27f8bdc7e5 implement minimal versions of
ARMAsmPrinter::runOnMachineFunction
LowerFORMAL_ARGUMENTS
ARMInstrInfo::isMoveInstr

llvm-svn: 28431
2006-05-23 02:48:20 +00:00
Owen Anderson 88812b5c0a Make all of the TargetMachine subclasses use the new string TargetData methods.
This is part of the on-going work on PR 761.

llvm-svn: 28414
2006-05-20 00:24:56 +00:00
Rafael Espindola b15597b59a implement movri
add a stub LowerFORMAL_ARGUMENTS

llvm-svn: 28388
2006-05-18 21:45:49 +00:00
Evan Cheng 305c49579c getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
llvm-svn: 28378
2006-05-18 00:12:58 +00:00
Evan Cheng dcec882286 Remove PointerType from class Target
llvm-svn: 28368
2006-05-17 21:20:27 +00:00
Rafael Espindola 4abf33f56e add an abort after every assert(0)
llvm-svn: 28310
2006-05-15 22:34:39 +00:00
Rafael Espindola ffdc24b847 added a skeleton of the ARM backend
llvm-svn: 28301
2006-05-14 22:18:28 +00:00