003cea6011
ARM assembly parsing for data type suffices on NEON VMOV aliases.
...
llvm-svn: 144722
2011-11-15 22:54:42 +00:00
131b45e632
ARM alternate size suffices for VTRN instructions.
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rdar://10435076
llvm-svn: 144694
2011-11-15 20:49:46 +00:00
0ac9058f89
Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32.
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llvm-svn: 144683
2011-11-15 19:55:00 +00:00
2aabaa704a
ARM parsing datatype suffix variants for register-writeback VLD1/VST1 instructions.
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rdar://10435076
llvm-svn: 144650
2011-11-15 17:49:59 +00:00
7ca4b6eb5c
Add vmov.f32 to materialize f32 immediate splats which cannot be handled by
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integer variants. rdar://10437054
llvm-svn: 144608
2011-11-15 02:12:34 +00:00
29cdcda80d
ARM parsing datatype suffix variants for fixed-writeback VLD1/VST1 instructions.
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rdar://10435076
llvm-svn: 144606
2011-11-15 01:46:57 +00:00
a498af2b1d
ARM parsing datatype suffix variants for non-writeback VST1 instructions.
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rdar://10435076
llvm-svn: 144593
2011-11-14 23:43:46 +00:00
72838a0345
ARM parsing datatype suffix variants for non-writeback VLD1 instructions.
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rdar://10435076
llvm-svn: 144592
2011-11-14 23:32:59 +00:00
750de7a399
Add explanatory comment.
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llvm-svn: 144589
2011-11-14 23:21:09 +00:00
3d6c0e0bb2
ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions.
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rdar://10435076
llvm-svn: 144587
2011-11-14 23:11:19 +00:00
8ca13deecf
Re-apply 144430, this time with the associated isel and disassmbler bits.
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Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.'
llvm-svn: 144437
2011-11-12 00:31:53 +00:00
155763b630
Oops. Missed the isel half of this. revert while I sort that out.
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llvm-svn: 144431
2011-11-11 23:51:31 +00:00
28f721a2b4
ARM assembly parsing for VST1 two-register encoding.
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llvm-svn: 144430
2011-11-11 23:45:47 +00:00
05df460269
ARM VST1 w/ writeback assembly parsing and encoding.
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llvm-svn: 143369
2011-10-31 21:50:31 +00:00
409b694c6c
Specify that the high bit of the alignment field is fixed to 0 on these instructions.
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llvm-svn: 143220
2011-10-28 20:43:24 +00:00
17ec1a19e5
ARM assembly parsing and encoding for VLD1 with writeback.
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Four entry register lists.
llvm-svn: 142882
2011-10-25 00:14:01 +00:00
30c39c8bf2
Nuke dead code. Nothing generates the VLD1d64QPseudo_UPD instruction.
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llvm-svn: 142877
2011-10-24 23:40:46 +00:00
92fd05ecdc
ARM assembly parsing and encoding for VLD1 w/ writeback.
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Three entry register list variation.
llvm-svn: 142876
2011-10-24 23:26:05 +00:00
3ea0657d54
ARM assembly parsing and encoding for VLD1 w/ writeback.
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One and two length register list variants.
llvm-svn: 142861
2011-10-24 22:16:58 +00:00
2098cb1e6f
ARM refactor am6offset usage for VLD1.
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Split am6offset into fixed and register offset variants so the instruction
encodings are explicit rather than relying an a magic reg0 marker.
Needed to being able to parse these.
llvm-svn: 142853
2011-10-24 21:45:13 +00:00
11c0b347c6
Assembly parsing for 4-register sequential variant of VLD2.
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llvm-svn: 142704
2011-10-21 23:58:57 +00:00
118b38cbf1
Assembly parsing for 2-register sequential variant of VLD2.
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llvm-svn: 142691
2011-10-21 22:21:10 +00:00
846bcff7c7
Assembly parsing for 4-register variant of VLD1.
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llvm-svn: 142682
2011-10-21 20:35:01 +00:00
c4360fe575
Assembly parsing for 3-register variant of VLD1.
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llvm-svn: 142675
2011-10-21 20:02:19 +00:00
2f2e3c4737
ARM VLD parsing and encoding.
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Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.
Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.
llvm-svn: 142670
2011-10-21 18:54:25 +00:00
e3013dd62d
Remove some outdated comments.
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llvm-svn: 142653
2011-10-21 16:14:12 +00:00
9036c5cf2b
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding.
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llvm-svn: 142583
2011-10-20 15:04:25 +00:00
8db25984a9
ARM VTBX (one register) assembly parsing and encoding.
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llvm-svn: 142581
2011-10-20 14:48:50 +00:00
ad47cfcef9
ARM VTBL (one register) assembly parsing and encoding.
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llvm-svn: 142441
2011-10-18 23:02:30 +00:00
6918617e32
Yet more ARM NEON assembly parsing for the lane index operand.
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llvm-svn: 142416
2011-10-18 20:21:17 +00:00
e9f204c197
ARM vmla/vmls assembly parsing for the lane index operand.
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llvm-svn: 142413
2011-10-18 20:14:56 +00:00
712f3670fd
ARM vmov assembly parsing for the lane index operand.
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llvm-svn: 142412
2011-10-18 20:10:47 +00:00
611450071c
ARM vmla/vmls assembly parsing for the lane index operand.
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llvm-svn: 142389
2011-10-18 18:27:07 +00:00
c8eff0327a
ARM vqdmulh assembly parsing for the lane index operand.
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llvm-svn: 142386
2011-10-18 18:12:09 +00:00
e6fbca3a61
ARM vmul assembly parsing for the lane index operand.
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llvm-svn: 142381
2011-10-18 18:01:52 +00:00
af26d7e280
ARM vqdmlal assembly parsing for the lane index operand.
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llvm-svn: 142365
2011-10-18 17:16:30 +00:00
e4454e0de2
ARM assembly parsing and encoding for VMOV.i64.
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llvm-svn: 142356
2011-10-18 16:18:11 +00:00
8211c051ca
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32.
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llvm-svn: 142321
2011-10-18 00:22:00 +00:00
cda32ae372
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16.
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llvm-svn: 142303
2011-10-17 23:09:09 +00:00
741cd73aab
ARM NEON "vmov.i8" immediate assembly parsing and encoding.
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NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.
llvm-svn: 142293
2011-10-17 22:26:03 +00:00
2ad0dee309
Tidy up organization.
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llvm-svn: 142248
2011-10-17 21:00:11 +00:00
d0637bfc68
ARM NEON assembly parsing and encoding for VDUP(scalar).
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llvm-svn: 141446
2011-10-07 23:56:00 +00:00
61f92efb5c
Remove the VMOVQQ pseudo instruction.
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llvm-svn: 138177
2011-08-20 00:52:40 +00:00
baf5538da9
Remove VMOVQQQQ pseudo instruction.
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llvm-svn: 138174
2011-08-20 00:40:14 +00:00
a6201f0a72
Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness.
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llvm-svn: 137686
2011-08-15 23:38:54 +00:00
b9d82f411c
Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase.
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llvm-svn: 137635
2011-08-15 18:44:44 +00:00
e0152a73c2
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
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This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.
llvm-svn: 137144
2011-08-09 20:55:18 +00:00
8de11bab76
Add missing register constraint for some VLD3/VLD4 pseudo instructions.
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<rdar://problem/9878189>
llvm-svn: 136962
2011-08-05 07:24:09 +00:00
454e1c7abb
Remove VMOVDneon and VMOVQ, which are just aliases for VORR. This continues to simplify the path towards an auto-generated disassembler.
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llvm-svn: 135290
2011-07-15 18:46:47 +00:00
9cf6f8a9b8
Remove unnecessary duplicate instruction definitions that simply overloaded the type of VEXT. This can be achieved with a Pat definition, and is much more disassembler friendly.
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llvm-svn: 135283
2011-07-15 17:48:05 +00:00
7ef7ddd2df
Clean up a few 80 column violations.
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llvm-svn: 132946
2011-06-13 22:54:22 +00:00
f0759ef271
Fix encoding for VEXTdf.
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llvm-svn: 132486
2011-06-02 21:25:24 +00:00
92ff16b7bb
Fixed MC encoding for index_align for VLD1/VST1 (single element from one lane) for size 32
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llvm-svn: 131085
2011-05-09 17:47:27 +00:00
27f3330132
Fixed encoding for VEXTqf
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llvm-svn: 129101
2011-04-07 19:56:12 +00:00
abda3caf67
Somehow we managed to forget to encode the lane index for a large swathe of NEON instructions. With this fix, the entire test-suite passes with the Thumb integrated assembler.
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llvm-svn: 128587
2011-03-30 23:45:29 +00:00
53dd03d537
Add a ARM-specific SD node for VBSL so that forms with a constant first operand
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can be recognized. This fixes <rdar://problem/9183078>.
llvm-svn: 128584
2011-03-30 23:01:21 +00:00
d6c5a741b5
Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually exist.
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llvm-svn: 128461
2011-03-29 16:45:53 +00:00
59eea670f8
ARM VDUPfd and VDUPfq can just be patterns. The instruction is the same
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as for VDUP32d and VDUP32q, respectively.
llvm-svn: 127489
2011-03-11 20:44:08 +00:00
c77dea7f55
ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32q
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and VDUPLN32d, respectively.
llvm-svn: 127486
2011-03-11 20:31:17 +00:00
24fe5e36ea
ARM VREV64df and VREV64qf can just be patterns. The instruction is the same
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as for VREV64d32 and VREV64q32, respectively.
llvm-svn: 127485
2011-03-11 20:18:05 +00:00
5e57137e87
* Correct encoding for VSRI.
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* Add tests for VSRI and VSLI.
llvm-svn: 127297
2011-03-09 00:33:17 +00:00
a7f303de71
Correct the encoding for VRSRA and VSRA instructions.
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llvm-svn: 127294
2011-03-09 00:00:35 +00:00
e313f16ad9
* Fix VRSHR and VSHR to have the correct encoding for the immediate.
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* Update the NEON shift instruction test to expect what 'as' produces.
llvm-svn: 127293
2011-03-08 23:48:09 +00:00
77ad1dc56d
Rename the narrow shift right immediate operands to "shr_imm*" operands. Also
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expand the testing of the narrowing shift right instructions.
No functionality change.
llvm-svn: 127193
2011-03-07 23:38:41 +00:00
3b1459b810
Narrow right shifts need to encode their immediates differently from a normal
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shift.
16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>
llvm-svn: 126723
2011-03-01 01:00:59 +00:00
e3ecd5fb9b
Add patterns to use post-increment addressing for Neon VST1-lane instructions.
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llvm-svn: 126477
2011-02-25 06:42:42 +00:00
a609b8954e
Change VLD3/4 and VST3/4 for quad registers to not update the address register.
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These operations are expanded to pairs of loads or stores, and the first one
uses the address register update to produce the address for the second one.
So far, the second load/store has also updated the address register, just
for convenience, since that output has never been used. In anticipation of
actually supporting post-increment updates for these operations, this changes
the non-updating operations to use a non-updating load/store for the second
instruction.
llvm-svn: 125013
2011-02-07 17:43:15 +00:00
42e67b5f73
Fix some NEON instruction itineraries.
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llvm-svn: 125012
2011-02-07 17:43:12 +00:00
8265d56638
Add ARM patterns to match EXTRACT_SUBVECTOR nodes.
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Also fix an off-by-one in SelectionDAGBuilder that was preventing shuffle
vectors from being translated to EXTRACT_SUBVECTOR.
Patch by Tim Northover.
The test changes are needed to keep those spill-q tests from testing aligned
spills and restores. If the only aligned stack objects are spill slots, we
no longer realign the stack frame. Prior to this patch, an EXTRACT_SUBVECTOR
was legalized by loading from the stack, which created an aligned frame index.
Now, however, there is nothing except the spill slot in the stack frame, so
I added an aligned alloca.
llvm-svn: 122995
2011-01-07 04:59:04 +00:00
eda2a9ec89
Rearrange some Neon multiclasses. No functional changes.
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llvm-svn: 122119
2010-12-18 00:42:58 +00:00
00871c71e9
Fix result type of Neon floating-point comparisons against zero.
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The result vector elements are always integers. Radar 8782191.
llvm-svn: 122112
2010-12-18 00:04:33 +00:00
fa27a8621c
Add Neon VCVT instructions for f32 <-> f16 conversions.
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Clang is now providing intrinsics for these and so we need to support them
in the backend. Radar 8068427.
llvm-svn: 121902
2010-12-15 22:14:12 +00:00
651eaa02b8
Remove the rest of the *_sfp Neon instruction patterns.
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Use the same COPY_TO_REGCLASS approach as for the 2-register *_sfp instructions.
This change made a big difference in the code generated for the
CodeGen/Thumb2/cross-rc-coalescing-2.ll test: The coalescer is still doing
a fine job, but some instructions that were previously moved outside the loop
are not moved now. It's using fewer VFP registers now, which is generally
a good thing, so I think the estimates for register pressure changed and that
affected the LICM behavior. Since that isn't obviously wrong, I've just
changed the test file. This completes the work for Radar 8711675.
llvm-svn: 121730
2010-12-13 23:02:37 +00:00
aae0862172
Simplify N2VSPat, removing some unnecessary type arguments.
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llvm-svn: 121729
2010-12-13 23:02:31 +00:00
9c00c014ab
Delete a line that I forgot to revert previously.
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llvm-svn: 121719
2010-12-13 22:05:55 +00:00
9b3546d877
Use COPY_TO_REGCLASS instead of pseudo instructions for Neon FP patterns.
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Jakob Olesen suggested that we can avoid the need for separate pseudo
instructions here by using COPY_TO_REGCLASS in the patterns. The pattern
gets pretty ugly but it seems to work well. Partial fix for Radar 8711675.
llvm-svn: 121718
2010-12-13 21:58:05 +00:00
157fec42c9
Use pseudo instructions for 2-register Neon instructions for scalar FP.
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Partial fix for Radar 8711675.
llvm-svn: 121716
2010-12-13 21:05:52 +00:00
52f522720e
Remove unused instruction class arguments.
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llvm-svn: 121715
2010-12-13 21:05:44 +00:00
9375d27460
Add float patterns for Neon vld1-lane/dup and vst1-lane operations.
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llvm-svn: 121583
2010-12-10 22:13:32 +00:00
e1d3322111
Remove unused arguments.
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llvm-svn: 121582
2010-12-10 22:13:24 +00:00
62c7b5bf76
Making use of VFP / NEON floating point multiply-accumulate / subtraction is
...
difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
additional pipeline stall. So it's frequently better to single codegen
vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
vmla + vmla is very bad. But this isn't ideal either:
vmul
vadd
vmla
Instead, we want to expand the second vmla:
vmla
vmul
vadd
Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
faster.
Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.
A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
vmla / vmls will trigger one of the special hazards.
Work in progress, only A+B are enabled.
llvm-svn: 120960
2010-12-05 22:04:16 +00:00
371e586544
Fix copy/pasto in vmin.f32 encoding.
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llvm-svn: 120709
2010-12-02 16:30:58 +00:00
4472801765
Use by-name rather than by-order matching for NEON operands.
...
llvm-svn: 120507
2010-12-01 00:28:25 +00:00
318ce7cb3f
Fix the encoding of VLD4-dup alignment.
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The only reasonable way I could find to do this is to provide an alternate
version of the addrmode6 operand with a different encoding function. Use it
for all the VLD-dup instructions for the sake of consistency.
llvm-svn: 120358
2010-11-30 00:00:42 +00:00
0b27b68164
Rename VLDnDUP instructions with double-spaced registers
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in an attempt to make things a little more consistent.
llvm-svn: 120357
2010-11-30 00:00:38 +00:00
431ac4ef50
Add support for NEON VLD3-dup instructions.
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The encoding for alignment in VLD4-dup instructions is still a work in progress.
llvm-svn: 120356
2010-11-30 00:00:35 +00:00
77ab165afe
Add support for NEON VLD3-dup instructions.
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llvm-svn: 120312
2010-11-29 19:35:29 +00:00
2d790df105
Add support for NEON VLD2-dup instructions.
...
llvm-svn: 120236
2010-11-28 06:51:26 +00:00
04b2c94205
Another minor refactoring for VLD1DUP instructions.
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The op11_8 field is the same for all of them so put it in the instruction
classes instead of specifying it separately for each instruction.
llvm-svn: 120234
2010-11-28 06:51:15 +00:00
d74cf2c8f6
Refactor. Set alignment bit in VLD1-dup instruction classes.
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llvm-svn: 120197
2010-11-27 07:12:02 +00:00
c92eea0175
Add NEON VLD1-dup instructions (load 1 element to all lanes).
...
llvm-svn: 120194
2010-11-27 06:35:16 +00:00
7e484e0be7
Use by-name rather than by-order operand matching for some NEON encodings.
...
llvm-svn: 119923
2010-11-21 06:47:06 +00:00
b4fd2c90e9
The Vm and Vn register fields must be the same for a register-register vmov.
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llvm-svn: 119867
2010-11-19 23:12:43 +00:00
785952e5ac
Operand names
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llvm-svn: 119864
2010-11-19 22:43:08 +00:00
7d8df3185f
Clarify operand names.
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llvm-svn: 119858
2010-11-19 22:36:02 +00:00
9c335bf977
Remove trailing whitespace.
...
llvm-svn: 119608
2010-11-18 01:39:50 +00:00
a74c7ccd59
ARM PseudoInst instructions don't need or use an assembler string. Get rid of
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the operand to the pattern.
llvm-svn: 119607
2010-11-18 01:38:26 +00:00
a68e3a5397
Encode the multi-load/store instructions with their respective modes ('ia',
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'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>
llvm-svn: 119310
2010-11-16 01:16:36 +00:00
c7baee31ad
Add support for ARM's specialized vector-compare-against-zero instructions.
...
llvm-svn: 118453
2010-11-08 23:21:22 +00:00
30c4892ea5
Add codegen and encoding support for the immediate form of vbic.
...
llvm-svn: 118291
2010-11-05 19:27:46 +00:00
0747307049
Add support for code generation of the one register with immediate form of vorr.
...
We could be more aggressive about making this work for a larger range of constants,
but this seems like a good start.
llvm-svn: 118201
2010-11-03 22:44:51 +00:00
bb81f80af6
Unlike a lot of NEON instructions, vext isn't _actually_ parameterized by element size. Instead,
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all of the different element sizes are pseudo instructions that map down to vext.8 underneath, with
the immediate shifted left to reflect the increased element size.
llvm-svn: 118183
2010-11-03 18:16:27 +00:00
7d0ac84abd
Add codegen patterns for VST1-lane instructions. Radar 8599955.
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llvm-svn: 118176
2010-11-03 16:24:53 +00:00
c6af2b4066
Break ARM addrmode4 (load/store multiple base address) into its constituent
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parts. Represent the operation mode as an optional operand instead.
rdar://8614429
llvm-svn: 118137
2010-11-03 01:01:43 +00:00
0ebd1fd594
Revert r118097 to fix buildbots.
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llvm-svn: 118121
2010-11-02 23:47:29 +00:00
7c30390277
Since these fields are not exactly equivalent to the encoded field, rename them to something with semantic meaning.
...
llvm-svn: 118097
2010-11-02 22:41:42 +00:00
dec87e10fd
Provide correct encodings for the remaining vst variants that we currently generate.
...
llvm-svn: 118087
2010-11-02 22:18:18 +00:00
adf88d4c5f
Tentative encodings for the "single element from one lane" variant of vst1.
...
llvm-svn: 118084
2010-11-02 21:54:45 +00:00
b95618cfe0
Add correct encodings for basic variants for vst3 and vst4.
...
llvm-svn: 118082
2010-11-02 21:47:03 +00:00
d80b29d6f7
Add NEON VST1-lane instructions. Partial fix for Radar 8599955.
...
llvm-svn: 118069
2010-11-02 21:18:25 +00:00
fa08e1e277
Add correct encodings for the basic variants for vst2.
...
llvm-svn: 118068
2010-11-02 21:16:58 +00:00
87c62e54e6
Add correct encodings for the basic form of vst1.
...
llvm-svn: 118067
2010-11-02 21:06:06 +00:00
9f20daf3b4
Factor out a common encoding class for loads and stores with a lane parameter.
...
llvm-svn: 118055
2010-11-02 20:47:39 +00:00
a83859539f
Add correct encodings for the rest of the vld instructions that we generate.
...
llvm-svn: 118053
2010-11-02 20:40:59 +00:00
526ffd57d2
Add correct NEON encodings for vld2, vld3, and vld4 basic variants.
...
llvm-svn: 117997
2010-11-02 01:24:55 +00:00
b3ca2060c0
Attempt to provide correct encodings for a number of other vld1 variants, which we can't test
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since we can neither generate nor parse them at the moment.
llvm-svn: 117988
2010-11-02 00:24:52 +00:00
ad40234eff
Add correct NEON encodings for the "multiple single elements" form of vld.
...
llvm-svn: 117984
2010-11-02 00:05:05 +00:00
dc44990c7d
Add NEON VLD1-lane instructions. Partial fix for Radar 8599955.
...
llvm-svn: 117964
2010-11-01 22:04:05 +00:00
2ef668840a
Add correct NEON encodings for vtbl and vtbx.
...
llvm-svn: 117513
2010-10-28 00:18:46 +00:00
14be930317
Add correct NEON encodings for vext, vtrn, vuzp, and vzip.
...
llvm-svn: 117512
2010-10-27 23:56:39 +00:00
fadb951e5b
Provide correct encodings for NEON vcvt, which has its own special immediate encoding
...
for specifying fractional bits for fixed point conversions.
llvm-svn: 117501
2010-10-27 22:49:00 +00:00
ed9652f959
Provide correct encodings for the get_lane and set_lane variants of vmov.
...
llvm-svn: 117495
2010-10-27 21:28:09 +00:00
40d24a4abf
Provide correct NEON encodings for vdup.
...
llvm-svn: 117475
2010-10-27 19:25:54 +00:00
8576a42cf3
Add correct NEON encodings for vsli and vsri.
...
llvm-svn: 117459
2010-10-27 17:40:08 +00:00
d7e8135e1e
Add correct NEON encodings for vsra and vrsra.
...
llvm-svn: 117458
2010-10-27 17:29:29 +00:00
825b2d1946
Add correct NEON encodings for vqshl, vqshrn, vqshrun, vqrshl, vqshrn, and vqrshrun.
...
llvm-svn: 117411
2010-10-26 22:50:46 +00:00
2888e2c7f9
Correct NEON encodings for vshrn, vrshl, vrshr, vrshrn.
...
llvm-svn: 117402
2010-10-26 21:58:41 +00:00
e18579976f
Simplify classes for shift instructions, which are never commutable.
...
llvm-svn: 117398
2010-10-26 21:13:59 +00:00
3665fee8de
Provide correct NEON encodings for vshl, register and immediate forms.
...
llvm-svn: 117394
2010-10-26 20:56:57 +00:00
691ce68d3c
Add correct NEON encoding for vpadal.
...
llvm-svn: 117380
2010-10-26 18:18:03 +00:00
284cb361d1
Add NEON encodings for vmov and vmvn of immediates.
...
llvm-svn: 117374
2010-10-26 17:40:54 +00:00
1f6aad053d
Add correct encodings for NEON vabal.
...
llvm-svn: 117315
2010-10-25 21:29:04 +00:00
b9c91679aa
Add correct NEON encodings for vaba.
...
llvm-svn: 117309
2010-10-25 20:52:57 +00:00
dd001b89d7
Attempt to provide correct encodings for NEON vbit and vbif, even though we can't test them at the moment.
...
llvm-svn: 117294
2010-10-25 20:17:22 +00:00
dea09c7564
Provide correct NEON encodings for vbsl.
...
llvm-svn: 117293
2010-10-25 20:13:13 +00:00
2477446ee5
Add correct instruction encodings for vbic, vorn, and vmvn.
...
llvm-svn: 117282
2010-10-25 18:43:52 +00:00
feb3ee0c93
Add NEON encoding tests for vcgt and vacgt.
...
llvm-svn: 117276
2010-10-25 18:03:59 +00:00
e5d0677173
Add tests for NEON encodings of vcge and vacge.
...
llvm-svn: 117274
2010-10-25 17:49:32 +00:00
c178b80f65
Add a warning about our inability to test the encoding of vceq with immediate zero.
...
llvm-svn: 117273
2010-10-25 17:33:02 +00:00
9d0122af7d
Add correct NEON encodings for vqdmlal.
...
llvm-svn: 117134
2010-10-22 19:35:48 +00:00
3d0264667f
Provide correct encodings for NEON vmlal.
...
llvm-svn: 117131
2010-10-22 19:05:25 +00:00
f48719f1b5
Provide correct NEON encodings for vmla.
...
llvm-svn: 117126
2010-10-22 18:54:37 +00:00
9e44cf2bb2
ARM encodes Q registers as 2xregno (i.e. the number of the D register that corresponds to the lower
...
half of the Q register), rather than with just regno. This allows us to unify the encodings for
a lot of different NEON instrucitons that differ only in whether they have Q or D register operands.
llvm-svn: 117056
2010-10-21 20:21:49 +00:00
6b7e401049
Add correct NEON encodings for vhadd and vrhadd.
...
llvm-svn: 117047
2010-10-21 18:55:04 +00:00
9561084188
Add correct encodings for NEON vaddw.s* and vaddw.u*.
...
llvm-svn: 117040
2010-10-21 18:20:25 +00:00
15c97706e8
Provide correct NEON encodings for vaddl.u* and vaddl.s*.
...
llvm-svn: 117039
2010-10-21 18:09:17 +00:00
6083502848
Implement correct encodings for NEON vadd, both integer and floating point.
...
llvm-svn: 116981
2010-10-21 00:48:00 +00:00
340cd5174b
A few 80 column fixes.
...
llvm-svn: 116451
2010-10-13 23:34:31 +00:00
e790afcbe1
More ARM scheduling itinerary fixes.
...
llvm-svn: 116266
2010-10-11 23:41:41 +00:00
94ad008beb
Proper VST scheduling itineraries.
...
llvm-svn: 116251
2010-10-11 22:03:18 +00:00
d7a404d85f
Add VLD4 scheduling itineraries.
...
llvm-svn: 116143
2010-10-09 04:07:58 +00:00
a762400bed
Finish vld3 and vld4.
...
llvm-svn: 116140
2010-10-09 01:45:34 +00:00
05f13e94bf
Correct some load / store instruction itinerary mistakes:
...
1. Cortex-A8 load / store multiplies can only issue on ALU0.
2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues.
3. Correctly model all vld1 and vld2 variants.
llvm-svn: 116134
2010-10-09 01:03:04 +00:00
1958cefd69
Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vldr / vstr, etc.
...
llvm-svn: 115898
2010-10-07 01:50:48 +00:00
2e3e2a006b
Change the NEON VDUPfdf and VDUPfqf pseudo-instructions to actually be
...
pseudo instructions.
llvm-svn: 115840
2010-10-06 21:16:16 +00:00
233b3a2f95
Add a 'pattern' arg to the ARM PseudoNeonI class.
...
llvm-svn: 115831
2010-10-06 20:36:55 +00:00
fae8305e2b
Nuke the rest of the :comment references
...
llvm-svn: 115373
2010-10-01 23:21:38 +00:00
1969887fc6
Fix scheduling infor for vmovn and vshrn which I broke accidentially.
...
llvm-svn: 115354
2010-10-01 21:48:06 +00:00
2a5d764858
NEON scheduling info fix. vmov reg, reg are single cycle instructions.
...
llvm-svn: 115344
2010-10-01 20:50:58 +00:00
6b853c3ce3
Change VLDMQ and VSTMQ to be pseudo instructions. They are expanded after
...
register allocation to VLDMD and VSTMD respectively. This avoids using the
dregpair operand modifier.
llvm-svn: 114047
2010-09-16 00:31:02 +00:00
b1e9d4bff1
Use VLD1/VST1 pseudo instructions for loadRegFromStackSlot and
...
storeRegToStackSlot.
llvm-svn: 113918
2010-09-15 01:48:05 +00:00
c7cf42d80b
Reapply r113875 with additional cleanups.
...
"The register specified for a dregpair is the corresponding Q register, so to
get the pair, we need to look up the sub-regs based on the qreg. Create a
lookup function since we don't have access to TargetRegisterInfo here to
be able to use getSubReg(ARM::dsub_[01])."
Additionaly, fix the NEON VLD1* and VST1* instruction patterns not to use
the dregpair modifier for the 2xdreg versions. Explicitly specifying the two
registers as operands is more correct and more consistent with the other
instruction patterns. This enables further cleanup of special case code in the
disassembler as a nice side-effect.
llvm-svn: 113903
2010-09-14 23:54:06 +00:00
dd29db5635
Make NEON ld/st pseudo instruction classes take the instruction itinerary as
...
an argument, so that we can distinguish instructions with the same register
classes but different numbers of registers (e.g., vld3 and vld4). Fix some
of the non-pseudo NEON ld/st instruction itineraries to reflect the number
of registers loaded or stored, not just the opcode name.
llvm-svn: 113854
2010-09-14 20:59:49 +00:00
c597fd3b4a
Convert some VTBL and VTBX instructions to use pseudo instructions prior to
...
register allocation. Remove the NEONPreAllocPass, which is no longer needed.
Yeah!!
llvm-svn: 113818
2010-09-13 23:55:10 +00:00
d5c57a5ed4
Switch all the NEON vld-lane and vst-lane instructions over to the new
...
pseudo-instruction approach. Change ARMExpandPseudoInsts to use a table
to record all the NEON load/store information.
llvm-svn: 113812
2010-09-13 23:01:35 +00:00
4adbaf1843
Fix NEON VLD pseudo instruction itineraries that were incorrectly copied from
...
the VST pseudos. The VLD/VST scheduling still needs work (see pr6722), but
at least we shouldn't confuse the loads with the stores.
llvm-svn: 113473
2010-09-09 05:40:26 +00:00
abcbe2474d
VFP/NEON load/store multiple instructions are addrmode4, not 5.
...
llvm-svn: 113322
2010-09-08 00:25:50 +00:00
35fafca587
Finish converting the rest of the NEON VLD instructions to use pseudo-
...
instructions prior to regalloc. Since it's getting a little close to
the 2.8 branch deadline, I'll have to leave the rest of the instructions
handled by the NEONPreAllocPass for now, but I didn't want to leave half
of the VLD instructions converted and the other half not.
llvm-svn: 112983
2010-09-03 18:16:02 +00:00
f65c9ef720
Replace NEON vabdl, vaba, and vabal intrinsics with combinations of the
...
vabd intrinsic and add and/or zext operations. In the case of vaba, this
also avoids the need for a DAG combine pattern to combine vabd with add.
Update tests. Auto-upgrade the old intrinsics.
llvm-svn: 112941
2010-09-03 01:35:08 +00:00
75a6408f88
Convert VLD1 and VLD2 instructions to use pseudo-instructions until
...
after regalloc.
llvm-svn: 112825
2010-09-02 16:00:54 +00:00
38ab35a911
Remove NEON vmull, vmlal, and vmlsl intrinsics, replacing them with multiply,
...
add, and subtract operations with zero-extended or sign-extended vectors.
Update tests. Add auto-upgrade support for the old intrinsics.
llvm-svn: 112773
2010-09-01 23:50:19 +00:00
4cd8a126c3
Remove NEON vmovn intrinsic, replacing it with vector truncate operations.
...
Auto-upgrade the old intrinsic and update tests.
llvm-svn: 112507
2010-08-30 20:02:30 +00:00
d0c054886c
Remove NEON vaddl, vaddw, vsubl, and vsubw intrinsics. Instead, use llvm
...
IR add/sub operations with one or both operands sign- or zero-extended.
Auto-upgrade the old intrinsics.
llvm-svn: 112416
2010-08-29 05:57:34 +00:00
950882be07
Use pseudo instructions for VST1 and VST2.
...
llvm-svn: 112357
2010-08-28 05:12:57 +00:00
8ee9394750
We don't need to custom-select VLDMQ and VSTMQ anymore.
...
llvm-svn: 112336
2010-08-28 00:20:11 +00:00
13ce07fa92
Change ARM VFP VLDM/VSTM instructions to use addressing mode #4 , just like
...
all the other LDM/STM instructions. This fixes asm printer crashes when
compiling with -O0. I've changed one of the NEON tests (vst3.ll) to run
with -O0 to check this in the future.
Prior to this change VLDM/VSTM used addressing mode #5 , but not really.
The offset field was used to hold a count of the number of registers being
loaded or stored, and the AM5 opcode field was expanded to specify the IA
or DB mode, instead of the standard ADD/SUB specifier. Much of the backend
was not aware of these special cases. The crashes occured when rewriting
a frameindex caused the AM5 offset field to be changed so that it did not
have a valid submode. I don't know exactly what changed to expose this now.
Maybe we've never done much with -O0 and NEON. Regardless, there's no longer
any reason to keep a count of the VLDM/VSTM registers, so we can use
addressing mode #4 and clean things up in a lot of places.
llvm-svn: 112322
2010-08-27 23:18:17 +00:00
97919e9c59
Use pseudo instructions for VST3.
...
llvm-svn: 112208
2010-08-26 18:51:29 +00:00
4cec44975e
Use pseudo instructions for VST1d64Q.
...
llvm-svn: 112170
2010-08-26 05:33:30 +00:00
9392b0e960
Start converting NEON load/stores to use pseudo instructions, beginning here
...
with the VST4 instructions. Until after register allocation, we want to
represent sets of adjacent registers by a single super-register. These
VST4 pseudo instructions have a single QQ or QQQQ source register operand.
They get expanded to the real VST4 instructions with 4 separate D register
operands. Once this conversion is complete, we'll be able to remove the
NEONPreAllocPass and avoid some fragile and hacky code elsewhere.
llvm-svn: 112108
2010-08-25 23:27:42 +00:00
9a511c07e4
Replace the arm.neon.vmovls and vmovlu intrinsics with vector sign-extend and
...
zero-extend operations.
llvm-svn: 111614
2010-08-20 04:54:02 +00:00
727be43a3d
Silence some -Asserts uninitialized variable warnings.
...
llvm-svn: 109956
2010-07-31 21:08:54 +00:00
bad47f62f6
Add support for NEON VMVN immediate instructions.
...
llvm-svn: 108324
2010-07-14 06:31:50 +00:00
bd54a53628
The bits in the cmode field of 32-bit VMOV immediate instructions all depend
...
of the value of the immediate.
llvm-svn: 108323
2010-07-14 06:30:44 +00:00
a3f1901531
Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to represent
...
NEON VMOV-immediate instructions. This simplifies some things.
llvm-svn: 108275
2010-07-13 21:16:48 +00:00
5bc8a79e7f
Also use REG_SEQUENCE for VTBX instructions.
...
llvm-svn: 107743
2010-07-07 00:08:54 +00:00
3ed511bc6b
Use REG_SEQUENCE nodes to make the table registers for VTBL instructions be
...
allocated to consecutive registers.
llvm-svn: 107730
2010-07-06 23:36:25 +00:00
574f68f815
Fix indentation.
...
llvm-svn: 106881
2010-06-25 20:54:44 +00:00
6d12973143
Remove a fixme comment that is no longer relevant.
...
llvm-svn: 106382
2010-06-19 05:32:41 +00:00
f3f7a770b7
Add basic support for NEON modified immediates besides VMOV.
...
llvm-svn: 106030
2010-06-15 19:05:35 +00:00
5b2b504038
Rename functions referring to VMOV immediates to refer to NEON "modified
...
immediate" operands. These functions have so far only been used for VMOV
but they also apply to other NEON instructions with modified immediate
operands. No functional changes.
llvm-svn: 105969
2010-06-14 22:19:57 +00:00
6eae520de9
Add instruction encoding for the Neon VMOV immediate instruction. This changes
...
the machine instruction representation of the immediate value to be encoded
into an integer with similar fields as the actual VMOV instruction. This makes
things easier for the disassembler, since it can just stuff the bits into the
immediate operand, but harder for the asm printer since it has to decode the
value to be printed. Testcase for the encoding will follow later when MC has
more support for ARM.
llvm-svn: 105836
2010-06-11 21:34:50 +00:00
846bd7992c
Further changes for Neon vector shuffles:
...
- change isShuffleMaskLegal to show that all shuffles with 32-bit and 64-bit
elements are legal
- the Neon shuffle instructions do not support 64-bit elements, but we were
not checking for that before lowering shuffles to use them
- remove some 64-bit element vduplane patterns that are no longer needed
llvm-svn: 105586
2010-06-07 23:53:38 +00:00
8d042c0269
Fix a few places that depended on the numeric value of subreg indices.
...
Add assertions in places that depend on consecutive indices.
llvm-svn: 104510
2010-05-24 17:13:28 +00:00
6c47d6423c
Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums
...
from ARMRegisterInfo.h
llvm-svn: 104508
2010-05-24 16:54:32 +00:00
dd7f566597
Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects.
...
llvm-svn: 104111
2010-05-19 06:07:03 +00:00
cd04ed3533
vmov of immediates are trivially re-materializable.
...
llvm-svn: 103982
2010-05-17 21:54:50 +00:00
497d831966
Chris said that the comment char should be escaped. Fix all the occurences of "@" in *.td
...
llvm-svn: 103903
2010-05-16 09:15:36 +00:00
cd67c21407
Added a QQQQ register file to model 4-consecutive Q registers.
...
llvm-svn: 103760
2010-05-14 02:13:41 +00:00
9de7cfe3f4
Bring back VLD1q and VST1q and use them for reloading / spilling Q registers. This allows folding loads and stores into VMOVQ.
...
llvm-svn: 103692
2010-05-13 01:12:06 +00:00
79efd71962
Mark some pattern-less instructions as neverHasSideEffects.
...
llvm-svn: 103683
2010-05-13 00:16:46 +00:00
86eb22976f
Use VLD2q32 / VST2q32 to reload / spill QQ (pair of Q) registers when stack slot is sufficiently aligned. Use VLDMD / VSTMD otherwise.
...
llvm-svn: 103235
2010-05-07 02:04:02 +00:00
ddc93c7e04
Remove VLD1q and VST1q for reloading and spilling Q registers. Just use VLD1q64 / VST1q64 and reference sub-registers.
...
llvm-svn: 103218
2010-05-07 00:24:52 +00:00
31cdcd46d6
Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170.
...
llvm-svn: 103172
2010-05-06 06:36:08 +00:00
9feb1bb117
Revert r103156 since it was breaking the build bots.
...
Reverse-merging r103156 into '.':
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/ARMRegisterInfo.h
U lib/Target/ARM/ARMBaseRegisterInfo.cpp
U lib/Target/ARM/ARMBaseInstrInfo.cpp
U lib/Target/ARM/ARMRegisterInfo.td
llvm-svn: 103159
2010-05-06 02:29:06 +00:00
8f99a1c6b4
Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q registers. These will be used to model VLD2 / VST2 instructions in order to get substantially better codegen for them.
...
llvm-svn: 103156
2010-05-06 01:52:03 +00:00
4d36f8890f
More fixes for itins
...
llvm-svn: 100662
2010-04-07 18:21:10 +00:00
ceb54d5ab0
Fix invalid itins for 32-bit varians of VMLAL and friends
...
llvm-svn: 100661
2010-04-07 18:21:04 +00:00
a248becd6c
Fix itins for VABA
...
llvm-svn: 100657
2010-04-07 18:20:42 +00:00
a3e4989ad8
Correct VMVN itinerary: operand is read in the second cycle, not in the first.
...
llvm-svn: 100656
2010-04-07 18:20:36 +00:00
140a65ce0b
More A9 itineraries
...
llvm-svn: 100655
2010-04-07 18:20:29 +00:00
1a1af5a830
Correct itinerary class for VPADD
...
llvm-svn: 100654
2010-04-07 18:20:24 +00:00
4650fd5fc6
VP{MAX, MIN} are of IIC_VSUBi4D itin class as well.
...
llvm-svn: 100653
2010-04-07 18:20:18 +00:00
7d4fad5942
VHADD differs from VHSUB at least on A9 - the former reads both operands in the second cycle, while the latter reads second operand in first cycle. Introduce new itin classes to catch this behavior. Whether this is true for A8 as well is WIP.
...
llvm-svn: 100652
2010-04-07 18:20:13 +00:00
c86256fa5d
Add NVTBLFrm to represent A8.6.406 VTBL, VTBX Vector Table Lookup Instructions.
...
These instructions use byte index in a control vector (M:Vm) to lookup byte
values in a table and generate a new vector (D:Vd). The table is specified via
a list of vectors, which can be:
{Dn}
{Dn D<n+1>}
{Dn D<n+1> D<n+2>}
{Dn D<n+1> D<n+2> D<n+3>}
llvm-svn: 99789
2010-03-29 01:14:22 +00:00
3dad5fbeb9
fix integer negates to use the proper type for the zero vectors,
...
this also depends on the new "bitconvert dropping" behavior just
added to tblgen.
llvm-svn: 99757
2010-03-28 08:39:10 +00:00
6c223ee0e9
fix vnot matching to explicitly specify the type of the
...
input to be v8i8 or v16i8, which buildvectors get canonicalized to.
This allows the patterns that were previously using a bare 'vnot' to
match, before they couldn't.
llvm-svn: 99754
2010-03-28 08:08:07 +00:00
0f8a02830a
Fix indentation.
...
llvm-svn: 99705
2010-03-27 04:01:23 +00:00
cf603fb1c5
Add a format argument to the N3V and N3VX classes, removing the N3Vf class.
...
llvm-svn: 99704
2010-03-27 03:56:52 +00:00
6094cdab9f
Add NVMulSLFrm to represent "3-register multiply with scalar" operations and set
...
it as the format for the appropriate N3V*SL*<> classes. These instructions
require special handling of the M:Vm field which encodes the restricted Dm and
the lane index within Dm.
Examples are A8.6.325 VMLA, VMLAL, VMLS, VMLSL (by scalar):
vmlal.s32 q3, d2, d10[0]
llvm-svn: 99690
2010-03-27 01:03:13 +00:00
93acfbf441
Remove the duplicate multiclass N3VSh_QHSD and use N3VInt_QHSD which is modified
...
to now take a format argument. N3VDInt<> and N3VQInt<> are modified to take a
format argument as well.
llvm-svn: 99676
2010-03-26 23:49:07 +00:00
0b57de3c4c
Add NVExtFrm to represent NEON Vector Extract Instructions, that uses Inst{11-8}
...
to encode the byte location of the extracted result in the concatenation of the
operands, from the least significant end.
Modify VEXTd and VEXTq classes to use the format.
llvm-svn: 99659
2010-03-26 22:28:56 +00:00
2cf04957c2
Add N3RegVShFrm to represent 3-Register Vector Shift Instructions, which do not
...
follow the N3RegFrm's operand order of D:Vd N:Vn M:Vm. The operand order of
N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the first src operand).
Add a parent class N3Vf which requires passing a Format argument and which the
N3V class is modified to inherit from. N3V class represents the "normal"
3-Register NEON Instructions with N3RegFrm.
Also add a multiclass N3VSh_QHSD to represent clusters of NEON 3-Register Shift
Instructions and replace 8 invocations with it.
llvm-svn: 99655
2010-03-26 21:26:28 +00:00
5d4e917d9f
Add N2RegVShLFrm and N2RegVShRFrm formats so that the disassembler can easily
...
dispatch to the appropriate routines to handle the different interpretations of
the shift amount encoded in the imm6 field. The Vd, Vm fields are interpreted
the same between the two, though.
See, for example, A8.6.367 VQSHL, VQSHLU (immediate) for N2RegVShLFrm format and
A8.6.368 VQSHRN, VQSHRUN for N2RegVShRFrm format.
llvm-svn: 99590
2010-03-26 01:07:59 +00:00
d82f9002e4
Add NVCVTFrm (NEON Convert with fractional bits immediate) and modify N2VImm to
...
expect a Format arg. N2VCvtD/N2VCvtQ are modified to use the NVCVTFrm format.
llvm-svn: 99548
2010-03-25 20:39:04 +00:00
45ab3f3ccf
Added a new instruction class NVDupLane to be inherited by VDUPLND and VDUPLNQ,
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instead of the current N2V. Format of NVDupLane instances are set to NEONFrm
currently.
llvm-svn: 99518
2010-03-25 17:01:27 +00:00
bff23ca690
Trivial formating change.
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llvm-svn: 99428
2010-03-24 21:25:07 +00:00
e99953ce9c
Reverted r99326 which added NVdVmVCVTFrm, and later renamed to NVCVTFrm.
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NVCVTFrm will later be used to describe "vcvt with fractional bits".
llvm-svn: 99415
2010-03-24 19:47:14 +00:00
da44d5977f
Reverted r99376. The disassembler will deal with the 2-reg format of these two
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N3VX instructions using special case code.
llvm-svn: 99409
2010-03-24 18:46:34 +00:00
aa9b1c81a7
Mark VMOVDneon and VMOVQ as having the N2RegFrm form to help the disassembler.
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llvm-svn: 99376
2010-03-24 01:29:25 +00:00
9b1f60adec
Renamed NVdVmImmFrm and NVdVmVCVTFrm to the more proper N2RegFrm and NVCVTFrm,
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respectively, and add some more comment.
llvm-svn: 99373
2010-03-24 00:57:50 +00:00
5be6d5a6a9
Add comment.
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llvm-svn: 99327
2010-03-23 21:30:12 +00:00
5dbf39285d
Add New NEON Format NVdVmVCVTFrm.
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Converted some of the NEON vcvt instructions to this format.
llvm-svn: 99326
2010-03-23 21:25:38 +00:00
59f75bba24
Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes.
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These instructions are only needed for codegen, so I've removed all the
explicit encoding bits for now; they should be set in the same way as the for
VLDMD and VSTMD whenever we add encodings for VFP. The use of addrmode5
requires that the instructions be custom-selected so that the number of
registers can be set in the AM5Opc value.
llvm-svn: 99309
2010-03-23 18:54:46 +00:00
9b680e21c0
Rename some instructions to match the corresponding NEON opcode.
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llvm-svn: 99266
2010-03-23 06:26:18 +00:00
cc0a2a75a0
Change VST1 instructions for loading Q register values to operate on pairs
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of D registers. Add a separate VST1q instruction with a Q register
source operand for use by storeRegToStackSlot.
llvm-svn: 99265
2010-03-23 06:20:33 +00:00
340861d29e
Change VLD1 instructions for loading Q register values to operate on pairs
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of D registers. Add a separate VLD1q instruction with a Q register
destination operand for use by loadRegFromStackSlot.
llvm-svn: 99261
2010-03-23 05:25:43 +00:00
e60e3ab624
Rename one more NEON instruction that I missed earlier.
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llvm-svn: 99201
2010-03-22 20:31:39 +00:00
c286c88db0
Regroup some instructions. No functional change.
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llvm-svn: 99192
2010-03-22 18:22:06 +00:00
c53a1125ff
Rename some VLD1/VST1 instructions to match the implementation, i.e., the
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corresponding NEON instructions, instead of operation they are currently
used for.
llvm-svn: 99189
2010-03-22 18:13:18 +00:00
98bf5189d7
Remove some redundant instruction classes.
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llvm-svn: 99187
2010-03-22 18:02:38 +00:00
debe0bdb13
Refactor instruction encoding arguments for VLDnLN/VSTnLN classes to
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specify encoding bits in arguments instead of "let" expressions.
llvm-svn: 99185
2010-03-22 16:43:10 +00:00
ae08a736d6
Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6")
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with changes to add a separate optional register update argument. Change all
the NEON instructions with address register writeback to use it.
llvm-svn: 99095
2010-03-20 22:13:40 +00:00
59e5141d44
Add instruction variants for VST2, VST3, and VST4 "store-lane" operations with
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address register writeback.
llvm-svn: 99094
2010-03-20 21:57:36 +00:00
b18adef4ad
Add variants of VST2, VST3 and VST4 with address register writeback, and
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rewrite the existing VST3 and VST4 instructions to use the same classes as
the others.
llvm-svn: 99093
2010-03-20 21:45:18 +00:00
89ba42c4ce
Add instructions for double-spaced VST3 and VST4 without address register
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writeback, and refactor the existing double-spaced VST2 instructions.
These are only for the disassembler since codegen doesn't use them, at
least for now.
llvm-svn: 99090
2010-03-20 21:15:48 +00:00
322cbff3d3
Add VST1 instructions with address register writeback.
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llvm-svn: 99083
2010-03-20 20:54:36 +00:00
9152d96dfb
Add instruction variants for VLD2, VLD3, and VLD4 "load-lane" operations with
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address register writeback.
llvm-svn: 99082
2010-03-20 20:47:18 +00:00
9b1584245a
Tidy some more comments and whitespace.
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llvm-svn: 99081
2010-03-20 20:39:53 +00:00
cf324658f6
Add variants of VLD2, VLD3 and VLD4 with address register writeback, and
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rewrite the existing VLD3 and VLD4 instructions to use the same classes as
the others.
llvm-svn: 99080
2010-03-20 20:10:51 +00:00
7ee900da22
Tidy some comments and whitespace for consistency.
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llvm-svn: 99078
2010-03-20 19:57:03 +00:00
Jim Grosbach