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10 Commits

Author SHA1 Message Date
Jan Vesely f97de00745 AMDGPU/R600: Implement memory loads from constant AS 
Reviewers: tstellard

Subscribers: arsenm

Differential Revision: http://reviews.llvm.org/D19792

llvm-svn: 269479
 2016-05-13 20:39:29 +00:00
Matt Arsenault 79963e80b8 AMDGPU: Rename intrinsic to better match instruction name 
Also fixes missing f32 test.

llvm-svn: 260780
 2016-02-13 01:03:00 +00:00
Matt Arsenault 295875efda AMDGPU: Remove 24-bit intrinsics 
The known bit matching code seems to work reasonably well,
so these shouldn't really be needed.

llvm-svn: 259180
 2016-01-29 10:05:16 +00:00
Matt Arsenault 7713162c32 AMDGPU: Remove more unused intrinsics 
Replace tests with lrp with basic IR expansion

llvm-svn: 258612
 2016-01-23 05:42:38 +00:00
Matt Arsenault ee0930821a AMDGPU: Remove random TGSI intrinsic 
I don't think this was ever used.

llvm-svn: 258514
 2016-01-22 18:42:44 +00:00
Matt Arsenault 0cbaa1762b AMDGPU: Remove AMDGPU.fract intrinsic 
Mesa doesn't use this, and this is pattern matched already
from fsub x, (ffloor x)

llvm-svn: 258513
 2016-01-22 18:42:38 +00:00
Bruce Mitchener e9ffb45b60 Fix typos. 
Summary: This fixes a variety of typos in docs, code and headers.

Subscribers: jholewinski, sanjoy, arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D12626

llvm-svn: 247495
 2015-09-12 01:17:08 +00:00
Tom Stellard 45bb48ea19 R600 -> AMDGPU rename 
llvm-svn: 239657
 2015-06-13 03:28:10 +00:00
Tom Stellard 1be1aa84ec Revert "AMDGPU: Add core backend files for R600/SI codegen v6" 
This reverts commit 4ea70107c5e51230e9e60f0bf58a0f74aa4885ea.

llvm-svn: 160303
 2012-07-16 18:19:53 +00:00
Tom Stellard bcce80fa95 AMDGPU: Add core backend files for R600/SI codegen v6 
llvm-svn: 160270
 2012-07-16 14:17:08 +00:00