Commit Graph

44 Commits

Author SHA1 Message Date
Akira Hatanaka 06aff571a3 [mips] Define a pseudo instruction which writes to both the lower and higher
parts of the accumulators and gets expanded post-RA.

llvm-svn: 192667
2013-10-15 01:48:30 +00:00
Akira Hatanaka ec67c90216 [mips] Use predicates to guard instructions using accumulator registers instead
of relying on AddedComplexity.

llvm-svn: 192665
2013-10-15 01:21:37 +00:00
Akira Hatanaka d98c99fd01 [mips] Rename isel nodes.
llvm-svn: 192663
2013-10-15 01:12:50 +00:00
Akira Hatanaka 16048332f1 [mips] Fix definition of mfhi and mflo instructions to read from the whole
accumulator instead of its sub-registers, $hi and $lo. 

We need this change to prevent a mflo following a mtlo from reading an
unpredictable/undefined value, as shown in the following example:

mult $6, $7 // result of $6 * $7 is written to $lo and $hi.
mflo $2     // read lower 32-bit result from $lo.
mtlo $4     // write to $lo. the content of $hi becomes unpredictable.
mfhi $3     // read higher 32-bit from $hi, which has an unpredictable value.

I don't have a test case for this change that reliably reproduces the problem.

llvm-svn: 192119
2013-10-07 18:49:46 +00:00
Akira Hatanaka 3121353c99 [mips] Use uimm5 and uimm6 instead of shamt and imm, if the immediate has to fit
into a 5-bit or 6-bit field.

llvm-svn: 190226
2013-09-07 00:02:02 +00:00
Akira Hatanaka 9bfa2e2e7f [mips] Use ptr_rc to simplify definitions of base+index load/store instructions.
Also, fix predicates.

llvm-svn: 189432
2013-08-28 00:55:15 +00:00
Akira Hatanaka 6781fc1648 [mips] Resolve register classes dynamically using ptr_rc to reduce the number of
load/store instructions defined. Previously, we were defining load/store
instructions for each pointer size (32 and 64-bit), but now we need just one
definition.

llvm-svn: 188830
2013-08-20 21:08:22 +00:00
Akira Hatanaka feb7ee84c5 [mips] Use register operands instead of register classes in DSP instruction
definitions.

llvm-svn: 188343
2013-08-14 01:02:20 +00:00
Akira Hatanaka 654655f1c5 [mips] Rename DSPRegs.
llvm-svn: 188342
2013-08-14 00:53:38 +00:00
Akira Hatanaka 8002a3f6d8 [mips] Rename HIRegs and LORegs.
llvm-svn: 188341
2013-08-14 00:47:08 +00:00
Akira Hatanaka 00fcf2e169 [mips] Rename accumulator register classes and FP register operands.
llvm-svn: 188020
2013-08-08 21:54:26 +00:00
Akira Hatanaka 6bf3c03861 [mips] Mark pseudo instructions as code-gen only.
llvm-svn: 188017
2013-08-08 21:44:39 +00:00
Akira Hatanaka 13e6ccf341 [mips] Rename register classes CPURegs and CPU64Regs.
llvm-svn: 187832
2013-08-06 23:08:38 +00:00
Akira Hatanaka 34a32c0b87 [mips] Replace usages of register classes with register operands. Also, remove
unnecessary jalr InstAliases in Mips64InstrInfo.td and add the code to print
jalr InstAliases in MipsInstPrinter::printAlias.

llvm-svn: 187821
2013-08-06 22:20:40 +00:00
Akira Hatanaka e86bd4f652 [mips] Split the DSP control register and define one register for each field of
its fields.

This removes false dependencies between DSP instructions which access different
fields of the the control register. Implicit register operands are added to
instructions RDDSP and WRDSP after instruction selection, depending on the
value of the mask operand.

llvm-svn: 181041
2013-05-03 18:37:49 +00:00
Akira Hatanaka 5705f546e5 [mips] Handle reading, writing or copying of ccond field of DSP control
register.

- Define pseudo instructions which store or load ccond field of the DSP
  control register.
- Emit the pseudos in MipsSEInstrInfo::storeRegToStack and loadRegFromStack.
- Expand the pseudos before callee-scan save.
- Emit instructions RDDSP or WRDSP to copy between ccond field and GPRs. 

llvm-svn: 180969
2013-05-02 23:07:05 +00:00
Akira Hatanaka 4254319ef9 [mips] Fix handling of instructions which copy to/from accumulator registers.
Expand copy instructions between two accumulator registers before callee-saved
scan is done. Handle copies between integer GPR and hi/lo registers in
MipsSEInstrInfo::copyPhysReg. Delete pseudo-copy instructions that are not
needed.

llvm-svn: 180827
2013-04-30 23:22:09 +00:00
Akira Hatanaka 68741cc38d [mips] Instruction selection patterns for DSP-ASE vector select and compare
instructions.

llvm-svn: 180820
2013-04-30 22:37:26 +00:00
Akira Hatanaka 84d6d9bdaa [mips] Clear isCommutable bit of instructions which are not commutable.
llvm-svn: 180801
2013-04-30 20:40:39 +00:00
Akira Hatanaka 0d6964cf4a [mips] In performDSPShiftCombine, check that all elements in the vector are
shifted by the same amount and the shift amount is smaller than the element
size.

llvm-svn: 180039
2013-04-22 19:58:23 +00:00
Akira Hatanaka 1ebb2a1c56 [mips] Instruction selection patterns for DSP-ASE vector shifts.
llvm-svn: 179906
2013-04-19 23:21:32 +00:00
Akira Hatanaka 59bfaf774b [mips] DSP-ASE move from HI/LO register instructions.
llvm-svn: 179739
2013-04-18 00:52:44 +00:00
Akira Hatanaka 2f08822f9d [mips] Reapply r179420 and r179421.
llvm-svn: 179434
2013-04-13 00:55:41 +00:00
Akira Hatanaka 8ed2892c1c Revert r179420 and r179421.
llvm-svn: 179422
2013-04-12 22:40:07 +00:00
Akira Hatanaka 931ad87f6a [mips] Instruction selection patterns for carry-setting and using add
instructions.

llvm-svn: 179421
2013-04-12 22:24:52 +00:00
Akira Hatanaka 8f41dd923e [mips] v4i8 and v2i16 add, sub and mul instruction selection patterns.
llvm-svn: 179420
2013-04-12 22:14:24 +00:00
Akira Hatanaka b3c1847b30 [mips] Add patterns for DSP indexed load instructions.
llvm-svn: 178408
2013-03-30 02:14:45 +00:00
Akira Hatanaka fb221c197d [mips] Fix DSP instructions to have explicit accumulator register operands.
Check that instruction selection can select multiply-add/sub DSP instructions
from a pattern that doesn't have intrinsics.

llvm-svn: 178406
2013-03-30 01:58:00 +00:00
Akira Hatanaka c8d85025a0 [mips] Define pseudo instructions for spilling and copying accumulator
registers.

llvm-svn: 178390
2013-03-30 00:54:52 +00:00
Akira Hatanaka b1527b7505 [mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass
parameter.

llvm-svn: 170661
2012-12-20 04:20:09 +00:00
Akira Hatanaka 02ec5516f8 [mips] Move class IsCommutable into MipsInstrInfo.td.
llvm-svn: 170054
2012-12-13 00:32:01 +00:00
Akira Hatanaka d66f489640 MIPS DSP: other miscellaneous instructions.
llvm-svn: 164845
2012-09-28 20:50:31 +00:00
Akira Hatanaka 334dad6aea MIPS DSP: ADDUH.QB instruction sub-class.
llvm-svn: 164840
2012-09-28 20:16:04 +00:00
Akira Hatanaka a9183eda74 MIPS DSP: ABSQ_S.PH instruction sub-class.
llvm-svn: 164787
2012-09-27 19:09:21 +00:00
Akira Hatanaka 892b1046c6 MIPS DSP: SHLL.QB instruction sub-class.
llvm-svn: 164786
2012-09-27 19:05:08 +00:00
Akira Hatanaka 314b43b781 MIPS DSP: rddsp (instruction which reads DSPControl register fields to a GPR).
llvm-svn: 164756
2012-09-27 04:08:42 +00:00
Akira Hatanaka b664ae67ce MIPS DSP: CMPU.EQ.QB instruction sub-class.
llvm-svn: 164755
2012-09-27 03:58:34 +00:00
Akira Hatanaka d09642beb3 MIPS DSP: ADDU.QB instruction sub-class.
llvm-svn: 164754
2012-09-27 03:13:59 +00:00
Akira Hatanaka e4bd054f98 MIPS DSP: Branch on Greater Than or Equal To Value 32 in DSPControl Pos Field instruction.
llvm-svn: 164751
2012-09-27 02:15:57 +00:00
Akira Hatanaka 9061a46443 MIPS DSP: all the remaining instructions which read or write accumulators.
llvm-svn: 164750
2012-09-27 02:11:20 +00:00
Akira Hatanaka 1babeaa44c MIPS DSP: add support for extract-word instructions.
llvm-svn: 164749
2012-09-27 02:05:42 +00:00
Akira Hatanaka de8231eada MIPS DSP: add bitcast patterns between vectors and int.
No test cases. These patterns will get tested along with dsp intrinsics.

llvm-svn: 164746
2012-09-27 01:56:38 +00:00
Akira Hatanaka 5eeac4f813 MIPS DSP: add vector load/store patterns.
llvm-svn: 164744
2012-09-27 01:50:59 +00:00
Akira Hatanaka ecfb828341 MIPS DSP: Add immediate leaves.
llvm-svn: 164435
2012-09-22 00:07:12 +00:00