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Author SHA1 Message Date
Chad Rosier a88cb23da7 Revert r140924 "Attempt to fix dynamic stack realignment for thumb1 functions." 
to appease nightly testers.  Not quite there yet.

llvm-svn: 140953
 2011-10-01 19:30:36 +00:00
Bill Wendling d072b73d78 No one should be using the method directly. Assert if they do. 
llvm-svn: 140947
 2011-10-01 12:47:34 +00:00
Bill Wendling f977ff5fb5 Add a convenience method to tell if two things are equal. 
llvm-svn: 140946
 2011-10-01 12:44:28 +00:00
Bill Wendling 4a4772fae2 Use the ARMConstantPoolMBB class to handle the MBB values. 
llvm-svn: 140943
 2011-10-01 09:30:42 +00:00
Bill Wendling 6dbc9fe82b Add ARMConstantPoolMBB to hold an MBB value in the constant pool. 
llvm-svn: 140942
 2011-10-01 09:19:10 +00:00
Bill Wendling c5a86069ca Remove dead code. 
llvm-svn: 140941
 2011-10-01 09:05:12 +00:00
Bill Wendling 9ff05f740f Remove now dead methods and ivar. 
llvm-svn: 140940
 2011-10-01 09:04:18 +00:00
Bill Wendling c214cb055d Use the new ARMConstantPoolSymbol class to handle external symbols. 
llvm-svn: 140939
 2011-10-01 08:58:29 +00:00
Bill Wendling d7fa016720 Add an ARMConstantPool class for external symbols. This will split out the support for external symbols from the base class. 
llvm-svn: 140938
 2011-10-01 08:36:59 +00:00
Bill Wendling d115c4d300 Remove now dead methods and ivar from ARMConstantPoolValue. 
llvm-svn: 140937
 2011-10-01 08:02:05 +00:00
Bill Wendling 7753d66468 Switch over to using ARMConstantPoolConstant for global variables, functions, 
and block addresses.

llvm-svn: 140936
 2011-10-01 08:00:54 +00:00
Bill Wendling f117a35de0 Some more refactoring. 
* Add a couple of Create methods to the ARMConstantPoolConstant class,
* Add its own version of getExistingMachineCPValue, and
* Modify hasSameValue to return false if the object isn't an ARMConstantPoolConstant.

llvm-svn: 140935
 2011-10-01 07:52:37 +00:00
Bill Wendling 6722556380 Add a Create method that accepts 'kind' and 'pcadj' arguments. 
llvm-svn: 140934
 2011-10-01 06:44:24 +00:00
Bill Wendling 396c211ae1 Refactoring: Separate out the ARM constant pool Constant from the ARM constant 
pool value.

It's not used right now, but will be soon.

llvm-svn: 140933
 2011-10-01 06:40:33 +00:00
Chad Rosier 21360a4949 Attempt to fix dynamic stack realignment for thumb1 functions. It is in fact 
useful if an optimization assumes the stack has been realigned.  Credit to
Eli for his assistance.
rdar://10043857

llvm-svn: 140924
 2011-10-01 02:03:18 +00:00
Jakob Stoklund Olesen 237dceff90 Store sub-class lists as a bit vector. 
This uses less memory and it reduces the complexity of sub-class
operations:

- hasSubClassEq() and friends become O(1) instead of O(N).

- getCommonSubClass() becomes O(N) instead of O(N^2).

In the future, TableGen will infer register classes.  This makes it
cheap to add them.

llvm-svn: 140898
 2011-09-30 22:19:07 +00:00
Jim Grosbach d76f43e18c Correct for my over-eager delete finger. 
llvm-svn: 140892
 2011-09-30 22:02:45 +00:00
Bill Wendling e8e4dbf468 Constify 'isLSDA' and move a method out-of-line. 
llvm-svn: 140868
 2011-09-30 18:42:06 +00:00
Jim Grosbach 4e0dbee62b ARM Darwin default relocation model is PIC. 
This matches clang, so default options in llc and friends are now closer to
clang's defaults.

llvm-svn: 140863
 2011-09-30 17:41:35 +00:00
Jim Grosbach d2222c386c ARM Fixup valus for movt/movw are for the whole value. 
Remove an assert that was expecting only the relevant 16bit portion for
the fixup being handled. Also kill some dead code in the T2 portion.

rdar://9653509

llvm-svn: 140861
 2011-09-30 17:23:05 +00:00
Jim Grosbach efc761a1eb ARM fix encoding of VMOV.f32 and VMOV.f64 immediates. 
Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.

rdar://10211428

llvm-svn: 140834
 2011-09-30 00:50:06 +00:00
Bill Wendling 69bc3de4fc Create a machine basic block in the constant pool and retrieve the symbol for an MBB. 
llvm-svn: 140824
 2011-09-29 23:50:42 +00:00
Bill Wendling a1127b2fa2 Support creating a constant pool value for a machine basic block. 
This is used when we want to take the address of a machine basic block, but it's
not associated with a BB in LLVM IR.

llvm-svn: 140823
 2011-09-29 23:48:44 +00:00
NAKAMURA Takumi 15b3c9c684 Target/ARM: Unbreak! CMake! Build! 
llvm-svn: 140774
 2011-09-29 03:32:49 +00:00
Jakob Stoklund Olesen bf64024a39 Delete NEONMoveFix, now unused. 
llvm-svn: 140773
 2011-09-29 02:56:45 +00:00
Jakob Stoklund Olesen f7ad189033 Use ExecutionDepsFix instead of NEONMoveFix. 
This enables NEON domain tracking across basic blocks, but should
otherwise do the same thing.

llvm-svn: 140772
 2011-09-29 02:48:41 +00:00
Bill Wendling a0d5f268a9 Move to ISelLowering. 
llvm-svn: 140754
 2011-09-29 01:13:55 +00:00
Evan Cheng 8156376aa9 Tighten a ARM dag combine condition to avoid an identity transformation, which 
ends up introducing a cycle in the DAG.

rdar://10196296

llvm-svn: 140733
 2011-09-28 23:16:31 +00:00
Bill Wendling 315b9573c6 Perform the lowering only if there are invokes. 
llvm-svn: 140719
 2011-09-28 20:29:45 +00:00
Bill Wendling dfe5acd34e Ahem...actually *add* the ARMSjLjLowering pass to the pass manager. 
llvm-svn: 140718
 2011-09-28 20:29:28 +00:00
James Molloy 21efa7d6e1 Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit. 
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.

Add decoder and disassembler tests.

Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.

llvm-svn: 140696
 2011-09-28 14:21:38 +00:00
Ted Kremenek e3e36f80f5 Unbreak CMake build. 
llvm-svn: 140655
 2011-09-27 23:29:59 +00:00
Jakob Stoklund Olesen f9b71a2e01 Implement TII::get/setExecutionDomain() for ARM. 
llvm-svn: 140653
 2011-09-27 22:57:21 +00:00
Jim Grosbach c63af1b7b6 ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w. 
Add inst alias to handle these assembly forms. Add tests, too.

rdar://10178799

llvm-svn: 140647
 2011-09-27 22:18:54 +00:00
Bill Wendling 354ff9e348 This is the start of the new SjLj EH preparation pass, which will replace the 
current IR-level pass.

The old SjLj EH pass has some problems, especially with the new EH model. Most
significantly, it violates some of the new restrictions the new model has. For
instance, the 'dispatch' table wants to jump to the landing pad, but we cannot
allow that because only an invoke's unwind edge can jump to a landing pad. This
requires us to mangle the code something awful. In addition, we need to keep the
now dead landingpad instructions around instead of CSE'ing them because the
DWARF emitter uses that information (they are dead because no control flow edge
will execute them - the control flow edge from an invoke's unwind is superceded
by the edge coming from the dispatch).

Basically, this pass belongs not at the IR level where SSA is king, but at the
code-gen level, where we have more flexibility.

llvm-svn: 140646
 2011-09-27 22:14:12 +00:00
Jim Grosbach af136f71ec Rename AddSelectionDAGCSEId() to addSelectionDAGCSEId(). 
Naming conventions consistency. No functional change.

llvm-svn: 140636
 2011-09-27 20:59:33 +00:00
Jakob Stoklund Olesen 1c7597693c Use existing function. 
llvm-svn: 140615
 2011-09-27 17:55:08 +00:00
Owen Anderson b1a9f65487 Remove extraneous commit garbage. 
llvm-svn: 140581
 2011-09-26 23:14:02 +00:00
Owen Anderson f01e2de5e6 ASR #32 is not allowed on Thumb2 USAT and SSAT instructions. 
llvm-svn: 140560
 2011-09-26 21:06:22 +00:00
David Meyer b1fbf9ff26 PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL 2011-06-09-TailCallByVal and 2010-11-04-BigByval 
llvm-svn: 140516
 2011-09-26 06:13:20 +00:00
Owen Anderson 4916840eb8 Teach the Thumb2 AsmParser to accept pre-indexed loads/stores with an offset of #-0. 
llvm-svn: 140426
 2011-09-23 22:25:02 +00:00
Jakob Stoklund Olesen 2056d15bd9 Also match negative offsets for addrmode3 and addrmode5. 
Math is hard, and isScaledConstantInRange() always returned false for
negative constants.  It was doing unsigned division of negative numbers
before casting back to signed.

llvm-svn: 140425
 2011-09-23 22:10:33 +00:00
Owen Anderson b0b865d658 Add more fixed bits to USAT16 encoding to filter out incorrect decodings. 
llvm-svn: 140422
 2011-09-23 21:57:50 +00:00
Owen Anderson 737beaf86d Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions. 
llvm-svn: 140420
 2011-09-23 21:26:40 +00:00
Owen Anderson 987a878946 Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated. 
llvm-svn: 140415
 2011-09-23 21:07:25 +00:00
Owen Anderson ffa8428acf Revert r140412. This affects more instructions than intended. 
llvm-svn: 140413
 2011-09-23 21:02:01 +00:00
Owen Anderson 7591d0c363 Thumb2 register-shifted-register loads cannot target the PC or the SP. 
llvm-svn: 140412
 2011-09-23 21:00:32 +00:00
Owen Anderson fbe52c0192 Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix other test failures I caused. 
llvm-svn: 140284
 2011-09-21 23:53:44 +00:00
Owen Anderson f52c68f0ca Print out immediate offset versions of PC-relative load/store instructions as [pc, #123] rather than simply #123. 
llvm-svn: 140283
 2011-09-21 23:44:46 +00:00
Owen Anderson bcc3fadad9 These do not need to be conditional on the presence of CommentStream, as they have a fallback path now. 
llvm-svn: 140267
 2011-09-21 17:58:45 +00:00