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21242 Commits

Author SHA1 Message Date
Evan Cheng 3c5198336c Use SDTCisPtrTy type property for store address. 
llvm-svn: 24656
 2005-12-10 01:59:36 +00:00
Evan Cheng 0da396ffe2 Stop emitting a redudant type check for complex pattern node. 
llvm-svn: 24655
 2005-12-10 01:57:33 +00:00
Evan Cheng 0d6cfee704 * Added X86 store patterns. 
* Added X86 dec patterns.

llvm-svn: 24654
 2005-12-10 00:48:20 +00:00
Evan Cheng dadc1057ac Added new getNode and getTargetNode variants for X86 stores. 
llvm-svn: 24653
 2005-12-10 00:37:58 +00:00
Evan Cheng bac252c289 For instructions which produce no result, e.g. store, chain's Resno == 0. 
llvm-svn: 24652
 2005-12-10 00:09:17 +00:00
Nate Begeman ade6f9a255 Add support patterns to many load and store instructions which will 
hopefully use patterns in the near future.

llvm-svn: 24651
 2005-12-09 23:54:18 +00:00
Chris Lattner 27656ac89c Add SDTCisPtrTy and use it for loads, to indicate that the operand of a load 
must be a pointer.  This removes a type check out of the code generated by
tblgen for load matching.

llvm-svn: 24650
 2005-12-09 22:58:42 +00:00
Chris Lattner 433573f4c6 Add a new SDTCisPtrTy constraint, which indicates that an operand must have 
the same type as the pointer type for a target.

llvm-svn: 24649
 2005-12-09 22:57:42 +00:00
Evan Cheng 275a3ed80c Added patterns for ADD8rm, etc. These fold load operands. e.g. addb 4(%esp), %al 
llvm-svn: 24648
 2005-12-09 22:48:48 +00:00
Evan Cheng 499ab2a9fa * Do not allow nodes which produce chain results (e.g. loads) to be folded if 
it has more than one real use (non-chain uses).
* Record folded chain producing node in CodeGenMap.
* Do not fold a chain producing node if it has already been selected as an
  operand of a chain use.

llvm-svn: 24647
 2005-12-09 22:45:35 +00:00
Chris Lattner a6f835f5a0 Avoid emitting two tabs when switching to a named section 
llvm-svn: 24646
 2005-12-09 19:28:49 +00:00
Chris Lattner e0f5f8e43c Teach the PPC backend about the ctor and dtor list when not using __main and 
linking the entire program into one bc file.

llvm-svn: 24645
 2005-12-09 18:24:29 +00:00
Chris Lattner 268d457b69 Teach legalize how to promote sext_inreg to fix a problem Andrew pointed 
out to me.

llvm-svn: 24644
 2005-12-09 17:32:47 +00:00
Evan Cheng c1f911a238 Prevent folding of instructions which produce chains that have more than 1 real use 
llvm-svn: 24643
 2005-12-09 06:06:08 +00:00
Evan Cheng f423a17e33 * Make sure complex pattern operands are selected first since their select 
functions can return false and causing the instruction pattern match to fail.
* Code clean up.

llvm-svn: 24642
 2005-12-09 00:48:42 +00:00
Andrew Lenharth 87bf2234b5 it helps if your conditionals are not reversed 
llvm-svn: 24641
 2005-12-09 00:45:42 +00:00
Chris Lattner be73d6eece improve code insertion in two ways: 
1. Only forward subst offsets into loads and stores, not into arbitrary
   things, where it will likely become a load.
2. If the source is a cast from pointer, forward subst the cast as well,
   allowing us to fold the cast away (improving cases when the cast is
   from an alloca or global).

This hasn't been fully tested, but does appear to further reduce register
pressure and improve code.  Lets let the testers grind on it a bit. :)

llvm-svn: 24640
 2005-12-08 08:00:12 +00:00
Chris Lattner 29e6c3dbf9 Add another important case we miss 
llvm-svn: 24639
 2005-12-08 07:13:28 +00:00
Evan Cheng 790af6d18f Added support for ComplexPattern. 
llvm-svn: 24638
 2005-12-08 04:28:48 +00:00
Evan Cheng f039648614 Added explicit type field to ComplexPattern. 
llvm-svn: 24637
 2005-12-08 02:15:07 +00:00
Evan Cheng c9a620060b * Added an explicit type field to ComplexPattern. 
* Renamed MatchingNodes to RootNodes.

llvm-svn: 24636
 2005-12-08 02:14:08 +00:00
Evan Cheng c9fab31098 * Added intelligence to X86 LEA addressing mode matching routine so it returns 
false if the match is not profitable. e.g. leal 1(%eax), %eax.
* Added patterns for X86 integer loads and LEA32.

llvm-svn: 24635
 2005-12-08 02:01:35 +00:00
Evan Cheng 9b9567bfb5 Added support for ComplexPattern. These are patterns that require C++ pattern 
matching code that is not currently auto-generated by tblgen, e.g. X86
addressing mode. Selection routines for complex patterns can return multiple operands, e.g. X86 addressing mode returns 4.

llvm-svn: 24634
 2005-12-08 02:00:36 +00:00
Nate Begeman ae89d862f5 Fix a crash where ConstantVec nodes were being generated with the wrong 
type when the target did not support them.  Also teach Legalize how to
expand ConstantVecs.

This allows us to generate

_test:
        lwz r2, 12(r3)
        lwz r4, 8(r3)
        lwz r5, 4(r3)
        lwz r6, 0(r3)
        addi r2, r2, 4
        addi r4, r4, 3
        addi r5, r5, 2
        addi r6, r6, 1
        stw r2, 12(r3)
        stw r4, 8(r3)
        stw r5, 4(r3)
        stw r6, 0(r3)
        blr

For:

void %test(%v4i *%P) {
        %T = load %v4i* %P
        %S = add %v4i %T, <int 1, int 2, int 3, int 4>
        store %v4i %S, %v4i * %P
        ret void
}

On PowerPC.

llvm-svn: 24633
 2005-12-07 19:48:11 +00:00
Chris Lattner 57c882edf8 Only transform (sext (truncate x)) -> (sextinreg x) if before legalize or 
if the target supports the resultant sextinreg

llvm-svn: 24632
 2005-12-07 18:02:05 +00:00
Chris Lattner 3225733e65 X86 doesn't support sextinreg for 8-bit things either. 
llvm-svn: 24631
 2005-12-07 17:59:14 +00:00
Chris Lattner cbd3d01a43 Teach the dag combiner to turn a truncate/sign_extend pair into a sextinreg 
when the types match up.  This allows the X86 backend to compile:

sbyte %toggle_value(sbyte* %tmp.1) {
        %tmp.2 = load sbyte* %tmp.1
        ret sbyte %tmp.2
}

to this:

_toggle_value:
        mov %EAX, DWORD PTR [%ESP + 4]
        movsx %EAX, BYTE PTR [%EAX]
        ret

instead of this:

_toggle_value:
        mov %EAX, DWORD PTR [%ESP + 4]
        movsx %EAX, BYTE PTR [%EAX]
        movsx %EAX, %AL
        ret

noticed in Shootout/objinst.

-Chris

llvm-svn: 24630
 2005-12-07 07:11:03 +00:00
Chris Lattner 30aa5f735f Remove a now-dead map, patch by Saem Ghani, thanks! 
llvm-svn: 24629
 2005-12-07 05:41:44 +00:00
Andrew Lenharth 26473b6b58 fix divide and remainder 
llvm-svn: 24628
 2005-12-06 23:27:39 +00:00
Chris Lattner de085f0165 Silence another annoying GCC warning 
llvm-svn: 24627
 2005-12-06 20:56:18 +00:00
Andrew Lenharth 312e65568c This solves the problem of the CBE renaming symbols that start with . but the assembly side still trying to reference them by their old names. Should be safe untill we hit a language front end that lets you specify such a name. 
llvm-svn: 24626
 2005-12-06 20:51:30 +00:00
Andrew Lenharth 973cd1c845 more decent branches for FP. I might have to make some intermediate nodes to actually be able to use the DAG for FPcmp 
llvm-svn: 24625
 2005-12-06 20:43:30 +00:00
Andrew Lenharth 29b7ef0065 OK, this does wonders for broken stuff 
llvm-svn: 24624
 2005-12-06 20:40:34 +00:00
Sumant Kowshik e3cccc938b Added comment for removing assert 
llvm-svn: 24623
 2005-12-06 18:16:08 +00:00
Sumant Kowshik a69fcbdeb8 Collapsing node if variable length struct with final field of length zero 
llvm-svn: 24621
 2005-12-06 18:04:30 +00:00
Sumant Kowshik 1473162af0 Handling of zero length last fields in struct used for growing it arbitrarily 
llvm-svn: 24620
 2005-12-06 18:01:20 +00:00
Chris Lattner d490d4f023 Fix test/Regression/Linker/2005-12-06-AppendingZeroLengthArrays.ll and 
PR662.  Thanks to Markus for providing me with a ton of files to
reproduce the problem!

llvm-svn: 24619
 2005-12-06 17:30:58 +00:00
Chris Lattner 98dcd12c28 new testcase for PR662 
llvm-svn: 24618
 2005-12-06 17:29:54 +00:00
Chris Lattner cfe67e1318 Implement external storage for post-order iteration, implementing PR267 
Patch by Saem Ghani, thanks!

llvm-svn: 24617
 2005-12-06 07:05:27 +00:00
Nate Begeman 41b1cdc771 Teach the SelectionDAG ISel how to turn ConstantPacked values into 
constant nodes with vector types.  Also teach the asm printer how to print
ConstantPacked constant pool entries.  This allows us to generate altivec
code such as the following, which adds a vector constantto a packed float.

LCPI1_0:  <4 x float> < float 0.0e+0, float 0.0e+0, float 0.0e+0, float 1.0e+0 >
        .space  4
        .space  4
        .space  4
        .long   1065353216      ; float 1
        .text
        .align  4
        .globl  _foo
_foo:
        lis r2, ha16(LCPI1_0)
        la r2, lo16(LCPI1_0)(r2)
        li r4, 0
        lvx v0, r4, r2
        lvx v1, r4, r3
        vaddfp v0, v1, v0
        stvx v0, r4, r3
        blr

For the llvm code:

void %foo(<4 x float> * %a) {
entry:
  %tmp1 = load <4 x float> * %a;
  %tmp2 = add <4 x float> %tmp1, < float 0.0, float 0.0, float 0.0, float 1.0 >
  store <4 x float> %tmp2, <4 x float> *%a
  ret void
}

llvm-svn: 24616
 2005-12-06 06:18:55 +00:00
Chris Lattner fea33f7e64 Use new PPC-specific nodes to represent shifts which require the 6-bit 
amount handling that PPC provides.  These are generated by the lowering code
and prevents the dag combiner from assuming (rightfully) that the shifts
don't only look at 5 bits.  This fixes a miscompilation of crafty with
the new front-end.

llvm-svn: 24615
 2005-12-06 02:10:38 +00:00
Andrew Lenharth e788bbf6ef added instructions with inverted immediates 
llvm-svn: 24614
 2005-12-06 00:33:53 +00:00
Andrew Lenharth 08c4a775e6 yea, it helps to have your path set right when testing 
llvm-svn: 24613
 2005-12-05 23:41:45 +00:00
Andrew Lenharth 3c7c4d7508 These never trigger, but whatever 
llvm-svn: 24612
 2005-12-05 23:19:44 +00:00
Evan Cheng c0c190239d Remove unnecessary let hasCtrlDep=1 now it can be inferred. 
llvm-svn: 24611
 2005-12-05 23:09:43 +00:00
Evan Cheng 0fe76d1585 * Infer instruction property hasCtrlDep from pattern if it has one. 
* Fixed a bug related to hasCtrlDep property use.

llvm-svn: 24610
 2005-12-05 23:08:55 +00:00
Andrew Lenharth 5bfcd1e63a move this over to the dag 
llvm-svn: 24609
 2005-12-05 20:50:53 +00:00
Chris Lattner 077200737c getRawValue zero extens for unsigned values, use getsextvalue so that we 
know that small negative values fit into the immediate field of addressing
modes.

llvm-svn: 24608
 2005-12-05 18:23:57 +00:00
Andrew Lenharth 9410433966 fix constant pool loads 
llvm-svn: 24607
 2005-12-05 17:51:02 +00:00
Chris Lattner 3539778883 Fix the #1 code quality problem that I have seen on X86 (and it also affects 
PPC and other targets).  In a particular, consider code like this:

struct Vector3 { double x, y, z; };
struct Matrix3 { Vector3 a, b, c; };
double dot(Vector3 &a, Vector3 &b) {
   return a.x * b.x  +  a.y * b.y  +  a.z * b.z;
}
Vector3 mul(Vector3 &a, Matrix3 &b) {
   Vector3 r;
   r.x = dot( a, b.a );
   r.y = dot( a, b.b );
   r.z = dot( a, b.c );
   return r;
}
void transform(Matrix3 &m, Vector3 *x, int n) {
   for (int i = 0; i < n; i++)
      x[i] = mul( x[i], m );
}

we compile transform to a loop with all of the GEP instructions for indexing
into 'm' pulled out of the loop (9 of them).  Because isel occurs a bb at a time
we are unable to fold the constant index into the loads in the loop, leading to
PPC code that looks like this:

LBB3_1: ; no_exit.preheader
        li r2, 0
        addi r6, r3, 64        ;; 9 values live across the loop body!
        addi r7, r3, 56
        addi r8, r3, 48
        addi r9, r3, 40
        addi r10, r3, 32
        addi r11, r3, 24
        addi r12, r3, 16
        addi r30, r3, 8
LBB3_2: ; no_exit
        lfd f0, 0(r30)
        lfd f1, 8(r4)
        fmul f0, f1, f0
        lfd f2, 0(r3)        ;; no constant indices folded into the loads!
        lfd f3, 0(r4)
        lfd f4, 0(r10)
        lfd f5, 0(r6)
        lfd f6, 0(r7)
        lfd f7, 0(r8)
        lfd f8, 0(r9)
        lfd f9, 0(r11)
        lfd f10, 0(r12)
        lfd f11, 16(r4)
        fmadd f0, f3, f2, f0
        fmul f2, f1, f4
        fmadd f0, f11, f10, f0
        fmadd f2, f3, f9, f2
        fmul f1, f1, f6
        stfd f0, 0(r4)
        fmadd f0, f11, f8, f2
        fmadd f1, f3, f7, f1
        stfd f0, 8(r4)
        fmadd f0, f11, f5, f1
        addi r29, r4, 24
        stfd f0, 16(r4)
        addi r2, r2, 1
        cmpw cr0, r2, r5
        or r4, r29, r29
        bne cr0, LBB3_2 ; no_exit

uh, yuck.  With this patch, we now sink the constant offsets into the loop, producing
this code:

LBB3_1: ; no_exit.preheader
        li r2, 0
LBB3_2: ; no_exit
        lfd f0, 8(r3)
        lfd f1, 8(r4)
        fmul f0, f1, f0
        lfd f2, 0(r3)
        lfd f3, 0(r4)
        lfd f4, 32(r3)       ;; much nicer.
        lfd f5, 64(r3)
        lfd f6, 56(r3)
        lfd f7, 48(r3)
        lfd f8, 40(r3)
        lfd f9, 24(r3)
        lfd f10, 16(r3)
        lfd f11, 16(r4)
        fmadd f0, f3, f2, f0
        fmul f2, f1, f4
        fmadd f0, f11, f10, f0
        fmadd f2, f3, f9, f2
        fmul f1, f1, f6
        stfd f0, 0(r4)
        fmadd f0, f11, f8, f2
        fmadd f1, f3, f7, f1
        stfd f0, 8(r4)
        fmadd f0, f11, f5, f1
        addi r6, r4, 24
        stfd f0, 16(r4)
        addi r2, r2, 1
        cmpw cr0, r2, r5
        or r4, r6, r6
        bne cr0, LBB3_2 ; no_exit

This is much nicer as it reduces register pressure in the loop a lot.  On X86,
this takes the function from having 9 spilled registers to 2.  This should help
some spec programs on X86 (gzip?)

This is currently only enabled with -enable-gep-isel-opt to allow perf testing
tonight.

llvm-svn: 24606
 2005-12-05 07:10:48 +00:00