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5 Commits

Author SHA1 Message Date
Matt Arsenault 28215caa60 GlobalISel: Partially implement fewerElementsVector G_UNMERGE_VALUES 
Odd sized vectors aren't handled yet.

llvm-svn: 368713
 2019-08-13 16:26:28 +00:00
Matt Arsenault d9d30a408e GlobalISel: Lower scalarizing unmerge of a vector to shifts 
AMDGPU sometimes has legal s16 and <2 x s16> operations, but all
registers are really 32-bit. An unmerge destination really should ben
widened to a 32-bit register. If widening a scalarizing vector with a
target size that matches the vector size, bitcast to integer and
extract the relevant bits with shifts.

I'm not sure if this is the right place for this. This could arguably
be part of widenScalar for the result. I also have a growing feeling
that we're missing a bitcast legalize action.

llvm-svn: 367604
 2019-08-01 19:10:05 +00:00
Matt Arsenault 18ec382698 GlobalISel: Implement moreElementsVector for implicit_def 
llvm-svn: 353754
 2019-02-11 22:00:39 +00:00
Matt Arsenault ca676343a9 GlobalISel: Implement fewerElementsVector for extensions 
llvm-svn: 352155
 2019-01-25 02:36:32 +00:00
Matt Arsenault 24563ef628 AMDGPU/GlobalISel: Cleanup legality for extensions 
llvm-svn: 351691
 2019-01-20 18:34:24 +00:00