Commit Graph

77887 Commits

Author SHA1 Message Date
David Blaikie 7682663ef6 [opaque pointer type] gep API migration, ArgPromo
This involved threading the type-to-gep through a data structure, since
the code was relying on the pointer type to carry this information. I
imagine there will be a lot of this work across the project... slow
work chasing each use case, but the assertions will help keep me honest.

llvm-svn: 232277
2015-03-14 21:11:26 +00:00
David Blaikie cd7b97e48f [opaque pointer type] more gep API migrations (AsmParser)
llvm-svn: 232276
2015-03-14 21:11:24 +00:00
Duncan P. N. Exon Smith d6d70e753d IR: Make Metadata::print() reliable and useful
Replumb the `AsmWriter` so that `Metadata::print()` is generally useful.
(Similarly change `Metadata::printAsOperand()`.)

- `SlotTracker` now has a mode where all metadata will be correctly
  numbered when initializing a `Module`.  Normally, `Metadata` only
  referenced from within `Function`s gets numbered when the `Function`
  is incorporated.
- `Metadata::print()` and `Metadata::printAsOperand()` (and
  `Metadata::dump()`) now take an optional `Module` argument.  When
  provided, `SlotTracker` is initialized with the new mode, and the
  numbering will be complete and consistent for all calls to `print()`.
- `Value::print()` uses the new `SlotTracker` mode when printing
  intrinsics with `MDNode` operands, `MetadataAsValue` operands, or the
  bodies of functions.  Thus, metadata numbering will be consistent
  between calls to `Metadata::print()` and `Value::print()`.
- `Metadata::print()` (and `Metadata::dump()`) now print the full
  definition of `MDNode`s:

    !5 = !{!6, !"abc", !7}

  This matches behaviour for `Value::print()`, which includes the name
  of instructions.
- Updated call sites in `Verifier` to call `print()` instead of
  `printAsOperand()`.

All this, so that `Verifier` can print out useful failure messages that
involve `Metadata` for PR22777.

Note that `Metadata::printAsOperand()` previously took an optional
`bool` and `Module` operand.  The former was cargo-culted from
`Value::printAsOperand()` and wasn't doing anything useful.  The latter
didn't give consistent results (without the new `SlotTracker` mode).

llvm-svn: 232275
2015-03-14 20:19:36 +00:00
David Blaikie 096b1da29d [opaque pointer type] more gep API migration
llvm-svn: 232274
2015-03-14 19:53:33 +00:00
Duncan P. N. Exon Smith 20b76ac2ae AsmWriter: Split out SlotTracker::processInstructionMetadata(), NFC
llvm-svn: 232273
2015-03-14 19:48:31 +00:00
Duncan P. N. Exon Smith 27f33ee368 AsmWriter: Use range-based for, NFC
llvm-svn: 232272
2015-03-14 19:44:01 +00:00
David Blaikie 22319eb920 [opaque pointer type] more gep API migrations
Adding nullptr to all the IRBuilder stuff because it's the first thing
that fails to build when testing without the back-compat functions, so
I'll keep having to re-add these locally for each chunk of migration I
do. Might as well check them in to save me the churn. Eventually I'll
have to migrate these too, but I'm going breadth-first.

llvm-svn: 232270
2015-03-14 19:24:04 +00:00
Yaron Keren bdae8d6403 No need to prototype RtlCaptureContext with mingw-w64.
llvm-svn: 232269
2015-03-14 19:20:56 +00:00
Duncan P. N. Exon Smith ec9d3f779a Recover the ability to 'b CheckFailed' after r231577
Given that the stated purpose of `CheckFailed()` is to provide a nice
spot for a breakpoint, it'd be nice not to have to use a regex to break
on it.  Recover the ability to simply use `b CheckFailed` by
specializing the message-only version, and by changing the variadic
version to call into the message-only version.

llvm-svn: 232268
2015-03-14 16:47:37 +00:00
Daniel Jasper 15e6954aea [MachineLICM] First steps of sinking GEPs near calls.
Specifically, if there are copy-like instructions in the loop header
they are moved into the loop close to their uses. This reduces the live
intervals of the values and can avoid register spills.

This is working towards a fix for http://llvm.org/PR22230.
Review: http://reviews.llvm.org/D7259

Next steps:
- Find a better cost model (which non-copy instructions should be sunk?)
- Make this dependent on register pressure

llvm-svn: 232262
2015-03-14 10:58:38 +00:00
Vasileios Kalintiris 46fa9b7b1e [mips] Remove trivial header for the MipsModuleISelDAGToDAG pass. NFC.
llvm-svn: 232260
2015-03-14 09:20:52 +00:00
Vasileios Kalintiris 6611eb35f1 [mips] Remove trivial header for the Mips16HardFloat pass. NFC.
llvm-svn: 232259
2015-03-14 09:02:23 +00:00
Vasileios Kalintiris 6312f516ee [mips] Remove trivial header for the MipsOs16 pass. NFC.
llvm-svn: 232258
2015-03-14 08:34:25 +00:00
David Blaikie 741c8f81e4 [opaque pointer type] Start migrating GEP creation to explicitly specify the pointee type
I'm just going to migrate these in a pretty ad-hoc & incremental way -
providing the backwards compatible API for now, then locally removing
it, fixing a few callers, adding it back in and commiting those callers.
Rinse, repeat.

The assertions should ensure that if I get this wrong we'll find out
about it and not just have one giant patch to revert, recommit, revert,
recommit, etc.

llvm-svn: 232240
2015-03-14 01:53:18 +00:00
Benjamin Kramer bd5ee505c9 CommandLine: Replace cold std::sort with array_pod_sort.
Also replace an old use of qsort with it. Compiles down to the same thing but
gives us some type safety. Safes a couple of kb on CommandLine.o.

NFC.

llvm-svn: 232236
2015-03-14 00:20:13 +00:00
Peter Collingbourne c9f277f754 LowerBitSets: Do not export symbols for bit set referenced globals on Darwin.
The linker on that platform may re-order symbols or strip dead symbols, which
will break bit set checks. Avoid this by hiding the symbols from the linker.

llvm-svn: 232235
2015-03-14 00:00:49 +00:00
Rafael Espindola e7ce9ec398 Use add32ri8 and friends on fast isel.
This fixes pr22854.

The core issue on the bug is that there are multiple instructions that
print the same in assembly. In fact, there doesn't seem to be any
syntax for specifying that a constant that fits in 8 bits should use a 32 bit
immediate.

The attached patch changes fast isel to consider i16immSExt8,
i32immSExt8, and i64immSExt8. They were disabled because fastisel didn’t know
to call the predicate back in the day.

llvm-svn: 232223
2015-03-13 22:18:18 +00:00
Alexei Starovoitov 58a615f9d0 bpf: turn on HasJIT flag in BPF backend
basic tests that use BPF backend to produce code in memory are passing.

llvm-svn: 232222
2015-03-13 22:03:25 +00:00
Rafael Espindola cba833a09d Be lazy about loading metadata in IRObjectFile.
This speeds up llvm-ar building lib64/libclangSema.a with debug IR files
from 8.658015807 seconds to just 0.351036519 seconds :-)

llvm-svn: 232221
2015-03-13 21:54:20 +00:00
Benjamin Kramer 848c9facc8 BranchFolding: MergePotentialsElt has a total order, just call array_pod_sort.
No functionality change intended.

llvm-svn: 232217
2015-03-13 21:17:02 +00:00
David Blaikie b9263570a5 [opaque pointer type] Bitcode support for explicit type parameter on the gep operator
This happened to be fairly easy to support backwards compatibility based
on the number of operands (old format had an even number, new format has
one more operand so an odd number).

test/Bitcode/old-aliases.ll already appears to test old gep operators
(if I remove the backwards compatibility in the BitcodeReader, this and
another test fail) so I'm not adding extra test coverage here.

llvm-svn: 232216
2015-03-13 21:03:36 +00:00
David Blaikie 4a5c8c602c Turn assertion into bitcode reading error
I don't think we test invalid bitcode records in any detail, so no test
here - just a change for consistency with existing error checks in
surrounding code.

llvm-svn: 232215
2015-03-13 21:03:34 +00:00
Robert Lougher 1858ba7626 Reapply "[Reassociate] Add initial support for vector instructions."
This reapplies the patch previously committed at revision 232190.  This was
reverted at revision 232196 as it caused test failures in tests that did not
expect operands to be commuted.  I have made the tests more resilient to
reassociation in revision 232206.

llvm-svn: 232209
2015-03-13 20:53:01 +00:00
Alexei Starovoitov a208faa0a3 bpf: fix build
fix missed bits which were left over after r231987

Signed-off-by: Alexei Starovoitov <ast@plumgrid.com>
llvm-svn: 232208
2015-03-13 20:49:38 +00:00
Duncan P. N. Exon Smith be95b4afc6 instcombine: alloca: Canonicalize scalar allocation array size
As a follow-up to r232200, add an `-instcombine` to canonicalize scalar
allocations to `i32 1`.  Since r232200, `iX 1` (for X != 32) are only
created by RAUWs, so this shouldn't fire too often.  Nevertheless, it's
a cheap check and a nice cleanup.

llvm-svn: 232202
2015-03-13 19:42:09 +00:00
Duncan P. N. Exon Smith 07ff9b03f6 instcombine: alloca: Limit array size type promotion
Move type promotion of the size of the array allocation to the end of
`simplifyAllocaArraySize()`.  This avoids promoting the type of the
array size if it's a `ConstantInt`, since the next -instcombine
iteration will drop it to a scalar allocation anyway.  Similarly, this
avoids promoting the type if it's an `UndefValue`, in which case the
alloca gets RAUW'ed.

This is NFC when considered over the lifetime of -instcombine, since
it's just reducing the number of iterations needed to reach fixed point.

llvm-svn: 232201
2015-03-13 19:34:55 +00:00
Duncan P. N. Exon Smith 720762e2c0 AsmWriter: Write alloca array size explicitly (and -instcombine fixup)
Write the `alloca` array size explicitly when it's non-canonical.
Previously, if the array size was `iX 1` (where X is not 32), the type
would mutate to `i32` when round-tripping through assembly.

The testcase I added fails in `verify-uselistorder` (as well as
`FileCheck`), since the use-lists for `i32 1` and `i64 1` change.
(Manman Ren came across this when running `verify-uselistorder` on some
non-trivial, optimized code as part of PR5680.)

The type mutation started with r104911, which allowed array sizes to be
something other than an `i32`.  Starting with r204945, we
"canonicalized" to `i64` on 64-bit platforms -- and then on every
round-trip through assembly, mutated back to `i32`.

I bundled a fixup for `-instcombine` to avoid r204945 on scalar
allocations.  (There wasn't a clean way to sequence this into two
commits, since the assembly change on its own caused testcase churn, and
the `-instcombine` change can't be tested without the assembly changes.)

An obvious alternative fix -- change `AllocaInst::AllocaInst()`,
`AsmWriter` and `LLParser` to treat `intptr_t` as the canonical type for
scalar allocations -- was rejected out of hand, since this required
teaching them each about the data layout.

A follow-up commit will add an `-instcombine` to canonicalize the scalar
allocation array size to `i32 1` rather than leaving `iX 1` alone.

rdar://problem/20075773

llvm-svn: 232200
2015-03-13 19:30:44 +00:00
Duncan P. N. Exon Smith bb730135c9 instcombine: alloca: Remove nesting in simplifyAllocaArraySize(), NFC
llvm-svn: 232199
2015-03-13 19:26:33 +00:00
Manman Ren 4a9b0ebe83 Add a parameter for getLazyBitcodeModule to lazily load Metadata.
We only defer loading metadata inside ParseModule when ShouldLazyLoadMetadata
is true and we have not loaded any Metadata block yet.

This commit implements all-or-nothing loading of Metadata. If there is a
request to load any metadata block, we will load all deferred metadata blocks.

We make sure the deferred metadata blocks are loaded before we materialize any
function or a module.

The default value of the added parameter ShouldLazyLoadMetadata for
getLazyBitcodeModule is false, so the default behavior stays the same.

We only set the parameter to true when creating LTOModule in local contexts.
These can only really be used for parsing symbols, so it's unnecessary to ever
load the metadata blocks.

If we are going to enable lazy-loading of Metadata for other usages of
getLazyBitcodeModule, where deferred metadata blocks need to be loaded, we can
expose BitcodeReader::materializeMetadata to Module, similar to
Module::materialize.

rdar://19804575

llvm-svn: 232198
2015-03-13 19:24:30 +00:00
Duncan P. N. Exon Smith c6820ec1c2 instcombine: alloca: Split out simplifyAllocaArraySize(), NFC
Follow-up commits will change some of the logic here.  Splitting into a
separate function simplifies the logic by allowing early returns instead
of deeper nesting.

llvm-svn: 232197
2015-03-13 19:22:03 +00:00
Robert Lougher 5e0ea66d59 Revert: "[Reassociate] Add initial support for vector instructions."
This reverts revision 232190 due to buildbot failure reported on clang-hexagon-elf
for test arm64_vtst.c.  To be investigated.

llvm-svn: 232196
2015-03-13 19:20:46 +00:00
Robert Lougher 1bad505c3c [Reassociate] Add initial support for vector instructions.
This patch adds initial support for vector instructions to the reassociation
pass. It enables most parts of the pass to work with vectors but to keep the
size of the patch small, optimization of Xor trees, canonicalization of
negative constants and converting shifts to muls, etc., have been left out.
This will be handled in later patches.

The patch is based on an initial patch by Chad Rosier.

Differential Revision: http://reviews.llvm.org/D7566

llvm-svn: 232190
2015-03-13 18:33:27 +00:00
Sanjoy Das f1e9e1df25 [SCEV] Fix PR22856.
Summary:
ScalarEvolutionExpander assumes that the header block of a loop is a
legal place to have a use for a phi node.  This is true only for phis
that are either in the header or dominate the header block, but it is
not true for phi nodes that are strictly internal to the loop body.

This change teaches ScalarEvolutionExpander to place uses of PHI nodes
in the basic block the PHI nodes belong to.  This is always legal, and
`hoistIVInc` ensures that the said position dominates `IsomorphicInc`.

Reviewers: atrick

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8311

llvm-svn: 232189
2015-03-13 18:31:19 +00:00
David Blaikie f72d05bc7b [opaque pointer type] Add textual IR support for explicit type parameter to gep operator
Similar to gep (r230786) and load (r230794) changes.

Similar migration script can be used to update test cases, which
successfully migrated all of LLVM and Polly, but about 4 test cases
needed manually changes in Clang.

(this script will read the contents of stdin and massage it into stdout
- wrap it in the 'apply.sh' script shown in previous commits + xargs to
apply it over a large set of test cases)

import fileinput
import sys
import re

rep = re.compile(r"(getelementptr(?:\s+inbounds)?\s*\()((<\d*\s+x\s+)?([^@]*?)(|\s*addrspace\(\d+\))\s*\*(?(3)>)\s*)(?=$|%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|zeroinitializer|<|\[\[[a-zA-Z]|\{\{)", re.MULTILINE | re.DOTALL)

def conv(match):
  line = match.group(1)
  line += match.group(4)
  line += ", "
  line += match.group(2)
  return line

line = sys.stdin.read()
off = 0
for match in re.finditer(rep, line):
  sys.stdout.write(line[off:match.start()])
  sys.stdout.write(conv(match))
  off = match.end()
sys.stdout.write(line[off:])

llvm-svn: 232184
2015-03-13 18:20:45 +00:00
Jan Vesely 7a9cca9e7d r600: Clear visited structure before running.
Fixes random crashes in for-loop piglit.

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Matt Arsenault <Matthew.Arsenault@amd.com>
llvm-svn: 232181
2015-03-13 17:32:46 +00:00
Jan Vesely 18b289f590 r600: Use deque and simplify loops in AMDGPUCFGStructurizer
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Matt Arsenault <Matthew.Arsenault@amd.com>
llvm-svn: 232180
2015-03-13 17:32:43 +00:00
Andrea Di Biagio 510feca1b8 [X86][AVX] Fix wrong lowering of v4x64 shuffles into concat_vector plus extract_subvector nodes.
This patch fixes a bug in the shuffle lowering logic implemented by function
'lowerV2X128VectorShuffle'.

The are few cases where function 'lowerV2X128VectorShuffle' wrongly expands a
shuffle of two v4X64 vectors into a CONCAT_VECTORS of two EXTRACT_SUBVECTOR
nodes. The problematic expansion only occurs when the shuffle mask M has an
'undef' element at position 2, and M is equivalent to mask <0,1,4,5>.
In that case, the algorithm propagates the wrong vector to one of the two
new EXTRACT_SUBVECTOR nodes.

Example:
;;
define <4 x double> @test(<4 x double> %A, <4 x double> %B) {
entry:
  %0 = shufflevector <4 x double> %A, <4 x double> %B, <4 x i32><i32 undef, i32 1, i32 undef, i32 5>
  ret <4 x double> %0
}
;;

Before this patch, llc (-mattr=+avx) generated:
  vinsertf128 $1, %xmm0, %ymm0, %ymm0

With this patch, llc correctly generates:
  vinsertf128 $1, %xmm1, %ymm0, %ymm0

Added test lower-vec-shuffle-bug.ll

Differential Revision: http://reviews.llvm.org/D8259

llvm-svn: 232179
2015-03-13 17:29:49 +00:00
Benjamin Kramer 76e37aa334 unique_ptrs are unique already, no need to unique them any further.
llvm-svn: 232178
2015-03-13 16:59:29 +00:00
David Majnemer e2a4b856d8 ConstantFold: Fix big shift constant folding
Constant folding for shift IR instructions ignores all bits above 32 of
second argument (shift amount).
Because of that, some undef results are not recognized and APInt can
raise an assert failure if second argument has more than 64 bits.

Patch by Paweł Bylica!

Differential Revision: http://reviews.llvm.org/D7701

llvm-svn: 232176
2015-03-13 16:39:46 +00:00
Daniel Sanders 60f1db0525 Recommit r232027 with PR22883 fixed: Add infrastructure for support of multiple memory constraints.
The operand flag word for ISD::INLINEASM nodes now contains a 15-bit
memory constraint ID when the operand kind is Kind_Mem. This constraint
ID is a numeric equivalent to the constraint code string and is converted
with a target specific hook in TargetLowering.

This patch maps all memory constraints to InlineAsm::Constraint_m so there
is no functional change at this point. It just proves that using these
previously unused bits in the encoding of the flag word doesn't break
anything.

The next patch will make each target preserve the current mapping of
everything to Constraint_m for itself while changing the target independent
implementation of the hook to return Constraint_Unknown appropriately. Each
target will then be adapted in separate patches to use appropriate
Constraint_* values.

PR22883 was caused the matching operands copying the whole of the operand flags
for the matched operand. This included the constraint id which needed to be
replaced with the operand number. This has been fixed with a conversion
function. Following on from this, matching operands also used the operand
number as the constraint id. This has been fixed by looking up the matched
operand and taking it from there. 

llvm-svn: 232165
2015-03-13 12:45:09 +00:00
Toma Tabacu e95a49118c [mips] [IAS] Refactor MipsTargetStreamer::emitMipsAbiFlags(). NFC.
Summary: Make emitMipsAbiFlags a direct member of MipsTargetELFStreamer, as that's the only place where it's used, and remove the empty implementations from MipsTargetStreamer and MipsTargetAsmStreamer.

Reviewers: dsanders, rafael

Reviewed By: rafael

Subscribers: rafael, llvm-commits

Differential Revision: http://reviews.llvm.org/D8199

llvm-svn: 232161
2015-03-13 11:40:01 +00:00
Owen Anderson 41a185c521 Teach TBAA analysis to report errors on cyclic TBAA metadata rather than hanging.
llvm-svn: 232144
2015-03-13 07:09:33 +00:00
Owen Anderson 08f46e1de6 Fix an infinite recursion in the verifier caused by calling isSized on a recursive type.
llvm-svn: 232143
2015-03-13 06:41:26 +00:00
Hao Liu 04183242b3 [MachineCopyPropagation] Fix a bug causing incorrect removal for the instruction sequences as follows
%Q5_Q6<def> = COPY %Q2_Q3
   %D5<def> =
   %D3<def> =
   %D3<def> = COPY %D6     // Incorrectly removed in MachineCopyPropagation
   Using of %D3 results in incorrect result ...

   Reviewed in http://reviews.llvm.org/D8242 

llvm-svn: 232142
2015-03-13 05:15:23 +00:00
Nick Lewycky b6ef9a14de When forming an addrec out of a phi don't just look at the last computation and steal its flags for our own, there may be other computations in the middle. Check whether the LHS of the computation is the phi itself and then we know it's safe to steal the flags. Fixes PR22795.
There's a missed optimization opportunity where we could look at the full chain of computation and take the intersection of the flags instead of only looking one instruction deep.

llvm-svn: 232134
2015-03-13 01:37:52 +00:00
Eric Christopher ef9e01eada Use the cached subtarget off of the machine function.
llvm-svn: 232129
2015-03-13 00:49:50 +00:00
Eric Christopher 5ab3b79ba8 Use the cached subtarget off of the machine function.
llvm-svn: 232128
2015-03-13 00:38:19 +00:00
Sanjay Patel 4339abe66f [X86, AVX2] Replace inserti128 and extracti128 intrinsics with generic shuffles
This should complete the job started in r231794 and continued in r232045:
We want to replace as much custom x86 shuffling via intrinsics
as possible because pushing the code down the generic shuffle
optimization path allows for better codegen and less complexity
in LLVM.

AVX2 introduced proper integer variants of the hacked integer insert/extract
C intrinsics that were created for this same functionality with AVX1.

This should complete the removal of insert/extract128 intrinsics.

The Clang precursor patch for this change was checked in at r232109.

llvm-svn: 232120
2015-03-12 23:16:18 +00:00
Eric Christopher 7fde301d5b Move a variable into the assert where it's used - fixes a -Asserts
build warning/error.

llvm-svn: 232119
2015-03-12 23:13:03 +00:00
Eric Christopher ae32649ff2 In preparation for moving ARM's TargetRegisterInfo to the TargetMachine
merge Thumb1RegisterInfo and Thumb2RegisterInfo. This will enable
us to match the TargetMachine for our TargetRegisterInfo classes.

llvm-svn: 232117
2015-03-12 22:48:50 +00:00