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17215 Commits

Author SHA1 Message Date
Duncan Sands c76ae9c8e0 Add datalayout information for the IEEE quad precision fp128 type. 
llvm-svn: 126780
 2011-03-01 20:56:50 +00:00
Bill Wendling 3b1459b810 Narrow right shifts need to encode their immediates differently from a normal 
shift.

   16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
   32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
   64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>

llvm-svn: 126723
 2011-03-01 01:00:59 +00:00
Chris Lattner 0c6cb46ac1 add a note 
llvm-svn: 126719
 2011-03-01 00:24:51 +00:00
Renato Golin ec0fc7d842 Fix .fpu printing in ARM assembly, regarding bug http://llvm.org/bugs/show_bug.cgi?id=8931 
llvm-svn: 126689
 2011-02-28 22:04:27 +00:00
Kevin Enderby 63b0d108a2 Add missing whitespace in the formatting. 
llvm-svn: 126687
 2011-02-28 21:45:12 +00:00
Chris Lattner c93d207e8c fix a signed comparison warning. 
llvm-svn: 126682
 2011-02-28 20:50:35 +00:00
David Greene 20a1cbefad [AVX] Add decode support for VUNPCKLPS/D instructions, both 128-bit 
and 256-bit forms.  Because the number of elements in a vector
      does not determine the vector type (4 elements could be v4f32 or
      v4f64), pass the full type of the vector to decode routines.

llvm-svn: 126664
 2011-02-28 19:06:56 +00:00
Kevin Enderby 58775fea6f Fix the arm's disassembler for blx that was building an MCInst without the 
needed two predicate operands before the imm operand.

llvm-svn: 126662
 2011-02-28 18:46:31 +00:00
Evan Cheng 6e3d443646 Fix a typo which cause dag combine crash. rdar://9059537. 
llvm-svn: 126661
 2011-02-28 18:45:27 +00:00
Stuart Hastings 67c5c3e939 Support for byval parameters on ARM. Will be enabled by a forthcoming 
patch to the front-end.  Radar 7662569.

llvm-svn: 126655
 2011-02-28 17:17:53 +00:00
Kalle Raiskila 612b85e58c Add branch hinting for SPU. 
The implemented algorithm is overly simplistic (just speculate all branches are
taken)- this is work in progress.

llvm-svn: 126651
 2011-02-28 14:08:24 +00:00
Che-Liang Chiou 75a800d3bf Add preliminary support for .f32 in the PTX backend. 
- Add appropriate TableGen patterns for fadd, fsub, fmul.
- Add .f32 as the PTX type for the LLVM float type.
- Allow parameters, return values, and global variable declarations
  to accept the float type.
- Add appropriate test cases.

Patch by Justin Holewinski

llvm-svn: 126636
 2011-02-28 06:34:09 +00:00
Benjamin Kramer 25bddae404 Silence enum conversion warnings. 
llvm-svn: 126578
 2011-02-27 18:13:53 +00:00
NAKAMURA Takumi d4e5003a3f Target/X86: Always emit "push/pop GPRs" in prologue/epilogue and emit "spill/reload frames" for XMMs. 
It improves Win64's prologue/epilogue but it would not affect ia32 and amd64 (lack of nonvolatile XMMs).

llvm-svn: 126568
 2011-02-27 08:47:19 +00:00
Benjamin Kramer 26691d9660 Add some DAGCombines for (adde 0, 0, glue), which are useful to optimize legalized code for large integer arithmetic. 
1. Inform users of ADDEs with two 0 operands that it never sets carry
2. Fold other ADDs or ADDCs into the ADDE if possible

It would be neat if we could do the same thing for SETCC+ADD eventually, but we can't do that in target independent code.

llvm-svn: 126557
 2011-02-26 22:48:07 +00:00
Owen Anderson b2c80da4ae Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS. 
llvm-svn: 126518
 2011-02-25 21:41:48 +00:00
Cameron Zwarich fcf51fd298 Roll out r126425 and r126450 to see if it fixes the failures on the buildbots. 
llvm-svn: 126488
 2011-02-25 16:30:32 +00:00
Bob Wilson e3ecd5fb9b Add patterns to use post-increment addressing for Neon VST1-lane instructions. 
llvm-svn: 126477
 2011-02-25 06:42:42 +00:00
Evan Cheng a921dc5860 Fix typo. 
llvm-svn: 126467
 2011-02-25 01:29:29 +00:00
Evan Cheng 70d29634a9 Each prologue may have multiple vpush instructions to store callee-saved 
D registers since the vpush list may not have gaps. Make sure the stack
adjustment instruction isn't moved between them. Ditto for vpop in
epilogues.

Sorry, can't reduce a small test case.
rdar://9043312

llvm-svn: 126457
 2011-02-25 00:24:46 +00:00
Chris Lattner 0152b7bc7c remove command line option debugging hook. 
llvm-svn: 126441
 2011-02-24 21:53:03 +00:00
Devang Patel b037383a35 Enable DebugInfo support for COFF object files. 
Patch by Nathan Jeffords!

llvm-svn: 126425
 2011-02-24 21:04:00 +00:00
Richard Osborne 42f52e737e Add XCore intrinsic for eeu instruction. 
llvm-svn: 126384
 2011-02-24 13:39:18 +00:00
Evan Cheng 3923466e82 Fix bug in X86 folding / unfolding table. Int_CMPSDrm and Int_CMPSSrm memory 
operands starts at index 2, not 1.
rdar://9045024
PR9305

llvm-svn: 126359
 2011-02-24 02:36:52 +00:00
Richard Osborne bfa5cc0e08 Add XCore intrinsic for clre instruction. 
llvm-svn: 126322
 2011-02-23 18:52:05 +00:00
Richard Osborne 4995b05f56 Add llvm.xcore.waitevent intrinsic. The effect of this intrinsic is to enable 
events on the thread and wait until a resource is ready to event. The vector
of the resource that is ready is returned.

llvm-svn: 126320
 2011-02-23 18:35:59 +00:00
Richard Osborne 2c610aa3ed Add XCore intrinsic for the setv instruction. 
llvm-svn: 126315
 2011-02-23 16:46:37 +00:00
Richard Osborne 12377e0947 Fix format for setc instruction. 
llvm-svn: 126314
 2011-02-23 15:20:16 +00:00
Richard Osborne aab96995f6 Add XCore intrinsic for settw instruction. 
llvm-svn: 126313
 2011-02-23 14:45:03 +00:00
Evan Cheng 97e6428014 Change VFPNeonA8 definition to make the code easier to read. 
llvm-svn: 126298
 2011-02-23 02:35:33 +00:00
Evan Cheng d6b641e5bc More fcopysign correctness and performance fix. 
The previous codegen for the slow path (when values are in VFP / NEON
registers) was incorrect if the source is NaN.

The new codegen uses NEON vbsl instruction to copy the sign bit. e.g.
        vmov.i32        d1, #0x80000000
        vbsl    d1, d2, d0
If NEON is not available, it uses integer instructions to copy the sign bit.
rdar://9034702

llvm-svn: 126295
 2011-02-23 02:24:55 +00:00
David Greene 9a6040dc86 [AVX] General VUNPCKL codegen support. 
llvm-svn: 126264
 2011-02-22 23:31:46 +00:00
Joerg Sonnenberger b7e635dcad Use the same (%dx) hack for in[bwl] as for out[bwl]. 
llvm-svn: 126244
 2011-02-22 20:40:09 +00:00
Evan Cheng 04ad35b53f VFP single precision arith instructions can go down to NEON pipeline, but on Cortex-A8 only. 
llvm-svn: 126238
 2011-02-22 19:53:14 +00:00
Roman Divacky e8a93fe8f0 Stack alignment is 16 bytes on FreeBSD/i386 too. 
llvm-svn: 126226
 2011-02-22 17:30:05 +00:00
Evan Cheng 666cf56668 Guard against de-referencing MBB.end(). 
llvm-svn: 126192
 2011-02-22 07:07:59 +00:00
Evan Cheng 2ce663031f available_externally (hidden or not) GVs are always accessed via stubs. rdar://9027648. 
llvm-svn: 126191
 2011-02-22 06:58:34 +00:00
Eric Christopher 919772fd5d Only use blx for external function calls on thumb, these could be fixed 
up by the dynamic linker, but it's better to use the correct instruction
to begin with.

Fixes rdar://9011034

llvm-svn: 126176
 2011-02-22 01:37:10 +00:00
Joerg Sonnenberger 60e7629258 Recognize loopz and loopnz as aliases for loope and loopne. 
From Dimitry Andric.

llvm-svn: 126168
 2011-02-22 00:43:07 +00:00
Rafael Espindola e39062199e Implement xgetbv and xsetbv. 
Patch by Jai Menon.

llvm-svn: 126165
 2011-02-22 00:35:18 +00:00
Evan Cheng 87a9f19f9c Skipping over debugvalue instructions to determine whether the split spot is in a IT block. rdar://9030770 
llvm-svn: 126159
 2011-02-21 23:40:47 +00:00
Devang Patel f3292b2196 Revert r124611 - "Keep track of incoming argument's location while emitting LiveIns." 
In other words, do not keep track of argument's location.  The debugger (gdb) is not prepared to see line table entries for arguments. For the debugger, "second" line table entry marks beginning of function body.
This requires some coordination with debugger to get this working. 
 - The debugger needs to be aware of prolog_end attribute attached with line table entries.
 - The compiler needs to accurately mark prolog_end in line table entries (at -O0 and at -O1+)

llvm-svn: 126155
 2011-02-21 23:21:26 +00:00
Sean Callanan 5e8603d1b9 Fixed a bug in the X86 disassembler where a member of the 
X86 instruction decode structure was being interpreted as
being in units of bits, although it is actually stored in
units of bytes.

llvm-svn: 126147
 2011-02-21 21:55:05 +00:00
Richard Osborne 1ae65c7cb8 Add XCore intrinsics for various instructions on ports. 
llvm-svn: 126132
 2011-02-21 18:23:30 +00:00
Duncan Sands bda7175a43 The stack should be 16 byte aligned on 32 bit solaris. Patch by Yuri. 
llvm-svn: 126130
 2011-02-21 17:37:17 +00:00
Chris Lattner 5237febf0c a serious "compare CSE" issue that is nontrivial to get right, 
but which is responsible for us doing really bad things to 256.bzip2.

llvm-svn: 126126
 2011-02-21 17:03:47 +00:00
NAKAMURA Takumi 860abd0f28 Target/X86/X86FastISel: [PR6275] Fix Win32's dllimport function with fastisel. 
"dllimport" function must not be GlobalVariable, but Function. It is enough to check with GlobalValue.
test/CodeGen/X86/dll-linkage.ll is updated to check llc -O0.

llvm-svn: 126110
 2011-02-21 04:50:06 +00:00
Venkatraman Govindaraju a82203f875 Generate correct Sparc32 ABI compliant code for functions that return a struct. 
llvm-svn: 126108
 2011-02-21 03:42:44 +00:00
Chris Lattner e9cba7bd34 add a missed loop deletion case. 
llvm-svn: 126103
 2011-02-21 02:13:39 +00:00
Chris Lattner 659c793a4e add an idiom that loop idiom could theoretically catch. 
llvm-svn: 126101
 2011-02-21 01:33:38 +00:00