Commit Graph

12286 Commits

Author SHA1 Message Date
Jeffrey Yasskin b40d3f76a0 Fix DenseMap iterator constness.
This patch forbids implicit conversion of DenseMap::const_iterator to
DenseMap::iterator which was possible because DenseMapIterator inherited
(publicly) from DenseMapConstIterator. Conversion the other way around is now
allowed as one may expect.

The template DenseMapConstIterator is removed and the template parameter
IsConst which specifies whether the iterator is constant is added to
DenseMapIterator.

Actually IsConst parameter is not necessary since the constness can be
determined from KeyT but this is not relevant to the fix and can be addressed
later.

Patch by Victor Zverovich!

llvm-svn: 86636
2009-11-10 01:02:17 +00:00
David Goodwin 0d412c2528 Fixed to address code review. No functional changes.
llvm-svn: 86634
2009-11-10 00:48:55 +00:00
David Goodwin cf89db135e Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies.
llvm-svn: 86628
2009-11-10 00:15:47 +00:00
Jim Grosbach 2524b04d0e Now that the default is 'enabled,' a separate command line option for ARM is
not necessary.

llvm-svn: 86621
2009-11-09 23:11:45 +00:00
Jim Grosbach 1218b804fb Enable dynamic stack realignment by default.
llvm-svn: 86604
2009-11-09 22:32:40 +00:00
Jim Grosbach 55d3480769 Set dynamic stack realignment to real values.
llvm-svn: 86602
2009-11-09 22:32:03 +00:00
Bill Wendling 787997f77e Similar to r86588, but for Darwin this time.
llvm-svn: 86592
2009-11-09 21:45:26 +00:00
Bill Wendling 7307bff420 The jump table was being generated before the end label for exception handling
was generated. This caused code like this:

## The asm code for the function
        .section        __TEXT,__const
        .align  2
lJTI11_0:
LJTI11_0:
        .long    LBB11_16
        .long    LBB11_4
        .long    LBB11_5
        .long    LBB11_6
        .long    LBB11_7
        .long    LBB11_8
        .long    LBB11_9
        .long    LBB11_10
        .long    LBB11_11
        .long    LBB11_12
        .long    LBB11_13
        .long    LBB11_14
Leh_func_end11:   ## <---now in the wrong section!

The `Leh_func_end11' would then end up in the wrong section, causing the
resulting EH frame information to be wrong:

__ZL11CheckRightsjPKcbRbRP6NSData.eh:
    .set    Lset500eh,Leh_frame_end11-Leh_frame_begin11
    .long   Lset500eh  ; Length of Frame Information Entry                                                                                                                   
Leh_frame_begin11:
    .long   Leh_frame_begin11-Leh_frame_common
    .long   Leh_func_begin11-.
    .set    Lset501eh,Leh_func_end11-Leh_func_begin11
    .long   Lset501eh                                   ; FDE address range                                                                                                                                   
`Lset501eh' is now something huge instead of the real value.

The X86 back-end generates the jump table after the EH information is
emitted. Do the same here.

llvm-svn: 86588
2009-11-09 21:20:14 +00:00
Jim Grosbach ad95414c26 Work around assembler not recognizing #0.0 form immediate for vmcp
llvm-svn: 86548
2009-11-09 15:27:51 +00:00
Bruno Cardoso Lopes 8dd7c54a42 Fix PR5149.
http://llvm.org/bugs/show_bug.cgi?id=5149

llvm-svn: 86543
2009-11-09 14:27:49 +00:00
Jim Grosbach d7cf55cd0e Use Unified Assembly Syntax for the ARM backend.
llvm-svn: 86494
2009-11-09 00:11:35 +00:00
Anton Korobeynikov 700c4ab3f9 Add and-not (bic) patterns. Based heavily on patch by Brian Lucas!
llvm-svn: 86471
2009-11-08 15:33:12 +00:00
Anton Korobeynikov e92c508764 Move OR patterns upper to all logical stuff. No functionality change.
llvm-svn: 86470
2009-11-08 15:32:44 +00:00
Anton Korobeynikov a404d61c8e Some nice peephole patterns. Based on patch by Brian Lucas!
llvm-svn: 86469
2009-11-08 15:32:28 +00:00
Anton Korobeynikov fd9a893cab Print tab before operand of jcc
llvm-svn: 86468
2009-11-08 15:32:11 +00:00
Anton Korobeynikov 4ca8d3a6a6 Fix invalid operand updates & implement post-inc memory operands
llvm-svn: 86466
2009-11-08 14:27:38 +00:00
Anton Korobeynikov eb8692cff9 Throw an error when stack realignment stuff fails instead of silent
code miscompilation

llvm-svn: 86463
2009-11-08 12:58:40 +00:00
Chris Lattner 295f266370 Make TargetData::getStringRepresentation spit out native integer types,
this gives llvm-gcc generated modules the right data.

llvm-svn: 86435
2009-11-08 02:32:01 +00:00
Jim Grosbach a15c3b7124 Use aligned load/store instructions for spilling Q registers when we know the stack slot is 128 bit aligned
llvm-svn: 86425
2009-11-08 00:27:19 +00:00
Evan Cheng fe864425cb Refactor code.
llvm-svn: 86423
2009-11-08 00:15:23 +00:00
Nate Begeman 3a313df69b x86 vector shuffle cleanup/fixes:
1. rename the movhp patfrag to movlhps, since thats what it actually matches
2. eliminate the bogus movhps load and store patterns, they were incorrect.  The load transforms are already handled (correctly) by shufps/unpack.
3. revert a recent test change to its correct form.

llvm-svn: 86415
2009-11-07 23:17:15 +00:00
Jim Grosbach 4e9f379554 80-column cleanup of file header comments
llvm-svn: 86408
2009-11-07 22:00:39 +00:00
Jim Grosbach d1d002a6fe Support alignment specifier for NEON vld/vst instructions
llvm-svn: 86404
2009-11-07 21:25:39 +00:00
Nick Lewycky b9397262b7 Improve tail call elimination to handle the switch statement.
llvm-svn: 86403
2009-11-07 21:10:15 +00:00
Evan Cheng 8b5278a466 t2ldrpci_pic can be used for blockaddress as well.
llvm-svn: 86400
2009-11-07 19:40:04 +00:00
Chris Lattner 8714348afd indicate what the native integer types for the target are.
Please verify.

llvm-svn: 86397
2009-11-07 19:07:32 +00:00
Anton Korobeynikov cf84ab5043 First try of the post-inc operands handling... Not fully worked, though :(
llvm-svn: 86386
2009-11-07 17:15:25 +00:00
Anton Korobeynikov d3c8319f48 Add some dummy support for post-incremented loads
llvm-svn: 86385
2009-11-07 17:15:06 +00:00
Anton Korobeynikov f93bb39b03 Add 8 bit libcalls and make use of them for msp430
llvm-svn: 86384
2009-11-07 17:14:39 +00:00
Anton Korobeynikov e61e0b9a74 Add few pseudo-source-values
llvm-svn: 86383
2009-11-07 17:13:57 +00:00
Anton Korobeynikov 2a88785685 Initial support for addrmode handling. Tests by Brian Lucas!
llvm-svn: 86382
2009-11-07 17:13:35 +00:00
Anton Korobeynikov 1bbc8d2a86 Some preliminary variable asmprinting
llvm-svn: 86381
2009-11-07 17:12:58 +00:00
Anton Korobeynikov 3b7c712e9e Use '.L' for global private prefix (as mspgcc)
llvm-svn: 86380
2009-11-07 17:12:38 +00:00
Anton Korobeynikov e04fa15cb3 Drop old asmprinter stuff
llvm-svn: 86379
2009-11-07 17:12:21 +00:00
Anton Korobeynikov 226467d6a6 It turns out that the testcase in question uncovered subreg-handling bug.
Add assert in asmprinter to catch such cases and xfail the tests.
PR is to be filled.

llvm-svn: 86375
2009-11-07 15:20:32 +00:00
Chris Lattner a381effe72 add the ability for TargetData to return information about legal integer
datatypes on a given CPU.  This is intended to allow instcombine and other
transformations to avoid converting big sequences of operations to an
inconvenient width, and will help clean up after SRoA.  See also "Adding 
legal integer sizes to TargetData" on Feb 1, 2009 on llvmdev, and PR3451.

Comments welcome.

llvm-svn: 86370
2009-11-07 09:35:34 +00:00
Chris Lattner 91f9582fe1 more cleanup.
llvm-svn: 86369
2009-11-07 09:23:04 +00:00
Chris Lattner d82510e109 add some missing #includes
llvm-svn: 86367
2009-11-07 09:20:54 +00:00
Chris Lattner f819398067 rewrite TargetData to use StringRef/raw_ostream instead of thrashing std::strings.
llvm-svn: 86366
2009-11-07 09:13:23 +00:00
Jeffrey Yasskin db5f24ce77 Make the need-stub variables accurate and consistent. In the case of
MachineRelocations, "stub" always refers to a far-call stub or a
load-a-faraway-global stub, so this patch adds "Far" to the term. (Other stubs
are used for lazy compilation and dlsym address replacement.) The variable was
also inconsistent between the positive and negative sense, and the positive
sense ("NeedStub") was more demanding than is accurate (since a nearby-enough
function can be called directly even if the platform often requires a stub).
Since the negative sense causes double-negatives, I switched to
"MayNeedFarStub" globally.

llvm-svn: 86363
2009-11-07 08:51:52 +00:00
Eric Christopher bd05185ef1 Fix a couple of shuffle patterns to use movhlps instead
of movhps as the constraint.  Changes optimizations so
update testcases as appropriate as well.

llvm-svn: 86360
2009-11-07 08:45:53 +00:00
Mon P Wang 5321dd8823 Fixed Overload table bug noticed by Jakob
llvm-svn: 86332
2009-11-07 04:07:33 +00:00
Evan Cheng a8e8a7c976 Refactor code. Fix a potential missing check. Teach isIdentical() about tLDRpci_pic.
llvm-svn: 86330
2009-11-07 04:04:34 +00:00
Evan Cheng 7ff831962a - Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdentical
except it doesn't care if the definitions' virtual registers differ. This is
  used by machine LICM and other MI passes to perform CSE.
- Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical.
  Since pc relative constantpool entries are always different, this requires it
  it check if the values can actually the same.

llvm-svn: 86328
2009-11-07 03:52:02 +00:00
Ted Kremenek 50dddc8b07 Update CMake file.
llvm-svn: 86325
2009-11-07 03:26:59 +00:00
Kenneth Uildriks 07119737aa Add code to check at SelectionDAGISel::LowerArguments time to see if return values can be lowered to registers. Coming soon, code to perform sret-demotion if return values cannot be lowered to registers
llvm-svn: 86324
2009-11-07 02:11:54 +00:00
Johnny Chen 3467dcb12d My previous patch (r84124) for setting the encoding bits 4 and 7 of DPSoRegFrm
was wrong and too aggressive in the sense that DPSoRegFrm includes both constant
shifts (with Inst{4} = 0) and register controlled shifts (with Inst{4} = 1 and
Inst{7} = 0).  The 'rr' fragment of the multiclass definitions actually means
register/register with no shift, see A8-11.

llvm-svn: 86319
2009-11-07 00:54:36 +00:00
Jim Grosbach 79d70e3e65 80-columns
llvm-svn: 86310
2009-11-07 00:13:30 +00:00
Evan Cheng 207b246650 - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative
load of a GV from constantpool and then add pc. It allows the code sequence to
  be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
  instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
  to this pass. This is done before post regalloc scheduling to allow the
  scheduler to proper schedule these instructions. It also allow them to be
  if-converted and shrunk by later passes.

llvm-svn: 86304
2009-11-06 23:52:48 +00:00
Anton Korobeynikov 9df3acf486 Honour subreg machine operands during asmprinting
llvm-svn: 86303
2009-11-06 23:45:15 +00:00