a585102d3e
add ifdef's to let people easily remove these dead api for testing.
...
llvm-svn: 137483
2011-08-12 18:08:19 +00:00
44f7ab4544
switch to the new struct api.
...
llvm-svn: 137482
2011-08-12 18:07:26 +00:00
01becebef3
switch to the new struct apis.
...
llvm-svn: 137481
2011-08-12 18:07:07 +00:00
335d399a0e
switch to use the new api for structtypes.
...
llvm-svn: 137480
2011-08-12 18:06:37 +00:00
2f50231c10
forward to the correct constructor.
...
llvm-svn: 137479
2011-08-12 18:03:30 +00:00
db4374a28a
Provide fast path as Jakob suggested.
...
llvm-svn: 137478
2011-08-12 18:01:34 +00:00
c5798a3a59
Separate decoding for STREXD and LDREXD to make each work better.
...
llvm-svn: 137476
2011-08-12 17:58:32 +00:00
8a2f747546
add two missing function impls
...
llvm-svn: 137470
2011-08-12 17:43:05 +00:00
190552d3e0
add new accessors to reflect new terminology in struct types.
...
llvm-svn: 137468
2011-08-12 17:31:02 +00:00
62da15a330
Revert r137310 because it does not optimize any code on ToT
...
llvm-svn: 137466
2011-08-12 17:15:04 +00:00
75ec09c0e3
Whitespace and formatting. No functional change intended.
...
llvm-svn: 137463
2011-08-12 16:45:18 +00:00
a41634e307
Silence a bunch (but not all) "variable written but not read" warnings
...
when building with assertions disabled.
llvm-svn: 137460
2011-08-12 14:54:45 +00:00
91ea511436
MachOWriter: Don't crash on fixups with arithmetic, emit a relocation instead. This matches what as does.
...
llvm-svn: 137414
2011-08-12 01:51:29 +00:00
210bf8351d
findDeadCallerSavedReg fix: Missing NULL terminator in register arrays.
...
Fix by Ivan Baev. Sorry I don't have a unit test, but the fix is obvious so I don't want to delay it.
llvm-svn: 137404
2011-08-12 00:49:19 +00:00
10a18d55ce
Don't convert objc_autoreleaseReturnValue to objc_autorelease if the result
...
is returned through a bitcast.
llvm-svn: 137402
2011-08-12 00:36:31 +00:00
121302772d
Don't let arbitrary calls disrupt nested retain+release pairs if
...
the retains and releases all use the same SSA pointer value.
Also, don't let CFG hazards disrupt nested retain+release pair
optimizations.
llvm-svn: 137399
2011-08-12 00:26:31 +00:00
4767a1a117
Use an actual reverse-CFG reverse-postorder for the bottom-up traversal,
...
rather than plain postorder, so that CFG constructs like single-exit loops
are reliably visited in a sensible order.
llvm-svn: 137398
2011-08-12 00:24:29 +00:00
1f582ba609
Simplify the interference checking code a bit.
...
This is possible now that we now longer provide an interface to iterate
the interference overlaps.
llvm-svn: 137397
2011-08-12 00:22:04 +00:00
8cffa28af8
ARM vector compare to zero instruction assembly parsing support.
...
llvm-svn: 137389
2011-08-11 23:51:13 +00:00
2b6860f0a1
Allow loop unrolling to get known trip counts from ScalarEvolution.
...
SCEV unrolling can unroll loops with arbitrary induction variables. It
is a prerequisite for -disable-iv-rewrite performance. It is also
easily handles loops of arbitrary structure including multiple exits
and is generally more robust.
This is under a temporary option to avoid affecting default
behavior for the next couple of weeks. It is needed so that I can
checkin unit tests for updateUnloop.
llvm-svn: 137384
2011-08-11 23:36:16 +00:00
da0192d72b
Remove the InterferenceResult class.
...
llvm-svn: 137381
2011-08-11 22:46:06 +00:00
cd14efaec2
Eliminate the last use of InterferenceResult.
...
The Query class now holds two iterators instead of an InterferenceResult
instance. The iterators are used as bookmarks for repeated
collectInterferingVRegs calls.
llvm-svn: 137380
2011-08-11 22:46:04 +00:00
79d60d0e94
Enclose directive .cprestore with .set macro and nomacro to silence assembler
...
warning.
llvm-svn: 137378
2011-08-11 22:42:31 +00:00
37f7e6b2f4
Remove no-longer-true comments. These are for the assembler, also.
...
llvm-svn: 137375
2011-08-11 22:30:30 +00:00
e25942154c
ARM STRT assembly parsing and encoding.
...
llvm-svn: 137372
2011-08-11 22:18:00 +00:00
eca346ee1a
Make the USAT16 operand decoder auto-generate-able.
...
llvm-svn: 137371
2011-08-11 22:10:11 +00:00
ff0b442330
Add another accidentally omitted predicate operand.
...
llvm-svn: 137370
2011-08-11 22:08:38 +00:00
2f7aa73312
Add missing predicate operand on SMLA and friends.
...
llvm-svn: 137368
2011-08-11 22:05:38 +00:00
a2b8b60646
ARM load shifted register pre-index fix shift value asm parser encoding.
...
llvm-svn: 137367
2011-08-11 22:05:09 +00:00
12d13efa21
Handle new register classes in Thumb2 mode. Should fix the ARM buildbots.
...
llvm-svn: 137364
2011-08-11 21:52:38 +00:00
f05e744857
Making SEL decodings auto-generate-able.
...
llvm-svn: 137363
2011-08-11 21:50:56 +00:00
8fbf023c9b
Add a dag combine to xform 256-bit shuffles into simple vector
...
inserts and extracts. This simple combine makes us generate only 1
instruction instead of 11 in the v8 case.
llvm-svn: 137362
2011-08-11 21:50:44 +00:00
88981ff168
Tidy up comment.
...
llvm-svn: 137359
2011-08-11 21:41:59 +00:00
b685c9f011
Fix decoding support for STREXD and LDREXD.
...
llvm-svn: 137356
2011-08-11 21:34:58 +00:00
da4f0eb12c
Remove more dead code.
...
collectInterferingVRegs will be the primary function for interference
checks.
llvm-svn: 137354
2011-08-11 21:18:34 +00:00
d886f8cd8d
ARM STRH assembly parsing and encoding.
...
llvm-svn: 137353
2011-08-11 21:17:22 +00:00
7e315fc37d
Fix typos in comments, and delete an unused function.
...
llvm-svn: 137352
2011-08-11 21:06:32 +00:00
6d8c039ab1
Add isIndirectBranch flag.
...
llvm-svn: 137351
2011-08-11 21:05:37 +00:00
7519336752
Privatize an unused part of the LiveIntervalUnion::Query interface.
...
No clients are iterating over interference overlaps.
llvm-svn: 137350
2011-08-11 21:00:42 +00:00
3a850f28d0
Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.
...
llvm-svn: 137347
2011-08-11 20:47:56 +00:00
05ff9d1f6d
Remove some dead code.
...
The InterferenceResult iterator turned out to be less important than we
thought it would be. LiveIntervalUnion clients want higher level
information, like the list of interfering virtual registers.
llvm-svn: 137346
2011-08-11 20:41:41 +00:00
2ea19d1438
Tidy up. Remove unused template parameter.
...
llvm-svn: 137345
2011-08-11 20:41:13 +00:00
887c0b1358
Improve operand validation for Thumb2 addressing modes.
...
llvm-svn: 137344
2011-08-11 20:40:40 +00:00
eb09f49a7f
ARM STRD assembly parsing and encoding.
...
llvm-svn: 137342
2011-08-11 20:28:23 +00:00
c12c30a670
Fix for LoopInfo::updateUnloop. Remove subloop blocks from former
...
ancestor loops.
I have a unit test that depends on scev-unroll, which unfortunately
isn't checked in. But I will check it in when I can.
llvm-svn: 137341
2011-08-11 20:27:32 +00:00
6066340301
Continue to tighten decoding by performing more operand validation.
...
llvm-svn: 137340
2011-08-11 20:21:46 +00:00
1b0f79573e
Tidy up.
...
llvm-svn: 137339
2011-08-11 20:13:35 +00:00
2a50260f2f
ARM STRBT assembly parsing and encoding.
...
llvm-svn: 137337
2011-08-11 20:04:56 +00:00
d564bf3181
ARM STR(immediate) assembly parsing and encoding.
...
llvm-svn: 137331
2011-08-11 19:22:40 +00:00
3477f2cea5
Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.
...
llvm-svn: 137325
2011-08-11 19:00:18 +00:00
043c820800
Fix PR10492 by teaching MOVHLPS and MOVLPS mask matching to be more strict.
...
llvm-svn: 137324
2011-08-11 18:59:13 +00:00
0e15b48f3c
Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC.
...
llvm-svn: 137323
2011-08-11 18:55:42 +00:00
e33c95d39b
Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me.
...
llvm-svn: 137322
2011-08-11 18:41:59 +00:00
fa7e6a54b1
Plug a memory leak.
...
llvm-svn: 137321
2011-08-11 18:39:28 +00:00
ed25385227
Improve error checking in the new ARM disassembler. Patch by James Molloy.
...
llvm-svn: 137320
2011-08-11 18:24:51 +00:00
27ad83d8a9
ARM push of a single register encodes as pre-indexed STR.
...
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.
llvm-svn: 137318
2011-08-11 18:07:11 +00:00
266ab10012
Cleanup. Another thorough review by Nick!
...
llvm-svn: 137317
2011-08-11 17:54:58 +00:00
8ba76c6d5c
ARM pop of a single register encodes as post-indexed LDR.
...
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.
llvm-svn: 137316
2011-08-11 17:35:48 +00:00
efdd183f52
Add a comment, per Bruno's CR.
...
llvm-svn: 137313
2011-08-11 17:05:47 +00:00
61140e1028
[AVX] When joining two XMM registers into a YMM register, make sure that the
...
lower XMM register gets in first. This will allow the SUBREG pattern to
elliminate the first vector insertion.
llvm-svn: 137310
2011-08-11 16:49:36 +00:00
1542d5a00a
[AVX] If the data which is going to be saved is already in two XMM registers
...
(for example, after integer operation), do not pack the registers into a YMM
before saving. Its better to save as two XMM registers.
Before:
vinsertf128 $1, %xmm3, %ymm0, %ymm3
vinsertf128 $0, %xmm1, %ymm3, %ymm1
vmovaps %ymm1, 416(%rsp)
After:
vmovaps %xmm3, 416+16(%rsp)
vmovaps %xmm1, 416(%rsp)
llvm-svn: 137308
2011-08-11 16:41:21 +00:00
96710b4308
fix PR10605 / rdar://9930964 by adding a pretty scary missed check.
...
It's somewhat surprising anything works without this. Before we would
compile the testcase into:
test: # @test
movl $4, 8(%rdi)
movl 8(%rdi), %eax
orl %esi, %eax
cmpl $32, %edx
movl %eax, -4(%rsp) # 4-byte Spill
je .LBB0_2
now we produce:
test: # @test
movl 8(%rdi), %eax
movl $4, 8(%rdi)
orl %esi, %eax
cmpl $32, %edx
movl %eax, -4(%rsp) # 4-byte Spill
je .LBB0_2
llvm-svn: 137303
2011-08-11 06:26:54 +00:00
dbd1352c80
Cleanup: Remove Int_ CVTSS2SI* forms
...
llvm-svn: 137297
2011-08-11 02:52:36 +00:00
a2d8bb97b9
Splats for v8i32/v8f32 can be handled by VPERMILPSY. This was causing
...
infinite recursive calls in legalize. Fix PR10562
llvm-svn: 137296
2011-08-11 02:49:44 +00:00
572c9aaf53
Use the splat index to generate the desired shuffle. Otherwise we
...
could only get undefs and the vector shuffle becomes an undef,
generating wrong code.
llvm-svn: 137295
2011-08-11 02:49:41 +00:00
3ae39f8ad1
Fix X86TargetLowering::LowerExternalSymbol so that it actually works in non-trivial cases. This hasn't been an issue before because the function isn't normally called (but apparently is used to generate a tail-call to sin() on ELF x86-32 with PIC and SSE2).
...
Fixes PR9693.
llvm-svn: 137292
2011-08-11 01:48:05 +00:00
784077eb57
Stay within 80 columns.
...
llvm-svn: 137283
2011-08-10 23:58:09 +00:00
d5d6359785
ARM LDRT assembly parsing and encoding.
...
llvm-svn: 137282
2011-08-10 23:43:54 +00:00
d3f7bcd43c
Tidy up. 80 columns.
...
llvm-svn: 137277
2011-08-10 23:23:47 +00:00
d3530b9117
Reapplying r136844.
...
An algorithm for incrementally updating LoopInfo within a
LoopPassManager. The incremental update should be extremely cheap in
most cases and can be used in places where it's not feasible to
regenerate the entire loop forest.
- "Unloop" is a node in the loop tree whose last backedge has been removed.
- Perform reverse dataflow on the block inside Unloop to propagate the
nearest loop from the block's successors.
- For reducible CFG, each block in unloop is visited exactly
once. This is because unloop no longer has a backedge and blocks
within subloops don't change parents.
- Immediate subloops are summarized by the nearest loop reachable from
their exits or exits within nested subloops.
- At completion the unloop blocks each have a new parent loop, and
each immediate subloop has a new parent.
llvm-svn: 137276
2011-08-10 23:22:57 +00:00
cd4dd255c0
ARM LDRH(immediate) assembly parsing and encoding support.
...
llvm-svn: 137260
2011-08-10 22:42:16 +00:00
1d9d5e93d1
ARM LDRD(register) assembly parsing and encoding.
...
Add support for literal encoding of #-0 along the way.
llvm-svn: 137254
2011-08-10 21:56:18 +00:00
bb23a4a9a5
Distinguish between two copies of one inlined variable. Take 2.
...
llvm-svn: 137253
2011-08-10 21:50:54 +00:00
37a62058fe
While extending definition range of a debug variable, consult lexical scopes also. There is no point extending debug variable out side its lexical block. This provides 6x compile time speedup in some cases.
...
llvm-svn: 137250
2011-08-10 21:25:34 +00:00
e30746c844
Revert unintentional parts of previous check-in.
...
llvm-svn: 137249
2011-08-10 21:16:49 +00:00
7e62302fae
Start using LexicalScopes utility. No intetional functionality change.
...
llvm-svn: 137246
2011-08-10 20:55:27 +00:00
f7164b2cfd
Fix typo. Not quite sure how that slipped in there.
...
llvm-svn: 137245
2011-08-10 20:49:18 +00:00
5b96b80644
ARM LDRD(immediate) assembly parsing and encoding support.
...
llvm-svn: 137244
2011-08-10 20:29:19 +00:00
410a11fe82
When performing a truncating store, it is sometimes possible to rearrange the
...
data in-register prior to saving to memory. When we reorder the data in memory
we prevent the need to save multiple scalars to memory, making a single regular
store.
llvm-svn: 137238
2011-08-10 19:30:14 +00:00
e1649c31cb
Provide utility to extract and use lexical scoping information from machine instructions.
...
llvm-svn: 137237
2011-08-10 19:04:06 +00:00
c86a5bd219
Add initial support for decoding NEON instructions in Thumb2 mode.
...
llvm-svn: 137236
2011-08-10 19:01:10 +00:00
6dbb060778
Comments. Thanks for the spell check Nick!
...
Also, my apologies for spoiling the autocomplete on SimplifyInstructions.cpp. I couldn't think of a better filename.
llvm-svn: 137229
2011-08-10 18:07:05 +00:00
3ff111c12d
The following X86 pattern is incorrect:
...
def : Pat<(X86Movss VR128:$src1,
(bc_v4i32 (v2i64 (load addr:$src2)))),
(MOVLPSrm VR128:$src1, addr:$src2)>;
This matches a MOVSS dag with a MOVLPS instruction. However, MOVSS will replace only the low 32 bits of the register, while the MOVLPS instruction will replace the low 64 bits. A testcase is added and illustrates the bug and also modified the one that was already present. Patch by Tanya Lattner.
llvm-svn: 137227
2011-08-10 17:45:17 +00:00
cad9f2af44
Whitespace.
...
llvm-svn: 137226
2011-08-10 17:39:11 +00:00
1531e5cd2b
Tabs --> spaces.
...
llvm-svn: 137225
2011-08-10 17:38:05 +00:00
5d69f63bbb
Cleanups based on Nick Lewycky's feedback.
...
llvm-svn: 137224
2011-08-10 17:36:48 +00:00
732f82c463
Rewrite some ARM InstrInfo functions to be most accepting of arbitrary register subclasses. Hopefully this fixes some buildbots.
...
llvm-svn: 137223
2011-08-10 17:21:20 +00:00
36a3abc671
Add support for the R and Q constraints.
...
llvm-svn: 137217
2011-08-10 16:26:42 +00:00
527bd07934
Clarify a comment.
...
llvm-svn: 137204
2011-08-10 05:02:22 +00:00
4d0040baf8
Invoke SimplifyIndVar when we partially unroll a loop. Fixes PR10534.
...
llvm-svn: 137203
2011-08-10 04:29:49 +00:00
e629d008fb
Cleanup. Make ScalarEvolution an explicit argument of the
...
SimplifyIndVar utility since it is required.
llvm-svn: 137202
2011-08-10 04:22:26 +00:00
74664d5ec6
SimplifyIndVar: make foldIVUser iterative to fold a chain of operands.
...
llvm-svn: 137199
2011-08-10 04:01:31 +00:00
0b0e47d6ad
Update CMake build.
...
llvm-svn: 137198
2011-08-10 03:51:58 +00:00
3ec331eaf4
Added a SimplifyIndVar utility to simplify induction variable users
...
based on ScalarEvolution without changing the induction variable phis.
This utility is the main tool of IndVarSimplifyPass, but the pass also
restructures induction variables in strange ways that are sensitive to
pass ordering. This provides a way for other loop passes to simplify
new uses of induction variables created during transformation. The
utility may be used by any pass that preserves ScalarEvolution. Soon
LoopUnroll will use it.
The net effect in this checkin is to cleanup the IndVarSimplify pass
by factoring out the SimplifyIndVar algorithm into a standalone utility.
llvm-svn: 137197
2011-08-10 03:46:27 +00:00
78b40c3f3a
Cleanup. Added LoopBlocksDFS::perform for simple clients.
...
llvm-svn: 137195
2011-08-10 01:59:05 +00:00
278ffd7d8e
Fix a bug in vpermilps mask checking. Fix PR10560
...
llvm-svn: 137194
2011-08-10 01:54:17 +00:00
b72bbe2a92
Fix the LoopUnroller to handle nontrivial loops and partial unrolling.
...
These are not individual bug fixes. I had to rewrite a good chunk of
the unroller to make it sane. I think it was getting lucky on trivial
completely unrolled loops with no early exits. I included some fairly
simple unit tests for partial unrolling. I didn't do much stress
testing, so it may not be perfect, but should be usable now.
llvm-svn: 137190
2011-08-10 00:28:10 +00:00
8059f0cf8d
Push GPRnopc through a large number of instruction definitions to tighten operand decoding.
...
llvm-svn: 137189
2011-08-10 00:03:03 +00:00
b91e489923
Trim an unneeded header.
...
llvm-svn: 137184
2011-08-09 23:49:21 +00:00
6a14dc01ff
Promote VMOVS to VMOVD when possible.
...
On Cortex-A8, we use the NEON v2f32 instructions for f32 arithmetic. For
better latency, we also send D-register copies down the NEON pipeline by
translating them to vorr instructions.
This patch promotes even S-register copies to D-register copies when
possible so they can also go down the NEON pipeline. Example:
vldr.32 s0, LCPI0_0
loop:
vorr d1, d0, d0
loop2:
...
vadd.f32 d1, d1, d16
The vorr instruction looked like this after regalloc:
%S2<def> = COPY %S0, %D1<imp-def>
Copies involving odd S-registers, and copies that don't define the full
D-register are left alone.
llvm-svn: 137182
2011-08-09 23:41:44 +00:00
Chris Lattner