efb8077ddd
X86 TLS: fix and optimize the implementation of "initial exec" model.
...
llvm-svn: 36355
2007-04-22 22:50:52 +00:00
2518889872
Implement "general dynamic", "initial exec" and "local exec" TLS models for
...
X86 32 bits.
llvm-svn: 36283
2007-04-20 21:38:10 +00:00
8b7aab009e
Implemented correct stack probing on mingw/cygwin for dynamic alloca's.
...
Also, fixed static case in presence of eax livin. This fixes PR331
PS: Why don't we still have push/pop instructions? :)
llvm-svn: 36195
2007-04-17 09:20:00 +00:00
f099841573
Add support for our first SSSE3 instruction "pmulhrsw".
...
llvm-svn: 35869
2007-04-10 22:10:25 +00:00
61eee86487
Mark re-materializable instructions.
...
llvm-svn: 35230
2007-03-21 00:16:56 +00:00
f9e5445ed4
Make LABEL a builtin opcode.
...
llvm-svn: 33537
2007-01-26 14:34:52 +00:00
197aa9634e
Fix a misencoding of CBW and CWD. This fixes PR1030.
...
llvm-svn: 33486
2007-01-24 18:31:00 +00:00
dd60ca029c
- Switch X86-64 JIT to large code size model.
...
- Re-enable some codegen niceties for X86-64 static relocation model codegen.
- Clean ups, etc.
llvm-svn: 32238
2006-12-05 19:50:18 +00:00
ae1cd75af7
- Use a different wrapper node for RIP-relative GV, etc.
...
- Proper support for both small static and PIC modes under X86-64
- Some (non-optimal) support for medium modes.
llvm-svn: 32046
2006-11-30 21:55:46 +00:00
28a9e9b230
Custom lower READCYCLECOUNTER for x86-64.
...
llvm-svn: 32017
2006-11-29 08:28:13 +00:00
9ac6442db6
remove dead/redundant vars
...
llvm-svn: 31435
2006-11-03 23:48:56 +00:00
b51b5c0b1f
Add debug support for X86/ELF targets (Linux). This allows llvm-gcc4
...
generated object modules to be debugged with gdb. Hopefully this helps
pre-release debugging.
llvm-svn: 31299
2006-10-30 22:32:30 +00:00
ab51cf2e78
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
...
llvm-svn: 30945
2006-10-13 21:14:26 +00:00
adcaf294d7
Move the Imp tblgen class from the X86 backend to common code.
...
llvm-svn: 30907
2006-10-12 17:49:27 +00:00
b5cda3daa9
Mark ADJCALLSTACKUP/DOWN as clobbering ESP so that virtregmap will notice
...
that it can't assume ESP is unmodified across the instrs.
llvm-svn: 30905
2006-10-12 17:42:56 +00:00
577ef7694e
Add properties to ComplexPattern.
...
llvm-svn: 30891
2006-10-11 21:03:53 +00:00
e71fe34d75
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
...
llvm-svn: 30844
2006-10-09 20:57:25 +00:00
1da0ab2f58
Delete dead code; fix 80 col violations.
...
llvm-svn: 30583
2006-09-22 21:43:59 +00:00
4259a0f654
X86ISD::CMP now produces a chain as well as a flag. Make that the chain
...
operand of a conditional branch to allow load folding into CMP / TEST
instructions.
llvm-svn: 30241
2006-09-11 02:19:56 +00:00
11b0a5dbd4
Committing X86-64 support.
...
llvm-svn: 30177
2006-09-08 06:48:29 +00:00
dc4ff5311f
Eliminate X86ISD::TEST, using X86ISD::CMP instead. Match X86ISD::CMP patterns
...
using test, which provides nice simplifications like:
- movl %edi, %ecx
- andl $2, %ecx
- cmpl $0, %ecx
+ testl $2, %edi
je LBB1_11 #cond_next90
There are a couple of dagiselemitter deficiencies that this exposes, they will
be handled later.
llvm-svn: 30156
2006-09-07 20:33:45 +00:00
a9411c0977
Consistency.
...
llvm-svn: 30152
2006-09-07 19:03:48 +00:00
81b645a76b
CALLSEQ_* produces chain even if that's not needed.
...
llvm-svn: 29603
2006-08-11 09:03:33 +00:00
683b966485
Clean up.
...
llvm-svn: 29228
2006-07-20 21:37:39 +00:00
02d8836cd5
INC / DEC instructions have shorter code size than ADD32ri8, etc.
...
llvm-svn: 29194
2006-07-19 00:27:29 +00:00
d5a086ab12
Emit inc / dec of registers as one byte instruction.
...
llvm-svn: 29110
2006-07-11 19:49:49 +00:00
fa9e60895b
Add shift and rotate by 1 instructions / patterns.
...
llvm-svn: 28980
2006-06-29 00:36:51 +00:00
2aed9ebded
Remove dead code.
...
llvm-svn: 28938
2006-06-27 20:34:14 +00:00
c8734381ac
X86 call instructions can take variable number of operands. Parameters of
...
vector types are passed via XMM registers.
llvm-svn: 28789
2006-06-14 22:24:55 +00:00
7ae8632cb4
Incorrect AT&T opcode.
...
llvm-svn: 28666
2006-06-02 21:09:10 +00:00
cfaffdd335
Rename ASM modifier trunc8, trunc16 to subreg8, subreg16.
...
llvm-svn: 28606
2006-05-31 22:34:26 +00:00
cf70c7f42d
Sign extender
...
llvm-svn: 28603
2006-05-31 22:05:11 +00:00
734e1e241b
A addressing mode folding enhancement:
...
Fold c2 in (x << c1) | c2 where (c2 < c1)
e.g.
int test(int x) {
return (x << 3) + 7;
}
This can be codegen'd as:
leal 7(,%eax,8), %eax
llvm-svn: 28550
2006-05-30 06:59:36 +00:00
b9ac06bb33
Remove unused patterns.
...
llvm-svn: 28417
2006-05-20 01:40:16 +00:00
7b8feb27c8
- Use exact-width integer types, e.g. int32_t, to avoid confusion.
...
- Fix a couple of minor bugs in i16immSExt8 and i16immZExt8.
- Added loadiPTR fragment used for indirect jumps and calls.
llvm-svn: 28392
2006-05-19 18:40:54 +00:00
1c8ef9832f
Explicitly specify MOV32mi can only be used store 32-bit GV, etc.
...
llvm-svn: 28390
2006-05-19 07:30:36 +00:00
e59042d004
Use generic iPTR instead i32 to represent pointer type.
...
llvm-svn: 28371
2006-05-17 21:21:41 +00:00
9fee442e63
X86 integer register classes naming changes. Make them consistent with FP, vector classes.
...
llvm-svn: 28324
2006-05-16 07:21:53 +00:00
9733bde74c
Fixing truncate. Previously we were emitting truncate from r16 to r8 as
...
movw. That is we promote the destination operand to r16. So
%CH = TRUNC_R16_R8 %BP
is emitted as
movw %bp, %cx.
This is incorrect. If %cl is live, it would be clobbered.
Ideally we want to do the opposite, that is emitted it as
movb ??, %ch
But this is not possible since %bp does not have a r8 sub-register.
We are now defining a new register class R16_ which is a subclass of R16
containing only those 16-bit registers that have r8 sub-registers (i.e.
AX - DX). We isel the truncate to two instructions, a MOV16to16_ to copy the
value to the R16_ class, followed by a TRUNC_R16_R8.
Due to bug 770, the register colaescer is not going to coalesce between R16 and
R16_. That will be fixed later so we can eliminate the MOV16to16_. Right now, it
can only be eliminated if we are lucky that source and destination registers are
the same.
llvm-svn: 28164
2006-05-08 08:01:26 +00:00
52c22512b9
Need extload patterns after Chris' DAG combiner changes
...
llvm-svn: 28127
2006-05-05 08:23:07 +00:00
ddb6cc1d8e
Better implementation of truncate. ISel matches it to a pseudo instruction
...
that gets emitted as movl (for r32 to i16, i8) or a movw (for r16 to i8). And
if the destination gets allocated a subregister of the source operand, then
the instruction will not be emitted at all.
llvm-svn: 28119
2006-05-05 05:40:20 +00:00
f4f3f0d25f
Make x86 isel lowering produce tailcall nodes. They are match to normal calls
...
for now.
Patch contributed by Alexander Friedman.
llvm-svn: 27994
2006-04-27 08:40:39 +00:00
9f0b13c885
Optimized stores to the constant pool, while cool, are unnecessary.
...
llvm-svn: 27948
2006-04-22 22:31:45 +00:00
4ca2ea5b43
JumpTable support! What this represents is working asm and jit support for
...
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.
llvm-svn: 27947
2006-04-22 18:53:45 +00:00
ebf1006d16
- More efficient extract_vector_elt with shuffle and movss, movsd, movd, etc.
...
- Some bug fixes and naming inconsistency fixes.
llvm-svn: 27377
2006-04-03 20:53:28 +00:00
3e4d38eea5
Added missing (any_extend (load ...)) patterns.
...
llvm-svn: 27120
2006-03-25 09:45:48 +00:00
ce0206e119
Fix the encodings of these new instructions, hopefully fixing the JIT
...
failures from last night
llvm-svn: 26981
2006-03-23 16:13:50 +00:00
fb6e02931c
Add support for 8 bit immediates with 16/32 bit cmp instructions
...
llvm-svn: 26966
2006-03-23 01:29:48 +00:00
9bf978dc20
Use the generic vector register classes VR64 / VR128 rather than V4F32,
...
V8I16, etc.
llvm-svn: 26838
2006-03-18 01:23:20 +00:00
4f674921d6
Move some pattern fragments to the right files.
...
llvm-svn: 26831
2006-03-17 19:55:52 +00:00
27750f3287
- Nuke 16-bit SBB instructions. We'll never use them.
...
- Nuke a bogus comment.
llvm-svn: 26815
2006-03-17 02:24:04 +00:00
70b25efa57
X86ISD::REP_STOS and X86ISD::REP_MOVS now produces a flag.
...
llvm-svn: 26604
2006-03-07 23:34:23 +00:00
30d7b70b73
Enable Dwarf debugging info.
...
llvm-svn: 26581
2006-03-07 02:02:57 +00:00
ad3c974a77
remove the read/write port/io intrinsics.
...
llvm-svn: 26479
2006-03-03 00:19:58 +00:00
1fac3b3360
* Allow mul, shl nodes to be codegen'd as LEA (if appropriate).
...
* Add patterns to handle GlobalAddress, ConstantPool, etc.
MOV32ri to materialize these nodes in registers.
ADD32ri to handle %reg + GA, etc.
MOV32mi to handle store GA, etc. to memory.
llvm-svn: 26374
2006-02-25 10:02:21 +00:00
e0ed6ec13f
- Clean up the lowering and selection code of ConstantPool, GlobalAddress,
...
and ExternalSymbol.
- Use C++ code (rather than tblgen'd selection code) to match the above
mentioned leaf nodes. Do not mutate and nodes and do not record the
selection in CodeGenMap. These nodes should be safe to duplicate. This is
a performance win.
llvm-svn: 26335
2006-02-23 20:41:18 +00:00
1f342c2884
PIC related bug fixes.
...
1. Various asm printer bug.
2. Lowering bug. Now TargetGlobalAddress is wrapped in X86ISD::TGAWrapper.
llvm-svn: 26324
2006-02-23 02:43:52 +00:00
9e252e3bcf
Added MMX, SSE1, and SSE2 vector instructions and some simple patterns.
...
Fixed some existing bugs (wrong predicates, prefixes) at the same time.
llvm-svn: 26310
2006-02-22 02:26:30 +00:00
d58478161f
One more round of reorg so sabre doesn't freak out. :-)
...
llvm-svn: 26303
2006-02-21 20:00:20 +00:00
6fc1162855
A big more cleaning up.
...
llvm-svn: 26302
2006-02-21 19:30:30 +00:00
8711b6bff3
Moving things to their proper places.
...
llvm-svn: 26301
2006-02-21 19:26:52 +00:00
6e595b9fd8
Split instruction info into multiple files, one for each of x87, MMX, and SSE.
...
llvm-svn: 26300
2006-02-21 19:13:53 +00:00
d57203c0a1
Added separate alias instructions for SSE logical ops that operate on non-packed types.
...
llvm-svn: 26297
2006-02-21 02:24:38 +00:00
afffe63fc1
Added MMX and XMM packed integer move instructions, movd and movq.
...
llvm-svn: 26296
2006-02-21 01:39:57 +00:00
43070b7541
Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit
...
packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).
llvm-svn: 26294
2006-02-20 22:34:53 +00:00
70af620709
Added fisttp for fp to int conversion.
...
llvm-svn: 26283
2006-02-18 02:36:28 +00:00
5588de9415
x86 / Darwin PIC support.
...
llvm-svn: 26273
2006-02-18 00:15:05 +00:00
5965bd19f8
kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
...
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
llvm-svn: 26255
2006-02-17 05:43:56 +00:00
eb7b3380fd
pxor (for FLD0SS) encoding was missing the OpSize prefix.
...
llvm-svn: 26244
2006-02-16 23:59:30 +00:00
24c461b51e
1. Use pxor instead of xoraps / xorapd to clear FR32 / FR64 registers. This
...
proves to be worth 20% on Ptrdist/ks. Might be related to dependency
breaking support.
2. Added FsMOVAPSrr and FsMOVAPDrr as aliases to MOVAPSrr and MOVAPDrr. These
are used for FR32 / FR64 reg-to-reg copies.
3. Tell reg-allocator to generate MOVSSrm / MOVSDrm and MOVSSmr / MOVSDmr to
spill / restore FsMOVAPSrr and FsMOVAPDrr.
llvm-svn: 26241
2006-02-16 22:45:17 +00:00
01afec2adb
MOVAPSrr and MOVAPDrr instruction format should be MRMSrcReg.
...
llvm-svn: 26234
2006-02-16 19:34:41 +00:00
aacc4c3b4c
cvtsd2ss / cvtss2sd encoding bug.
...
llvm-svn: 26193
2006-02-15 00:31:03 +00:00
665c26ab40
movaps, movapd encoding bug.
...
llvm-svn: 26192
2006-02-15 00:11:37 +00:00
d62a3bfa66
Eliminate the printCallOperand method, using a 'call' modifier on
...
printOperand instead.
llvm-svn: 26025
2006-02-06 23:41:19 +00:00
0a977c95aa
Remove an unnecessary predicate.
...
llvm-svn: 25954
2006-02-04 02:23:01 +00:00
11613a5219
Separate FILD and FILD_FLAG, the later is only used for SSE2. It produces a
...
flag so it can be flagged to a FST.
llvm-svn: 25953
2006-02-04 02:20:30 +00:00
8b40cde148
Rearrange code to my liking. :)
...
llvm-svn: 25887
2006-02-01 23:01:57 +00:00
9e350cd6ad
- Use xor to clear integer registers (set R, 0).
...
- Added a new format for instructions where the source register is implied
and it is same as the destination register. Used for pseudo instructions
that clear the destination register.
llvm-svn: 25872
2006-02-01 06:13:50 +00:00
72d5c256c9
- Allow XMM load (for scalar use) to be folded into ANDP* and XORP*.
...
- Use XORP* to implement fneg.
llvm-svn: 25857
2006-01-31 22:28:30 +00:00
c642aa5e1c
* Fix 80-column violations
...
* Rename hasSSE -> hasSSE1 to avoid my continual confusion with 'has any SSE'.
* Add inline asm constraint specification.
llvm-svn: 25854
2006-01-31 19:43:35 +00:00
2dd217b88f
Added custom lowering of fabs
...
llvm-svn: 25831
2006-01-31 03:14:29 +00:00
5b97fcf0f5
Always use FP stack instructions to perform i64 to f64 as well as f64 to i64
...
conversions. SSE does not have instructions to handle these tasks.
llvm-svn: 25817
2006-01-30 08:02:57 +00:00
132177e103
The FP stack doesn't support UNDEF, ask the legalizer to legalize it
...
instead of lying and saying we have it.
llvm-svn: 25775
2006-01-29 06:44:22 +00:00
63045d221b
AT&T assembly convention: registers are in lower case.
...
llvm-svn: 25714
2006-01-27 22:53:29 +00:00
cde9e30bc6
x86 CPU detection and proper subtarget support
...
llvm-svn: 25679
2006-01-27 08:10:46 +00:00
1240574609
PHI and INLINEASM are now built-in instructions provided by Target.td
...
llvm-svn: 25674
2006-01-27 01:46:15 +00:00
97c68f0f5c
Remove the uses of STATUS flag register. Rely on node property SDNPInFlag,
...
SDNPOutFlag, and SDNPOptInFlag instead.
llvm-svn: 25629
2006-01-26 00:29:36 +00:00
6f33eaeb81
Emit the copies out of call return registers *after* the ISD::CALLSEQ_END
...
node, fixing fastcc and the case where a function has a frame pointer due
to dynamic allocas.
llvm-svn: 25580
2006-01-24 05:17:12 +00:00
468fecdc99
Rename fcmovae to fcmovnb and fcmova to fcmovnbe (following Intel manual).
...
Some assemblers can't recognize the aliases.
llvm-svn: 25494
2006-01-21 02:55:41 +00:00
cce748d316
A few more SH{L|R}D peepholes.
...
llvm-svn: 25473
2006-01-20 01:13:30 +00:00
8591b9f254
Added i16 SH{L|R}D patterns.
...
llvm-svn: 25468
2006-01-19 23:26:24 +00:00
91007126c2
adc and sbb need an incoming flag to ensure it reads the carry flag
...
from add / sub.
llvm-svn: 25444
2006-01-19 06:53:20 +00:00
a7bfbe996e
Two peepholes:
...
(or (x >> c) | (y << (32 - c))) ==> (shrd x, y, c)
(or (x << c) | (y >> (32 - c))) ==> (shld x, y, c)
llvm-svn: 25438
2006-01-19 01:56:29 +00:00
14417ed99c
Zero extending load from i1 to i8.
...
llvm-svn: 25391
2006-01-17 07:02:46 +00:00
bec9d720b0
Bug fixes: fpGETRESULT should produces a flag result and X86ISD::FST should
...
read a flag.
llvm-svn: 25378
2006-01-17 00:19:47 +00:00
c14bb1026b
More typo's
...
llvm-svn: 25375
2006-01-16 23:26:53 +00:00
64eeed27d9
Some typo's
...
llvm-svn: 25374
2006-01-16 22:48:46 +00:00
911c68d7a8
Fix FP_TO_INT**_IN_MEM lowering.
...
llvm-svn: 25368
2006-01-16 21:21:29 +00:00
2494ce49f0
Added patterns for 8-bit multiply
...
llvm-svn: 25338
2006-01-15 10:05:20 +00:00
2fba8a3aaa
bswap implementation
...
llvm-svn: 25312
2006-01-14 03:14:10 +00:00
3bc25e8a54
A typo.
...
llvm-svn: 25307
2006-01-14 01:18:49 +00:00
392c7d2779
Add truncstore i1 patterns.
...
llvm-svn: 25296
2006-01-13 21:45:19 +00:00
6305e50ee1
Fix sint_to_fp (fild*) support.
...
llvm-svn: 25257
2006-01-12 22:54:21 +00:00
c993d4522d
Specify transformation from GlobalAddress to TargetGlobalAddress and
...
ExternalSymbol to TargetExternalSymbol.
llvm-svn: 25253
2006-01-12 19:36:31 +00:00
84dc9b55f0
X86ISD::SETCC (e.g. SETEr) produces a flag (so multiple SETCC can be
...
linked together).
llvm-svn: 25247
2006-01-12 08:27:59 +00:00
b94db9e9a4
* Materialize GlobalAddress and ExternalSym with MOV32ri rather than
...
LEA32r.
* Do not lower GlobalAddress to TargetGlobalAddress. Let isel does it.
llvm-svn: 25246
2006-01-12 07:56:47 +00:00
6d2ab04463
Added ROTL and ROTR.
...
llvm-svn: 25232
2006-01-11 23:20:05 +00:00
ae986f1f1e
Support for MEMCPY and MEMSET.
...
llvm-svn: 25226
2006-01-11 22:15:48 +00:00
bc7a0f44bd
* Add special entry code main() (to set x87 to 64-bit precision).
...
* Allow a register node as SelectAddr() base.
* ExternalSymbol -> TargetExternalSymbol as direct function callee.
* Use X86::ESP register rather than CopyFromReg(X86::ESP) as stack ptr for
call parmater passing.
llvm-svn: 25207
2006-01-11 06:09:51 +00:00
339edad775
SSE cmov support.
...
llvm-svn: 25190
2006-01-11 00:33:36 +00:00
efaf5c56fd
* fp to sint patterns.
...
* fiadd, fisub, etc.
llvm-svn: 25189
2006-01-10 22:22:02 +00:00
73a1ad975e
FP_TO_INT*_IN_MEM and x87 FP Select support.
...
llvm-svn: 25188
2006-01-10 20:26:56 +00:00
7c4486215f
* Added undef patterns.
...
* Some reorg.
llvm-svn: 25163
2006-01-09 23:10:28 +00:00
9c249c37f8
Support for ADD_PARTS, SUB_PARTS, SHL_PARTS, SHR_PARTS, and SRA_PARTS.
...
llvm-svn: 25158
2006-01-09 18:33:28 +00:00
53dd0ac226
Addd (shl x, 1) ==> (shl x, x) peepholes.
...
llvm-svn: 25123
2006-01-06 02:31:59 +00:00
172fce7050
* Fast call support.
...
* FP cmp, setcc, etc.
llvm-svn: 25117
2006-01-06 00:43:03 +00:00
a5ae6e8320
Added ConstantFP patterns.
...
llvm-svn: 25108
2006-01-05 02:08:37 +00:00
45e19098a6
DAG based isel call support.
...
llvm-svn: 25103
2006-01-05 00:27:02 +00:00
14c53b45f5
Added field noResults to Instruction.
...
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.
llvm-svn: 25017
2005-12-26 09:11:45 +00:00
9ae486047e
* Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead.
...
* Added a pseudo instruction (for each target) that represent "return void".
This is a workaround for lack of optional flag operand (return void is not
lowered so it does not have a flag operand.)
llvm-svn: 24997
2005-12-23 22:14:32 +00:00
5c59d49630
More X86 floating point patterns.
...
llvm-svn: 24990
2005-12-23 07:31:11 +00:00
dfad8ed54e
Bye bye HACKTROCITY.
...
llvm-svn: 24935
2005-12-22 02:26:21 +00:00
9cdc16c6d3
* Fix a GlobalAddress lowering bug.
...
* Teach DAG combiner about X86ISD::SETCC by adding a TargetLowering hook.
llvm-svn: 24921
2005-12-21 23:05:39 +00:00
02767195bb
Oops. Accidentally deleted RET pattern. It's still needed for return void;
...
llvm-svn: 24920
2005-12-21 22:22:16 +00:00
c1583dbd63
* Added support for X86 RET with an additional operand to specify number of
...
bytes to pop off stack.
* Added support for X86 SETCC.
llvm-svn: 24917
2005-12-21 20:21:51 +00:00
0dcdd83c0e
This was meant to go in
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llvm-svn: 24900
2005-12-21 07:50:26 +00:00
f431ad4477
Rewrite FP stackifier support in the X86InstrInfo.td file, splitting patterns
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that were overloaded to work before and after the stackifier runs. With the
new clean world, it is possible to write patterns for these instructions: woo!
This also adds a few simple patterns here and there, though there are a lot
still missing. These should be easy to add though. :)
See the comments under "Floating Point Stack Support" for more details on
the new world order.
This patch as absolutely no effect on the generated code, woo!
llvm-svn: 24899
2005-12-21 07:47:04 +00:00
988827a482
Wrap some long lines: no functionality change
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llvm-svn: 24898
2005-12-21 05:34:58 +00:00
a74ce62746
* Added lowering hook for external weak global address. It inserts a load
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for Darwin.
* Added lowering hook for ISD::RET. It inserts CopyToRegs for the return
value (or store / fld / copy to ST(0) for floating point value). This
eliminate the need to write C++ code to handle RET with variable number
of operands.
llvm-svn: 24888
2005-12-21 02:39:21 +00:00
5c0b4df483
SSE2 floating point load / store patterns. SSE2 fp to int conversion patterns.
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llvm-svn: 24886
2005-12-20 22:59:51 +00:00
5815a6e455
Added X86 readport patterns.
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llvm-svn: 24879
2005-12-20 07:38:38 +00:00
6fc31046aa
X86 conditional branch support.
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llvm-svn: 24870
2005-12-19 23:12:38 +00:00
db8e888fb5
eliminate some redundancy
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llvm-svn: 24781
2005-12-17 19:47:05 +00:00
b06925d1dd
Added anyext, modelled as zext on X86.
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llvm-svn: 24759
2005-12-17 01:47:57 +00:00
cb19390ead
Added support for cmp, test, and conditional move instructions.
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llvm-svn: 24756
2005-12-17 01:24:02 +00:00
74151ba279
* Promote all 1 bit entities to 8 bit.
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* Handling extload (1 bit -> 8 bit) and remove C++ code that handle 1 bit
zextload.
llvm-svn: 24726
2005-12-15 19:49:23 +00:00
305c6a73b5
Added frameindex, constpool, globaladdr, and externalsym as root nodes of
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leaaddr.
llvm-svn: 24724
2005-12-15 08:31:04 +00:00
bc9344477e
Use MOV8rm to load 1 bit value.
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llvm-svn: 24721
2005-12-15 00:59:17 +00:00
c273900dd8
Added sext and zext patterns.
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llvm-svn: 24705
2005-12-14 02:22:27 +00:00
229f0ee6d7
Add load + store folding srl and sra patterns.
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llvm-svn: 24696
2005-12-13 07:24:22 +00:00
acec857b1a
Beautify a few patterns.
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llvm-svn: 24690
2005-12-13 02:40:18 +00:00
89c6db4baf
Some shl patterns which do load + store folding.
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llvm-svn: 24689
2005-12-13 02:34:51 +00:00
108beceb0f
A few helper fragments for loads. e.g. (i8 (load addr:$src)) -> (loadi8 addr:$src). Only to improve readibility.
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llvm-svn: 24688
2005-12-13 01:57:51 +00:00
ddd5ae5a22
Add and, or, and xor patterns which fold load + stores.
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llvm-svn: 24687
2005-12-13 01:41:36 +00:00
e5a94a03e2
Add inc + dec patterns which fold load + stores.
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llvm-svn: 24686
2005-12-13 01:02:47 +00:00
bde9e6fca6
Add neg and not patterns which fold load + stores.
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llvm-svn: 24685
2005-12-13 00:54:44 +00:00
c414d563f0
Missed a couple redundant explicit type casts.
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llvm-svn: 24684
2005-12-13 00:25:07 +00:00
62e6808aa5
Fix some bad choice of names: i16SExt8 ->i16immSExt8, etc.
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llvm-svn: 24683
2005-12-13 00:14:11 +00:00
86b2cf22d2
* Split immSExt8 to i16SExt8 and i32SExt8 for i16 and i32 immediate operands.
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This enables the removal of some explicit type casts.
* Rename immZExt8 to i16ZExt8 as well.
llvm-svn: 24682
2005-12-13 00:01:09 +00:00
3e52756928
Add some integer mul patterns.
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llvm-svn: 24681
2005-12-12 23:47:46 +00:00
Lauro Ramos Venancio