7a4e1ba737
[X86] Fix bug in COMISD and COMISS definition in td files
...
COMISD should receive QWORD because it is defined as
(V)COMISD xmm1, xmm2/m64
COMISS should receive DWORD because it is defined as
(V)COMISS xmm1, xmm2/m32
Differential Revision: http://reviews.llvm.org/D11712
llvm-svn: 245551
2015-08-20 11:21:36 +00:00
66233b7d79
Removing tailing whitespaces
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llvm-svn: 244203
2015-08-06 09:06:20 +00:00
8352a0ddf2
AVX512: Implemented encoding and intrinsics for VGETEXPSS/D instructions
...
Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D11528
llvm-svn: 243390
2015-07-28 06:53:28 +00:00
f2460112ad
Implemented encoding and intrinsics of the following instructions
...
vunpckhps/pd, vunpcklps/pd,
vpunpcklbw, vpunpckhbw, vpunpcklwd, vpunpckhwd, vpunpckldq, vpunpckhdq, vpunpcklqdq, vpunpckhqdq
Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D11509
llvm-svn: 243246
2015-07-26 14:41:44 +00:00
074a64e72c
AVX-512: Implemented encoding , DAG lowering and intrinsics for Integer Truncate with/without saturation
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Added tests for DAG lowering ,encoding and intrinsic
Differential Revision: http://reviews.llvm.org/D11218
llvm-svn: 243122
2015-07-24 17:24:15 +00:00
fe414353db
Revert r242990: "AVX-512: Implemented encoding , DAG lowering and ..."
...
This commit broke the build. Numerous build bots broken, and it was
blocking my progress so reverting.
It should be trivial to reproduce -- enable the BPF backend and it
should fail when running llvm-tblgen.
llvm-svn: 242992
2015-07-23 08:03:44 +00:00
da1b2ea955
AVX-512: Implemented encoding , DAG lowering and intrinsics for Integer Truncate with/without saturation
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Added tests for DAG lowering ,encoding and intrinsic
Differential Revision: http://reviews.llvm.org/D11218
llvm-svn: 242990
2015-07-23 07:39:21 +00:00
a5b2e5e2a7
[X86][AVX512] add reduce/range/scalef/rndScale
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include encoding and intrinsics
Differential Revision: http://reviews.llvm.org/D11222
llvm-svn: 242896
2015-07-22 12:00:43 +00:00
f7fd547e27
AVX512 : Implemented VPMADDUBSW and VPMADDWD instruction ,
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Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D11351
llvm-svn: 242761
2015-07-21 07:11:28 +00:00
0f370936a0
AVX-512: Added all AVX-512 forms of Vector Convert for Float/Double/Int/Long types.
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In this patch I have only encoding. Intrinsics and DAG lowering will be in the next patch.
I temporary removed the old intrinsics test (just to split this patch).
Half types are not covered here.
Differential Revision: http://reviews.llvm.org/D11134
llvm-svn: 242023
2015-07-13 13:26:20 +00:00
8b756596fc
[X86][SSE] Use the general SMAX/SMIN/UMAX/UMIN opcodes and remove the X86 implementation
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With the completion of D9746 there is now a common implementation of integer signed/unsigned min/max nodes, removing the need for the equivalent X86 specific implementations.
This patch removes the old X86ISD nodes, legalizes the relevant SSE2/SSE41/AVX2/AVX512 instructions for the ISD versions and converts the small amount of existing X86 code.
Differential Revision: http://reviews.llvm.org/D10947
llvm-svn: 241506
2015-07-06 20:30:47 +00:00
c6f3c82ffc
[X86][AVX512] Multiply Packed Unsigned Integers with Round and Scale
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pmulhrsw
review:
http://reviews.llvm.org/D10948
llvm-svn: 241443
2015-07-06 14:03:40 +00:00
73f26f8ffc
[x86][AVX512] add Multiply High Op
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include encoding and intrinsics tests.
review
http://reviews.llvm.org/D10896
llvm-svn: 241406
2015-07-05 12:23:20 +00:00
15820b072b
AVX-512: Implemented missing encoding for FMA scalar instructions
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Added tests for encoding
Differential Revision: http://reviews.llvm.org/D10865
llvm-svn: 241159
2015-07-01 13:24:28 +00:00
30bc4ca313
AVX-512: all forms of SCATTER instruction on SKX,
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encoding, intrinsics and tests.
llvm-svn: 240936
2015-06-29 12:14:24 +00:00
a7a8e9a018
AVX-512: Implemented missing encoding and intrinsics for FMA instructions
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Added tests for DAG lowering ,encoding and intrinsics
Differential Revision: http://reviews.llvm.org/D10796
llvm-svn: 240926
2015-06-29 09:10:00 +00:00
7ec4b7a8bb
[x86][AVX512]
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Add vscalef support
include encoding and intrinsics
review:
http://reviews.llvm.org/D10730
llvm-svn: 240906
2015-06-28 14:30:39 +00:00
6a1a357f1f
AVX-512: Added all SKX forms of GATHER instructions.
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Added intrinsics.
Added encoding and tests.
llvm-svn: 240905
2015-06-28 10:53:29 +00:00
5e2f8c4231
AVX-512: Added all forms of VPABS instruction
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Added all intrinsics, tests for encoding, tests for intrinsics.
llvm-svn: 240386
2015-06-23 08:19:46 +00:00
55a997437c
AVX-512: added VPSHUFB instruction - all SKX forms
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Added intrinsics and encoding tests.
llvm-svn: 240277
2015-06-22 13:00:42 +00:00
ba5ab328e5
AVX-512: All forms of VCOPMRESS VEXPAND instructions,
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encoding tests.
llvm-svn: 240272
2015-06-22 11:16:30 +00:00
81f03c30a5
[AVX512]
...
add instructions: VPAVGB and VPAVGW
review
http://reviews.llvm.org/D10504
llvm-svn: 240012
2015-06-18 12:30:53 +00:00
d3057e5e37
AVX-512: (fixed) Added encoding of all forms of VPERMT2W/D/Q/PS/PD and VPERMI2W/D/Q/PS/PD.
...
Intrinsics and tests for them are comming in the next patch.
llvm-svn: 240003
2015-06-18 08:56:19 +00:00
4f13f3f9b8
reverted 239999 due to test failures
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llvm-svn: 240001
2015-06-18 08:06:49 +00:00
975a637cd9
AVX-512: Added encoding of all forms of VPERMT2W/D/Q/PS/PD
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and VPERMI2W/D/Q/PS/PD.
Intrinsics and tests for them are comming in the next patch.
llvm-svn: 239999
2015-06-18 07:29:40 +00:00
dfcc3d31a7
AVX-512: cvtusi2ss/d intrinsics.
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Change builtin function name and signature ( add third parameter - rounding mode ).
Added tests for intrinsics.
Differential Revision: http://reviews.llvm.org/D10473
llvm-svn: 239888
2015-06-17 07:23:57 +00:00
02d126cb9d
[AVX512] add integer min/max intrinsics support.
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review:
http://reviews.llvm.org/D10439
llvm-svn: 239806
2015-06-16 08:39:27 +00:00
abe4a79b75
AVX-512: Implemented cvtsi2ss/d cvtusi2ss/d instructions with round control for KNL.
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Added intrinsics for cvtsi2ss/d instructions.
Added tests for intrinsics and encoding.
Differential Revision: http://reviews.llvm.org/D10430
llvm-svn: 239694
2015-06-14 12:44:55 +00:00
00c9ad5ec2
AVX-512: Fixed a bug in comparison of i1 vectors.
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cmp eq should give kxnor instruction
cmp neq should give kxor
https://llvm.org/bugs/show_bug.cgi?id=23631
llvm-svn: 239460
2015-06-10 06:49:28 +00:00
00d9f8457b
AVX-512: Implemented 256/128bit VALIGND/Q instructions for SKX and KNL
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Implemented DAG lowering for all these forms.
Added tests for DAG lowering and encoding.
Differential Revision: http://reviews.llvm.org/D10310
llvm-svn: 239300
2015-06-08 14:03:17 +00:00
4078c75bd4
AVX-512: added all SKX forms of VPERMW/D/Q instructions.
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Added all forms of VPERMPS/PD instrcuctions.
Added encoding tests.
llvm-svn: 239016
2015-06-04 07:07:13 +00:00
402ebb34af
re-apply 238809
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AVX-512: Implemented GETEXP instruction for KNL and SKX
Added rounding mode modifier for SQRTPS/PD
Added tests for encoding and intrinsics.
CR:
http://reviews.llvm.org/D9991
llvm-svn: 238923
2015-06-03 13:41:48 +00:00
9e38086534
AVX-512: Implemented SHUFF32x4/SHUFF64x2/SHUFI32x4/SHUFI64x2 instructions for SKX and KNL.
...
Added tests for encoding.
By Igor Breger (igor.breger@intel.com )
llvm-svn: 238917
2015-06-03 10:56:40 +00:00
8938f5acca
AVX-512: Implemented VRANGESD and VRANGESS instructions for SKX Implemented DAG lowering for all these forms.
...
Added tests for encoding.
By Igor Breger (igor.breger@intel.com )
llvm-svn: 238834
2015-06-02 14:12:54 +00:00
3425c932da
AVX-512: Implemented VFIXUPIMMSD and VFIXUPIMMSS instructions for KNL
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Implemented DAG lowering for all these forms.
Added tests for encoding.
By Igor Breger (igor.breger@intel.com )
llvm-svn: 238811
2015-06-02 08:28:57 +00:00
8d897dd05f
revert 238809
...
llvm-svn: 238810
2015-06-02 07:45:19 +00:00
17de10f37e
AVX-512: Implemented GETEXP instruction for KNL and SKX
...
Added rounding mode modifier for SQRTPS/PD
Added tests for encoding and intrinsics.
llvm-svn: 238809
2015-06-02 07:18:14 +00:00
3582eb3b39
AVX-512: Implemented VRANGEPD and VRANGEPD instructions for SKX.
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Implemented DAG lowering for all these forms.
Added tests for encoding.
By Igor Breger (igor.breger@intel.com )
llvm-svn: 238738
2015-06-01 11:05:34 +00:00
75ede68793
AVX-512: added all forms of VPSHUFD and VPSHUFHW, VPSHUFLW
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including encodings.
llvm-svn: 238729
2015-06-01 07:17:23 +00:00
42c96d9c0a
AVX-512: Implemented VFIXUPIMMPD and VFIXUPIMMPS instructions for KNL and SKX
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Implemented DAG lowering for all these forms.
Added tests for encoding.
by Igor Breger (igor.breger@intel.com )
llvm-svn: 238728
2015-06-01 06:50:49 +00:00
86c7b46680
AVX-512: Fixed a bug in extracting subvector from v64i1
...
By Igor Breger (igor.breger@intel.com )
llvm-svn: 238322
2015-05-27 14:09:33 +00:00
3948c590e3
AVX-512: Implemented all forms of sign-extend and zero-extend instructions for KNL and SKX
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Implemented DAG lowering for all these forms.
Added tests for DAG lowering and encoding.
By Igor Breger (igor.breger@intel.com )
llvm-svn: 238301
2015-05-27 08:15:19 +00:00
f61727d880
AVX-512: fixed algorithm of building vectors of i1 elements
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fixed extract-insert i1 element,
load i1, zextload i1 should be with "and $1, %reg" to prevent loading garbage.
added a bunch of new tests.
llvm-svn: 237793
2015-05-20 14:32:03 +00:00
08ce53c0ea
AVX-512: Added patterns for scalar-to-vector broadcast
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llvm-svn: 237558
2015-05-18 07:06:23 +00:00
ad9c396838
AVX-512: Added VBROADCASTF64X4, VBROADCASTF64X2, VBROADCASTI32X8, and other instructions from this set
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Added encoding tests.
llvm-svn: 237557
2015-05-18 06:42:57 +00:00
1d6a495d6d
AVX-512: fixed a bug in mask operations - (i1 1) pattern
...
Filling k-reg with all-ones value was wrong,
(i1 1) should switch on only one bit in mask register
llvm-svn: 237536
2015-05-17 07:28:51 +00:00
1b2f2f1b37
AVX-512: fixed a bug in encoding of VPSRAQ instrcution,
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added a bunch of encoding tests.
llvm-svn: 237232
2015-05-13 07:35:05 +00:00
0d7e9364d1
AVX-512: Added SKX instructions and intrinsics:
...
{add/sub/mul/div/} x {ps/pd} x {128/256} 2. max/min with sae
By Asaf Badouh (asaf.badouh@intel.com )
llvm-svn: 236971
2015-05-11 06:05:05 +00:00
75d1489326
AVX-512: fixed a bug in i1 vectors lowering
...
llvm-svn: 236947
2015-05-10 10:33:32 +00:00
29792e9a80
AVX-512: Added all forms of FP compare instructions for KNL and SKX.
...
Added intrinsics for the instructions. CC parameter of the intrinsics was changed from i8 to i32 according to the spec.
By Igor Breger (igor.breger@intel.com )
llvm-svn: 236714
2015-05-07 11:24:42 +00:00
60eb9db7bb
AVX-512: added calling convention for i1 vectors in 32-bit mode.
...
Fixed some bugs in extend/truncate for AVX-512 target.
Removed VBROADCASTM (masked broadcast) node, since it is not used any more.
llvm-svn: 236420
2015-05-04 12:40:50 +00:00
52266388f8
AVX-512: added integer "add" and "sub" instructions with saturation for SKX
...
with intrinsics and tests
by Asaf Badouh (asaf.badouh@intel.com )
llvm-svn: 236418
2015-05-04 12:35:55 +00:00
2557a22be7
AVX-512: Added VPACK* instructions forms for KNL and SKX
...
and their intrinsics
by Asaf Badouh (asaf.badouh@intel.com )
llvm-svn: 236414
2015-05-04 09:14:02 +00:00
e1eda8a9e6
Masked gather and scatter - added DAGCombine visitors
...
and AVX-512 instruction selection patterns.
All other patches, including tests will follow.
http://reviews.llvm.org/D7665
llvm-svn: 236211
2015-04-30 08:38:48 +00:00
d1084c5b3f
AVX-512: Extend/Truncate operations for SKX,
...
SETCC for bit-vectors
llvm-svn: 235875
2015-04-27 12:57:59 +00:00
0e6d6d54ce
AVX-512: Added VPMOVx2M instructions for SKX,
...
fixed encoding of VPMOVM2x.
llvm-svn: 235385
2015-04-21 14:38:31 +00:00
431b81e41f
AVX-512: Added VPTESTM and VPTESTNM instructions for SKX
...
llvm-svn: 235383
2015-04-21 13:13:46 +00:00
50b88ddb87
AVX-512: Added logical and arithmetic instructions for SKX
...
by Asaf Badouh (asaf.badouh@intel.com )
llvm-svn: 235375
2015-04-21 10:27:40 +00:00
1eeece1285
AVX-512: intrinsics for VPADD, VPMULDQ and VPSUB
...
by Asaf Badouh (asaf.badouh@intel.com )
llvm-svn: 233906
2015-04-02 10:51:40 +00:00
d8fda62247
AVX-512: blank lines, duplicated tests, no functional changes
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see comments http://reviews.llvm.org/D6835
llvm-svn: 233528
2015-03-30 09:29:28 +00:00
72e3ccc375
AVX-512: Fixed the "commutative" property flag in VPANDN instruction
...
By Asaf Badouh (asaf.badouh@intel.com )
llvm-svn: 233489
2015-03-29 09:14:29 +00:00
5d06b4c80c
AVX-512: Added encoding tests for VPROR, VPROL instructions,
...
fixed opcode.
llvm-svn: 232018
2015-03-12 07:28:41 +00:00
0b9dbe33aa
AVX-512: Added SKX forms of shift instructions.
...
Added rotation instructions, encoding only.
Added encoding tests for all these forms.
llvm-svn: 231916
2015-03-11 10:25:42 +00:00
de05f10de2
AVX-512, SKX: Enabled masked_load/store operations for this target.
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Added lowering for ISD::CONCAT_VECTORS and ISD::INSERT_SUBVECTOR for i1 vectors,
it is needed to pass all masked_memop.ll tests for SKX.
llvm-svn: 231371
2015-03-05 15:11:35 +00:00
d207f17fa1
AVX-512: Moved patterns for masked load/store under avx_store, avx_load classes.
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No functional changes.
llvm-svn: 231069
2015-03-03 15:03:35 +00:00
2689d78909
AVX-512: Simplified MOV patterns, no functional changes.
...
llvm-svn: 230954
2015-03-02 12:46:21 +00:00
09b27e7b24
[X86] Fix diassembler crash on AVX512 cmpps/cmppd with immediate that doesn't fit in 5-bits. Fixes PR22743.
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llvm-svn: 230924
2015-03-02 00:22:29 +00:00
0995479e67
Reverted 230471 - gather scatter handling in table gen.
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llvm-svn: 230892
2015-03-01 08:23:41 +00:00
02ffd26023
AVX-512: Added mask and rounding mode for scalar arithmetics
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Added more tests for scalar instructions to destinguish between AVX and AVX-512 forms.
llvm-svn: 230891
2015-03-01 07:44:04 +00:00
56eadcf5ce
AVX-512: Gather and Scatter patterns
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Gather and scatter instructions additionally write to one of the source operands - mask register.
In this case Gather has 2 destination values - the loaded value and the mask.
Till now we did not support code gen pattern for gather - the instruction was generated from
intrinsic only and machine node was hardcoded.
When we introduce the masked_gather node, we need to select instruction automatically,
in the standard way.
I added a flag "hasTwoExplicitDefs" that allows to handle 2 destination operands.
(Some code in the X86InstrFragmentsSIMD.td is commented out, just to split one big
patch in many small patches)
llvm-svn: 230471
2015-02-25 09:46:31 +00:00
52e81bc499
AVX-512: recommitted 229837 + bugfix + test
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llvm-svn: 230223
2015-02-23 15:12:31 +00:00
0d94fa98e5
Revert "AVX-512: Full implementation for VRNDSCALESS/SD instructions and intrinsics."
...
The instructions were being generated on architectures that don't support avx512.
This reverts commit r229837.
llvm-svn: 229942
2015-02-20 00:45:28 +00:00
06b32cdfed
Add a license header to the AVX512 file.
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llvm-svn: 229941
2015-02-20 00:36:53 +00:00
69e8b45b13
AVX-512: Full implementation for VRNDSCALESS/SD instructions and intrinsics.
...
llvm-svn: 229837
2015-02-19 10:48:04 +00:00
714f23bcdb
AVX-512: Added support for FP instructions with embedded rounding mode.
...
By Asaf Badouh <asaf.badouh@intel.com>
llvm-svn: 229645
2015-02-18 07:59:20 +00:00
ba84672519
AVX-512: changes in intel_ocl_bi calling conventions
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- added mask types v8i1 and v16i1 to possible function parameters
- enabled passing 512-bit vectors in standard CC
- added a test for KNL intel_ocl_bi conventions
llvm-svn: 229482
2015-02-17 09:20:12 +00:00
d2cb3c8876
AVX-512: Fixed the "test" operation for i1 type
...
Using KORTESTW for comparison i1 value with zero was wrong since the instruction tests 16 bits.
KORTESTW may be used with KSHIFTL+KSHIFTR that clean the 15 upper bits.
I removed (X86cmp i1, 0) pattern and zero-extend i1 to i8 and then use TESTB.
There are some cases where i1 is in the mask register and the upper bits are already zeroed.
Then KORTESTW is the better solution, but it is subject for optimization.
Meanwhile, I'm fixing the correctness issue.
llvm-svn: 228916
2015-02-12 08:40:34 +00:00
820d49270d
[X86] Remove 'memop' uses from AVX512. Use 'load' instead.
...
llvm-svn: 228562
2015-02-09 04:04:50 +00:00
7b0dd39db6
AVX-512: Added FMA intrinsics with rounding mode
...
By Asaf Badouh and Elena Demikhovsky
Added special nodes for rounding: FMADD_RND, FMSUB_RND..
It will prevent merge between nodes with rounding and other standard nodes.
llvm-svn: 227303
2015-01-28 10:21:27 +00:00
7d3c6d307a
[X86] Teach disassembler to handle illegal immediates on AVX512 integer compare instructions.
...
llvm-svn: 227302
2015-01-28 10:09:56 +00:00
1a603b3f13
AVX-512: Changes in operations on masks registers for KNL and SKX
...
- Added KSHIFTB/D/Q for skx
- Added KORTESTB/D/Q for skx
- Fixed store operation for v8i1 type for KNL
- Store size of v8i1, v4i1 and v2i1 are changed to 8 bits
llvm-svn: 227043
2015-01-25 12:47:15 +00:00
ca8e179bc2
[X86] Give scalar VRNDSCALE instructions priority in AVX512 mode.
...
llvm-svn: 227039
2015-01-25 08:49:22 +00:00
1d60952401
Simplify a multiclass. No functional change.
...
llvm-svn: 227038
2015-01-25 08:49:19 +00:00
53a846764c
[X86] Replace i32i8imm on SSE/AVX instructions with i32u8imm which will make the assembler bounds check them. It will also make them print as unsigned.
...
llvm-svn: 227032
2015-01-25 02:21:16 +00:00
fc946a0e6f
[X86] Use u8imm in several places that used i32i8imm that don't require an i32 type.
...
llvm-svn: 227031
2015-01-25 02:21:13 +00:00
46469aa4da
[X86] Add IntrNoMem to the AVX512 conflict intrinsics.
...
llvm-svn: 226897
2015-01-23 06:11:45 +00:00
e0c8e8f6a7
Revert r226798. Guess I missed the patterns.
...
llvm-svn: 226802
2015-01-22 09:01:20 +00:00
ffef4cf1e1
Use u8imm instead of i32i8imm on a couple instructions that have no patterns and thus no reason to use a larger operand size.
...
llvm-svn: 226798
2015-01-22 08:53:11 +00:00
9b39e54001
[X86] Remove some unused multiclasses from AVX512 instruction file.
...
llvm-svn: 226797
2015-01-22 08:53:08 +00:00
7ff6ab30a9
[X86] Convert all the i8imm used by AVX512 and MMX instructions to u8imm.
...
llvm-svn: 226646
2015-01-21 08:43:49 +00:00
f38dea1cfa
[x86] Add assembly parser bounds checking to the immediate value for cmpss/cmpsd/cmpps/cmppd.
...
llvm-svn: 226642
2015-01-21 06:07:53 +00:00
9f4d485610
[x86] Add some mayLoad/hasSideEffects flags. Remove one that was already covered by a pattern.
...
llvm-svn: 226562
2015-01-20 12:15:30 +00:00
f4bf9119a1
[x86] Change AVX512 intrinsics to take a 8-bit immediate for the comparision kind instead of a 32-bit immediate. This better aligns with the emitted instruction. It also matches SSE and AVX1 equivalents. Also add auto upgrade support.
...
llvm-svn: 226430
2015-01-19 06:07:27 +00:00
3e8b22bc1b
[AVX512] Add intrinsics for masked aligned FP loads and stores
...
Similar to the unaligned cases.
Test was generated with update_llc_test_checks.py.
Part of <rdar://problem/17688758>
llvm-svn: 226296
2015-01-16 18:50:09 +00:00
9fdd078afb
Hide some redundant AVX512 instructions from the asm parser, but force them to show up in the disassembler.
...
llvm-svn: 226155
2015-01-15 09:37:15 +00:00
6e3a582809
[x86] Prevent instruction selection of AVX512 cmp.ps/pd/ss/sd intrinsics with illegal immediates. Correctly this time. I did the wrong patterns the first time.
...
llvm-svn: 224891
2014-12-27 20:08:45 +00:00
1113fb343e
[x86] Prevent instruction selection of AVX512 cmp.ps/pd/ss/sd intrinsics with illegal immediates. Forgot to do this when I did SSE/SSE2/AVX/AVX2.
...
llvm-svn: 224887
2014-12-27 18:51:06 +00:00
fcea06acb5
AVX-512: Added FMA instructions, intrinsics an tests for KNL and SKX targets
...
by Asaf Badouh
http://reviews.llvm.org/D6456
llvm-svn: 224764
2014-12-23 10:30:39 +00:00
3121449f0b
AVX-512: BLENDM - fixed encoding of the broadcast version
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Added more intrinsics and encoding tests.
llvm-svn: 224760
2014-12-23 09:36:28 +00:00
949b0d46bf
AVX-512: Added all forms of BLENDM instructions,
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intrinsics, encoding tests for AVX-512F and skx instructions.
llvm-svn: 224707
2014-12-22 13:52:48 +00:00
Marina Yatsina