Commit Graph

25 Commits

Author SHA1 Message Date
Vasileios Kalintiris 6d68778588 [mips] Expose adjustStackPtr() from MipsInstrInfo. NFC.
Summary:
adjustStackPtr() is implemented from both MipsSEInstrInfo and
Mips16InstrInfo. It makes sense to expose this function from
MipsInstrInfo and avoid explicit casting in some cases.

Depends on D8638.

Reviewers: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D8640

llvm-svn: 233905
2015-04-02 10:42:44 +00:00
Eric Christopher a20c3cf85d Remove the need to cache the subtarget in the Mips TargetRegisterInfo
classes.

llvm-svn: 232012
2015-03-12 05:43:57 +00:00
Benjamin Kramer a7c40ef022 Canonicalize header guards into a common format.
Add header guards to files that were missing guards. Remove #endif comments
as they don't seem common in LLVM (we can easily add them back if we decide
they're useful)

Changes made by clang-tidy with minor tweaks.

llvm-svn: 215558
2014-08-13 16:26:38 +00:00
Eric Christopher 675cb4dab8 Make InstrInfo depend only upon the Subtarget getting passed in
rather than the TargetMachine.

llvm-svn: 213425
2014-07-18 23:25:00 +00:00
Craig Topper 56c590af3b [C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Mips edition
llvm-svn: 207506
2014-04-29 07:58:02 +00:00
Reed Kotler 2db182b5e8 Delete dead code.
llvm-svn: 196551
2013-12-06 00:13:50 +00:00
Reed Kotler 5c8ae09537 Allow the code which returns the length for inline assembler to know
specifically about the .space directive. This allows us to force large
blocks of code to appear in test cases for things like constant islands
without having to make giant test cases to force things like long 
branches to take effect.

llvm-svn: 194555
2013-11-13 04:37:52 +00:00
Reed Kotler 30cedf65ef Clean up code for Mips16 large frame handling.
llvm-svn: 187701
2013-08-04 01:13:25 +00:00
Akira Hatanaka 067d8152f0 [mips] Rename functions. No functionality changes.
llvm-svn: 181713
2013-05-13 17:43:19 +00:00
Akira Hatanaka 465faccafa [mips] Define overloaded versions of storeRegToStack and loadRegFromStack.
No functionality changes.

llvm-svn: 178327
2013-03-29 02:14:12 +00:00
Reed Kotler bd1058a877 Make pseudos FEXT_CCRX16_ins and FEXT_CCRXI16_ins into custom emitters.
llvm-svn: 176007
2013-02-25 02:25:47 +00:00
Reed Kotler 7a86b3dc2b Make psuedo FEXT_T8I816_ins into a custom emitter.
llvm-svn: 176002
2013-02-24 23:17:51 +00:00
Reed Kotler 7b503c2b03 Expand pseudos/macros:
SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16
$T8 shows up as register $24 when emitted from C++ code so we had
to change some tests that were already there for this functionality.

llvm-svn: 175593
2013-02-20 05:45:15 +00:00
Reed Kotler d82171990f Expand pseudos BteqzT8CmpiX16 and BtnezT8CmpiX16.
llvm-svn: 175474
2013-02-19 00:20:58 +00:00
Reed Kotler cb37409b92 Beginning of expanding all current mips16 macro/pseudo instruction sequences.
This expansion will be moved to expandISelPseudos as soon as I can figure
out how to do that. There are other instructions which use this 
ExpandFEXT_T8I816_ins and as soon as I have finished expanding them all,
I will delete the macro asm string text so it has no way to be used
in the future.

llvm-svn: 175413
2013-02-18 00:59:04 +00:00
Reed Kotler 188dad0eeb One more try to make this look nice. I have lots of pseudo lowering
as well as 16/32 bit variants to do and so I want this to look nice
when I do it. I've been experimenting with this. No new test cases
are needed.

llvm-svn: 175369
2013-02-16 19:04:29 +00:00
Reed Kotler 8cf5103b2b Use a different scheme to chose 16/32 variants. This scheme is more
consistent with how BuildMI works. No new tests needed. All should work
the same as before.

llvm-svn: 175342
2013-02-16 09:47:57 +00:00
Reed Kotler f662cff689 For Mips 16, add the optimization where the 16 bit form of addiu sp can be used
if the offset fits in 11 bits. This makes use of the fact that the abi
requires sp to be 8 byte aligned so the actual offset can fit in 8
bits. It will be shifted left and sign extended before being actually used.
The assembler or direct object emitter will shift right the 11 bit
signed field by 3 bits. We don't need to deal with that here.

llvm-svn: 175073
2013-02-13 20:28:27 +00:00
Reed Kotler 66165c8f96 When Mips16 frames grow large, the immediate field may exceed the maximum
allowed size for the instruction. This code uses RegScavenger to fix this.
We sometimes need 2 registers for Mips16 so we must handle things
differently than how register scavenger is normally used.

llvm-svn: 174696
2013-02-08 03:57:41 +00:00
Akira Hatanaka e067e5a13f [mips] 80 columns.
llvm-svn: 171515
2013-01-04 19:38:05 +00:00
Reed Kotler d019dbf75e fix most of remaining issues with large frames.
these patches are tested a lot by test-suite but
make check tests are forthcoming once the next
few patches that complete this are committed.
with the next few patches the pass rate for mips16 is
near 100%

llvm-svn: 170656
2012-12-20 04:07:42 +00:00
Chandler Carruth 802d755533 Sort includes for all of the .h files under the 'lib' tree. These were
missed in the first pass because the script didn't yet handle include
guards.

Note that the script is now able to handle all of these headers without
manual edits. =]

llvm-svn: 169224
2012-12-04 07:12:27 +00:00
Reed Kotler 27a7229c47 Implement ADJCALLSTACKUP and ADJCALLSTACKDOWN
llvm-svn: 167107
2012-10-31 05:21:10 +00:00
Akira Hatanaka cb37e13fa7 Add definitions of two subclasses of MipsRegisterInfo, Mips16RegisterInfo and
MipsSERegisterInfo.

llvm-svn: 161092
2012-07-31 23:41:32 +00:00
Akira Hatanaka b7fa3c9db0 Add definitions of two subclasses of MipsInstrInfo, MipsInstrInfo (for mips16),
and MipsSEInstrInfo (for mips32/64).

llvm-svn: 161081
2012-07-31 21:49:49 +00:00