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507 Commits

Author SHA1 Message Date
Vincent Lejeune a8c38fedd6 R600: Replace legacy debug code in AMDILCFGStructurizer.cpp 
llvm-svn: 186723
 2013-07-19 21:44:56 +00:00
Tom Stellard 8374720aad R600/SI: Fix crash with VSELECT 
https://bugs.freedesktop.org/show_bug.cgi?id=66175

llvm-svn: 186616
 2013-07-18 21:43:53 +00:00
Tom Stellard adf732cfbc R600/SI: Add support for v2f32 loads 
llvm-svn: 186615
 2013-07-18 21:43:48 +00:00
Tom Stellard ed2f6149f3 R600/SI: Add support for v2f32 stores 
llvm-svn: 186614
 2013-07-18 21:43:42 +00:00
Tom Stellard 67ae4762ef R600: Expand VSELECT for all types 
llvm-svn: 186613
 2013-07-18 21:43:35 +00:00
Craig Topper 8fc4096fab Move string pointer from being a static class member to just a static global in the one file its needed in. 
llvm-svn: 186476
 2013-07-17 00:31:35 +00:00
Craig Topper d3a34f81f8 Add 'const' qualifiers to static const char* variables. 
llvm-svn: 186371
 2013-07-16 01:17:10 +00:00
Tom Stellard 31209cc8eb R600/SI: Add support for 64-bit loads 
https://bugs.freedesktop.org/show_bug.cgi?id=65873

llvm-svn: 186339
 2013-07-15 19:00:09 +00:00
Craig Topper 0afd0ab749 Make some arrays 'static const' 
llvm-svn: 186307
 2013-07-15 06:39:13 +00:00
Craig Topper 5871321e49 Use llvm::array_lengthof to replace sizeof(array)/sizeof(array[0]). 
llvm-svn: 186301
 2013-07-15 04:27:47 +00:00
Craig Topper b94011fd28 Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size. 
llvm-svn: 186274
 2013-07-14 04:42:23 +00:00
Benjamin Kramer c22c790f89 R600: Remove unsafe type punning. No intended functionality change. 
llvm-svn: 186196
 2013-07-12 20:18:05 +00:00
Tom Stellard ccae60acc3 R600/SI: Add support for f64 kernel arguments 
Patch by: Niels Ole Salscheider

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 186182
 2013-07-12 18:15:26 +00:00
Tom Stellard 4e1100ab75 R600/SI: Implement select and compares for SI 
Patch by: Niels Ole Salscheider

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 186181
 2013-07-12 18:15:19 +00:00
Tom Stellard 8ed7b45da3 R600/SI: Add fsqrt pattern for SI 
Patch by: Niels Ole Salscheider

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 186180
 2013-07-12 18:15:13 +00:00
Tom Stellard 2a6a610516 R600/SI: Add double precision fsub pattern for SI 
Patch by: Niels Ole Salscheider

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 186179
 2013-07-12 18:15:08 +00:00
Tom Stellard ab8a8c84d4 R600/SI: SI support for 64bit ConstantFP 
Patch by: Niels Ole Salscheider

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 186178
 2013-07-12 18:15:02 +00:00
Tom Stellard 7512c0803c R600/SI: Add initial double precision support for SI 
Patch by: Niels Ole Salscheider

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 186177
 2013-07-12 18:14:56 +00:00
Aaron Ballman f04bbd8b7f Replacing an empty switch with its moral equivalent. No functional changes intended. 
llvm-svn: 186017
 2013-07-10 17:19:22 +00:00
Michel Danzer 49812b5bbd R600/SI: Initial local memory support 
Enough for the radeonsi driver to use it for calculating derivatives.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 186012
 2013-07-10 16:37:07 +00:00
Michel Danzer 1f87df365f R600/SI: Add pattern for the AMDGPU.barrier.local intrinsic 
lit test coverage to follow in the next commit.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 186011
 2013-07-10 16:36:57 +00:00
Michel Danzer 8d69617b27 R600/SI: Add intrinsic for retrieving the current thread ID 
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 186010
 2013-07-10 16:36:52 +00:00
Michel Danzer 1c45430e76 R600/SI: Initial support for LDS/GDS instructions 
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 186009
 2013-07-10 16:36:43 +00:00
Michel Danzer 83f87c4c2e R600/SI: Add intrinsics for texture sampling with user derivatives 
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 186008
 2013-07-10 16:36:36 +00:00
Vincent Lejeune ce499744b3 R600: Do not predicated basic block with multiple alu clause 
Test is not included as it is several 1000 lines long.
To test this functionnality, a test case must generate at least 2 ALU clauses,
where an ALU clause is ~110 instructions long.

NOTE: This is a candidate for the stable branch.
llvm-svn: 185943
 2013-07-09 15:03:33 +00:00
Vincent Lejeune b8aac8d720 R600: Fix a rare bug where swizzle optimization returns wrong values 
llvm-svn: 185942
 2013-07-09 15:03:25 +00:00
Vincent Lejeune a4d8d2ef2b R600: Fix wrong export reswizzling 
llvm-svn: 185941
 2013-07-09 15:03:19 +00:00
Vincent Lejeune b55940cc7d R600: Use DAG lowering pass to handle fcos/fsin 
NOTE: This is a candidate for the stable branch.
llvm-svn: 185940
 2013-07-09 15:03:11 +00:00
Vincent Lejeune f10d1cd2a3 R600: Print Export Swizzle 
llvm-svn: 185939
 2013-07-09 15:03:03 +00:00
Craig Topper 31ee5866de Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid specifying the vector size. 
llvm-svn: 185540
 2013-07-03 15:07:05 +00:00
Rafael Espindola 64e1af8eb9 Remove address spaces from MC. 
This is dead code since PIC16 was removed in 2010. The result was an odd mix,
where some parts would carefully pass it along and others would assert it was
zero (most of the object streamer for example).

llvm-svn: 185436
 2013-07-02 15:49:13 +00:00
Chad Rosier 797ee3e3c6 Add a newline. 
llvm-svn: 185385
 2013-07-01 21:31:10 +00:00
Vincent Lejeune a8a50248d8 R600: Fix an unitialized variable in R600InstrInfo.cpp 
llvm-svn: 185294
 2013-06-30 21:44:06 +00:00
Benjamin Kramer 396906456f R600: Unbreak GCC build. 
operator++ on an enum is not legal. clang happens to accept it anyways, I think
that's a known bug.

llvm-svn: 185269
 2013-06-29 20:04:19 +00:00
Vincent Lejeune 77a8352476 R600: Support schedule and packetization of trans-only inst 
llvm-svn: 185268
 2013-06-29 19:32:43 +00:00
Vincent Lejeune bb8a872158 R600: Bank Swizzle now display SCL equivalent 
llvm-svn: 185267
 2013-06-29 19:32:29 +00:00
Tom Stellard c46e56721e R600/SI: Add processor types for each CIK variant 
Patch By: Alex Deucher

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
llvm-svn: 185209
 2013-06-28 20:23:29 +00:00
Tom Stellard c026e8bc8e R600: Add local memory support via LDS 
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 185162
 2013-06-28 15:47:08 +00:00
Tom Stellard ce540330df R600: Add support for GROUP_BARRIER instruction 
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 185161
 2013-06-28 15:46:59 +00:00
Tom Stellard 5eb903d9c5 R600: Add ALUInst bit to tablegen definitions v2 
v2:
  - Remove functions left over from a previous rebase.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 185160
 2013-06-28 15:46:53 +00:00
Tom Stellard 02661d9605 R600: Use new getNamedOperandIdx function generated by TableGen 
llvm-svn: 184880
 2013-06-25 21:22:18 +00:00
Aaron Watry 0a794a4612 R600: Consolidate expansion of v2i32/v4i32 ops for EG/SI 
By default, we expand these operations for both EG and SI. Move the
duplicated code into a common space for now. If the targets ever actually
implement these operations as instructions, we can override that in the relevant
target.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 184848
 2013-06-25 13:55:57 +00:00
Aaron Watry daabb20e1b R600/SI: Expand xor v2i32/v4i32 
Add test cases for both vector sizes on SI and also add v2i32 test for EG.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 184846
 2013-06-25 13:55:52 +00:00
Aaron Watry 83fa6006bc R600/SI: Expand urem of v2i32/v4i32 for SI 
Also add lit test for both cases on SI, and v2i32 for evergreen.

Note: I followed the guidance of the v4i32 EG check... UREM produces really
complex code, so let's just check that the instruction was lowered
successfully.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 184844
 2013-06-25 13:55:46 +00:00
Aaron Watry 5527b6c6b6 R600/SI: Expand udiv v[24]i32 for SI and v2i32 for EG 
Also add lit test for both cases on SI, and v2i32 for evergreen.

Note: I followed the guidance of the v4i32 EG check... UDIV produces really
complex code, so let's just check that the instruction was lowered
successfully.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 184843
 2013-06-25 13:55:43 +00:00
Aaron Watry 16d80c0529 R600/SI: Expand ashr of v2i32/v4i32 for SI 
Also add lit test for both cases on SI, and v2i32 for evergreen.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 184842
 2013-06-25 13:55:40 +00:00
Aaron Watry f63791e778 R600/SI: Expand srl of v2i32/v4i32 for SI 
Also add lit test for both cases on SI, and v2i32 for evergreen.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 184841
 2013-06-25 13:55:37 +00:00
Aaron Watry 5584553984 R600/SI: Expand shl of v2i32/v4i32 for SI 
Also add lit test for both cases on SI, and v2i32 for evergreen.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 184840
 2013-06-25 13:55:32 +00:00
Aaron Watry 2fa162e88e R600/SI: Expand or of v2i32/v4i32 for SI 
Also add lit test for both cases on SI, and v2i32 for evergreen.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 184839
 2013-06-25 13:55:29 +00:00
Aaron Watry 265eef5efe R600/SI: Expand mul of v2i32/v4i32 for SI 
Also add lit test for both cases on SI, and v2i32 for evergreen.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 184838
 2013-06-25 13:55:26 +00:00
Aaron Watry 00aeb119db R600/SI: Expand and of v2i32/v4i32 for SI 
Also add lit test for both cases on SI, and v2i32 for evergreen.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 184837
 2013-06-25 13:55:23 +00:00
Tom Stellard 0125f2a6e4 R600/SI: Report unaligned memory accesses as legal for > 32-bit types 
In reality, some unaligned memory accesses are legal for 32-bit types and
smaller too, but it all depends on the address space.  Allowing
unaligned loads/stores for > 32-bit types is mainly to prevent the
legalizer from splitting one load into multiple loads of smaller types.

https://bugs.freedesktop.org/show_bug.cgi?id=65873

llvm-svn: 184822
 2013-06-25 02:39:35 +00:00
Tom Stellard 9810ec613c R600: Add support for i32 loads from the constant address space on Cayman 
Tested-By: Aaron Watry <awatry@gmail.com>
llvm-svn: 184821
 2013-06-25 02:39:30 +00:00
Tom Stellard b06f3fc1be R600/SI: Add support for v4i32 and v4f32 kernel args 
Tested-By: Aaron Watry <awatry@gmail.com>
llvm-svn: 184820
 2013-06-25 02:39:25 +00:00
Tom Stellard 9d2e1500b4 R600: Fix typo in R600Schedule.td 
This should only make a difference in programs that use a lot of the
vector ALU instructions like BFI_INT and BIT_ALIGN.  There is a slight
improvement in the phatk bitcoin mining kernel with this patch on
Evergreen (vector size == 1):

Before:
1173 Instruction Groups / 9520 dwords

After:
1167 Instruction Groups / 9510 dwords

Reviewed-by: Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 184819
 2013-06-25 02:39:20 +00:00
Aaron Watry 52a72c926c R600: Fix spelling error in comment 
our -> or

llvm-svn: 184756
 2013-06-24 16:57:57 +00:00
Tom Stellard 96d38760fc R600/SI: Expand sub for v2i32 and v4i32 for SI 
Also add a v2i32 test to the existing v4i32 test.

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry<awatry@gmail.com>
llvm-svn: 184482
 2013-06-20 21:55:37 +00:00
Tom Stellard 043795e818 R600/SI: Expand add for v2i32 and v4i32 
Also add SI tests to existing file and a v2i32 test for both
R600 and SI.

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>
llvm-svn: 184481
 2013-06-20 21:55:30 +00:00
Tom Stellard 6ec9e8043c R600: Expand v2i32 load/store instead of custom lowering 
The custom lowering causes llc to crash with a segfault.

Ideally, the custom lowering can be fixed, but this allows
programs which load/store v2i32 to work without crashing.

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry<awatry@gmail.com>
llvm-svn: 184480
 2013-06-20 21:55:23 +00:00
Bill Wendling a3cd350249 Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change. 
llvm-svn: 184360
 2013-06-19 21:36:55 +00:00
Matt Arsenault d46fce1141 Move StructurizeCFG out of R600 to generic Transforms. 
Register it with PassManager

llvm-svn: 184343
 2013-06-19 20:18:24 +00:00
Matt Arsenault 2aabb06175 Use GetUnderlyingObject instead of custom function 
llvm-svn: 184261
 2013-06-18 23:37:58 +00:00
Bill Wendling b7b1681157 Remove dead prototype. 
llvm-svn: 184173
 2013-06-18 06:24:14 +00:00
Vincent Lejeune 41d4cf26b4 R600: PV stores Reg id, not index 
llvm-svn: 184117
 2013-06-17 20:16:40 +00:00
Vincent Lejeune 8bd10421ec R600: Properly set COUNT_3 bit in TEX clause initiating inst for pre EG gen. 
Fixes rv7x0 bug in Heaven reported here:
https://bugs.freedesktop.org/show_bug.cgi?id=64257

llvm-svn: 184116
 2013-06-17 20:16:26 +00:00
Tom Stellard 371573448c R600: Add SI load support for v[24]i32 and store for v2i32 
Also add a seperate vector lit test file, since r600 doesn't seem to handle
v2i32 load/store yet, but we can test both for SI.

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>
llvm-svn: 184021
 2013-06-15 00:09:31 +00:00
Tom Stellard ecf9d86404 R600: Use correct encoding for Vertex Fetch instructions on Cayman 
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 184016
 2013-06-14 22:12:30 +00:00
Tom Stellard 6aa0d5578d R600: Use EXPORT_RAT_INST_STORE_DWORD for stores on Cayman 
We were using RAT_INST_STORE_RAW, which seemed to work, but the docs
say this instruction doesn't exist for Cayman, so it's probably safer
to use a documented instruction instead.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 184015
 2013-06-14 22:12:24 +00:00
Tom Stellard d99b7932ae R600: Factor the instruction encoding out the RAT_WRITE_CACHELESS_eg class 
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 184014
 2013-06-14 22:12:19 +00:00
Tom Stellard 3d0823f1cd R600: Move instruction encoding definitions into a separate .td file 
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 184013
 2013-06-14 22:12:09 +00:00
Tom Stellard adba083bc2 R600: Don't try to fix reg class when copying IMPLICIT_DEF to a register 
The test case for this is way too complex to be useful as a lit test,
and I was unable to reduce it.

https://bugs.freedesktop.org/show_bug.cgi?id=65438

llvm-svn: 183937
 2013-06-13 20:14:00 +00:00
Benjamin Kramer 193960c822 R600: Make helper functions static. 
llvm-svn: 183744
 2013-06-11 13:32:25 +00:00
Vincent Lejeune d1a9d18120 R600: Use a refined heuristic to choose when switching clause 
This is using a hint from AMD APP OpenCL Programming Guide with
empirically tweaked parameters.
I used Unigine Heaven 3.0 to determine best parameters on my system
(i7 2600/Radeon 6950/Kernel 3.9.4) the benchmark :
it went from 38.8 average fps to 39.6, which is ~3% gain.
(Lightmark 2008.2 gain is much more marginal: from 537 to 539)

There is no lit test provided as the parameter were determined
empirically and it it would be nearly impossiblet to find a test
program that check for optimal behavior.

llvm-svn: 183593
 2013-06-07 23:30:34 +00:00
Vincent Lejeune 4d143328df R600: Anti dep better handled in tex clause 
llvm-svn: 183592
 2013-06-07 23:30:26 +00:00
Tom Stellard d74583777f R600: Fix calculation of stack offset in AMDGPUFrameLowering 
We weren't computing structure size correctly and we were relying on
the original alloca instruction to compute the offset, which isn't
always reliable.

Reviewed-by: Vincent Lejeune <vljn@ovi.com>
llvm-svn: 183568
 2013-06-07 20:52:05 +00:00
Tom Stellard a6c6e1bfc2 R600: Rework subtarget info and remove AMDILDevice classes 
This should simplify the subtarget definitions and make it easier to
add new ones.

Reviewed-by: Vincent Lejeune <vljn@ovi.com>
llvm-svn: 183566
 2013-06-07 20:37:48 +00:00
Bill Wendling 37e9adb091 Don't cache the instruction and register info from the TargetMachine, because 
the internals of TargetMachine could change.

No functionality change intended.

llvm-svn: 183561
 2013-06-07 20:28:55 +00:00
Tom Stellard 3498e4ff1d R600: Fix the fetch limits for R600 generation GPUs 
Reviewed-by: Vincent Lejeune <vljn@ovi.com>

https://bugs.freedesktop.org/show_bug.cgi?id=64257

llvm-svn: 183560
 2013-06-07 20:28:55 +00:00
Tom Stellard 99792774a4 R600: Move Subtarget feature definitions into AMDGPU.td 
This is the convention used by the other targets.

Reviewed-by: Vincent Lejeune <vljn@ovi.com>
llvm-svn: 183559
 2013-06-07 20:28:49 +00:00
Tom Stellard b0804ec2ad R600: Remove unnecessary include 
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
llvm-svn: 183558
 2013-06-07 20:28:43 +00:00
Benjamin Kramer 705d841bb6 R600: Don't compare iterators of different maps. 
Found be libstdc's debug mode.

llvm-svn: 183549
 2013-06-07 19:59:34 +00:00
Benjamin Kramer ebe0be9ca4 Vincent says the element is at most once in the vector, so we don't need a full std::remove. 
llvm-svn: 183541
 2013-06-07 18:18:12 +00:00
Benjamin Kramer a857fe115b R600: Fix a potential iterator invalidation issue. 
As a bonus this reduces the loop from O(n^2) to O(n).

llvm-svn: 183532
 2013-06-07 16:13:49 +00:00
Vincent Lejeune 931bb768fd R600: Remove an extra break in R600OptimizeVectorRegisters.cpp 
llvm-svn: 183528
 2013-06-07 15:44:53 +00:00
Vincent Lejeune 0030362ed9 R600: Rewrite an awkward loop in R600MachineScheduler 
llvm-svn: 183458
 2013-06-06 23:08:32 +00:00
Vincent Lejeune 54476a1503 R600: Remove leftover code in R600MachineScheduler.cpp 
Spotted by Benjamin Kramer.

llvm-svn: 183413
 2013-06-06 14:18:29 +00:00
Bill Wendling b91216817f Cast to the correct type. Pointer, not reference. 
llvm-svn: 183385
 2013-06-06 05:39:29 +00:00
NAKAMURA Takumi 4a8f079371 R600OptimizeVectorRegisters.cpp: Tweak a warning. [-Wsometimes-uninitialized] 
FIXME: Is it false alarm?
llvm-svn: 183371
 2013-06-06 02:15:12 +00:00
NAKAMURA Takumi e5555fc238 R600OptimizeVectorRegisters.cpp: Suppress a warning. [-Wunused-variable] 
llvm-svn: 183370
 2013-06-06 02:15:06 +00:00
NAKAMURA Takumi 372574d447 Trailing linefeed. 
llvm-svn: 183369
 2013-06-06 02:15:00 +00:00
Bill Wendling e410576865 Cast to the proper type. 
llvm-svn: 183365
 2013-06-06 01:04:21 +00:00
Tom Stellard acec99c948 R600: Replace predicate loop with predicate function 
llvm-svn: 183351
 2013-06-05 23:39:50 +00:00
Vincent Lejeune dec1875207 R600: Add a pass that merge Vector Register 
Previously commited @183279 but tests were failing, reverted @183286
It was broken because @183336 was missing, now it's there.

llvm-svn: 183343
 2013-06-05 21:38:04 +00:00
Vincent Lejeune 4b5b849753 R600: Schedule copy from phys register at beginning of block 
It allows regalloc pass to remove them by trivially assigning associated reg

llvm-svn: 183336
 2013-06-05 20:27:35 +00:00
Tom Stellard aad5376fb6 R600: Make sure to schedule AR register uses and defs in the same clause 
Reviewed-by: vljn at ovi.com
llvm-svn: 183294
 2013-06-05 03:43:06 +00:00
Rafael Espindola beef23fe21 Revert "R600: Add a pass that merge Vector Register" 
This reverts commit r183279. CodeGen/R600/texture-input-merge.ll was failing.

llvm-svn: 183286
 2013-06-05 01:48:30 +00:00
Vincent Lejeune a45aafabfe R600: Add a pass that merge Vector Register 
llvm-svn: 183279
 2013-06-04 23:17:26 +00:00
Vincent Lejeune c689679173 R600: Const/Neg/Abs can be folded to dot4 
llvm-svn: 183278
 2013-06-04 23:17:15 +00:00
Vincent Lejeune 276ceb8d5f R600: Swizzle texture/export instructions 
llvm-svn: 183229
 2013-06-04 15:04:53 +00:00
Aaron Ballman 19978553d4 Silencing an MSVC warning about mixing bool and unsigned int. 
llvm-svn: 183176
 2013-06-04 01:03:03 +00:00
Tom Stellard 94593ee8c3 R600/SI: Add support for work item and work group intrinsics 
llvm-svn: 183138
 2013-06-03 17:40:18 +00:00
Tom Stellard ed882c2f1b R600/SI: Add a calling convention for compute shaders 
llvm-svn: 183137
 2013-06-03 17:40:11 +00:00
Tom Stellard 046039e81b R600/SI: Custom lower i64 sign_extend 
llvm-svn: 183136
 2013-06-03 17:40:03 +00:00
Tom Stellard 0518ff89ba R600/SI: Adjust some instructions' out register class after ISel 
This is necessary to avoid generating VGPR to SGPR copies in some
cases.

llvm-svn: 183135
 2013-06-03 17:39:58 +00:00
Tom Stellard bad1f59212 R600/SI: Handle REG_SEQUENCE in fitsRegClass() 
llvm-svn: 183134
 2013-06-03 17:39:54 +00:00
Tom Stellard b5a97004fb R600/SI: Handle nodes with glue results correctly SITargetLowering::foldOperands() 
llvm-svn: 183133
 2013-06-03 17:39:50 +00:00
Tom Stellard 2183b70523 R600/SI: Fixup CopyToReg register class in PostprocessISelDAG() 
The CopyToReg nodes will sometimes try to copy a value from a VGPR to an
SGPR.  This kind of copy is not possible, so we need to detect
VGPR->SGPR copies and do something else.  The current strategy is to
replace these copies with VGPR->VGPR copies and hope that all the users
of CopyToReg can accept VGPRs as arguments.

llvm-svn: 183132
 2013-06-03 17:39:46 +00:00
Tom Stellard 07a10a3d3f R600/SI: Add support for global loads 
llvm-svn: 183131
 2013-06-03 17:39:43 +00:00
Tom Stellard 556d9aa841 R600/SI: Rework MUBUF store instructions 
The lowering of stores is now mostly handled in the tablegen files.  No
more BUFFER_STORE nodes I generated during legalization.

llvm-svn: 183130
 2013-06-03 17:39:37 +00:00
Vincent Lejeune 91a942b93e R600: 3 op instructions have no write bit but the result are store in PV 
llvm-svn: 183111
 2013-06-03 15:56:12 +00:00
Vincent Lejeune eabf83e0a2 R600: CALL_FS consumes a stack size entry 
llvm-svn: 183108
 2013-06-03 15:44:42 +00:00
Vincent Lejeune f83df1f1cb R600: use capital letter for PV channel 
llvm-svn: 183107
 2013-06-03 15:44:35 +00:00
Vincent Lejeune a09873dda7 R600: Constraints input regs of interp_xy,_zw 
llvm-svn: 183106
 2013-06-03 15:44:16 +00:00
Ahmed Bougacha b1a4d9da3b Make SubRegIndex size mandatory, following r183020. 
This also makes TableGen able to compute sizes/offsets of synthesized
indices representing tuples.

llvm-svn: 183061
 2013-05-31 23:45:26 +00:00
Patrik Hagglund ae8faf2e9a Temporary fix to get rid of gcc warning. 
llvm-svn: 182832
 2013-05-29 07:32:08 +00:00
Andrew Trick ef9de2a739 Track IR ordering of SelectionDAG nodes 2/4. 
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.

llvm-svn: 182703
 2013-05-25 02:42:55 +00:00
Tom Stellard 1b086cbcb8 R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst reg 
Patch by: Vincent Lejeune

https://bugs.freedesktop.org/show_bug.cgi?id=64877

NOTE: This is a candidate for the 3.3 branch.
llvm-svn: 182600
 2013-05-23 18:26:42 +00:00
Benjamin Kramer d78bb468bd Move passes from namespace llvm into anonymous namespaces. Sort includes while there. 
llvm-svn: 182594
 2013-05-23 17:10:37 +00:00
Benjamin Kramer 635e368e33 R600: Hide symbols of implementation details. 
Also removes an unused function.

llvm-svn: 182587
 2013-05-23 15:43:05 +00:00
Aaron Ballman 15f193a1a3 Setting the default value (fixes CRT assertions about uninitialized variable use when doing debug MSVC builds), and fixing coding style. 
llvm-svn: 182585
 2013-05-23 14:55:00 +00:00
Rafael Espindola 00345fa97b Fix 32 bit build in c++11 mode. 
The error was:
error: non-constant-expression cannot be narrowed from type 'long long' to 'long' in initializer list [-Wc++11-narrowing]
        MI.getOperand(6).getImm() & 0x1F,

llvm-svn: 182584
 2013-05-23 13:22:30 +00:00
Rafael Espindola 39aca620db Fix a leak on the r600 backend. 
This should bring the valgrind bot back to life.

llvm-svn: 182561
 2013-05-23 03:31:47 +00:00
Rafael Espindola bd6847fbea clang-format this file. 
llvm-svn: 182560
 2013-05-23 03:28:39 +00:00
Rafael Espindola e3d83fb8c3 Fix use after free (pr16103). 
llvm-svn: 182482
 2013-05-22 15:31:11 +00:00
Rafael Espindola ebd8e38849 Check that a function starts with llvm. before using GET_FUNCTION_RECOGNIZER. 
Fixes a use of uninitialized memory found by asan and valgind.

llvm-svn: 182480
 2013-05-22 14:57:42 +00:00
NAKAMURA Takumi 4f328e1c2f R600ISelLowering.cpp: Avoid "using namespace Intrinsic;" to appease MSC. Specify namespaces explicitly here. 
MSC is confused about "memcpy" between <cstring> and llvm::Intrinsic::memcpy, when llvm::Intrinsic were exposed.

llvm-svn: 182452
 2013-05-22 06:37:31 +00:00
NAKAMURA Takumi 18ca09c1cc R600: Whitespace and untabify. 
llvm-svn: 182451
 2013-05-22 06:37:25 +00:00
Owen Anderson 616852848a Create an FPOW SDNode opcode def in the target independent .td file rather than in a specific backend. 
llvm-svn: 182450
 2013-05-22 06:36:09 +00:00
Rafael Espindola 21ea01d132 Attempt to fix the mingw32 bot. 
This should hopefully fix
http://lab.llvm.org:8011/builders/clang-x86_64-darwin11-self-mingw32

llvm-svn: 182446
 2013-05-22 02:30:47 +00:00
Rafael Espindola 525cf28652 s/u_int32_t/uint32_t/ 
llvm-svn: 182444
 2013-05-22 01:36:19 +00:00
Rafael Espindola f568827654 Fix warning in non-assert build. 
llvm-svn: 182443
 2013-05-22 01:29:38 +00:00
Benjamin Kramer 927ca942ce R600: Fix bug detected by GCC warning. 
R600TextureIntrinsicsReplacer.cpp:232: warning: the address of ‘ArgsType’ will always evaluate as ‘true’

This doesn't have any effect on the output as a vararg intrinsic behaves the
same way as a non-vararg one.

llvm-svn: 182293
 2013-05-20 15:58:43 +00:00
Tom Stellard f1ee716446 R600/SI: Use a multiclass for MUBUF_Load_Helper 
This will simplify the instructions and also the pattern definitions.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182288
 2013-05-20 15:02:31 +00:00
Tom Stellard b8458f88d6 R600/SI: Add a pattern for S_LOAD_DWORDX2_* instructions 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182287
 2013-05-20 15:02:28 +00:00
Tom Stellard d2eebf001e R600/SI: Add pattern for rotr 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182286
 2013-05-20 15:02:24 +00:00
Tom Stellard 5643c4ac72 R600: Swap the legality of rotl and rotr 
The hardware supports rotr and not rotl.

llvm-svn: 182285
 2013-05-20 15:02:19 +00:00
Tom Stellard 1cfd7a50bb R600/SI: Add patterns for 64-bit shift operations 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182284
 2013-05-20 15:02:12 +00:00
Tom Stellard 459a79a81c R600/SI: Use the same names for VOP3 operands and encoding fields 
This makes it possible to reorder the operands without breaking the
encoding.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182283
 2013-05-20 15:02:08 +00:00
Tom Stellard b35efba4d9 R600/SI: Make fitsRegClass() operands const 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 182282
 2013-05-20 15:02:01 +00:00
Matt Arsenault 75865923c9 Add LLVMContext argument to getSetCCResultType 
llvm-svn: 182180
 2013-05-18 00:21:46 +00:00
Rafael Espindola 5986ce0e5d Fix the build in c++11 mode. 
The errors were:

non-constant-expression cannot be narrowed from type 'int64_t' (aka 'long') to 'uint32_t' (aka 'unsigned int') in initializer list

and

non-constant-expression cannot be narrowed from type 'long' to 'uint32_t' (aka 'unsigned int') in initializer list

llvm-svn: 182168
 2013-05-17 22:45:52 +00:00
Vincent Lejeune d3fcb5016c R600: Lower int_load_input to copyFromReg instead of Register node 
It solves a bug uncovered by dot4 patch where the register class of
int_load_input use was ignored.

llvm-svn: 182130
 2013-05-17 16:51:06 +00:00
Vincent Lejeune 3d5118ca40 R600: Use bottom up scheduling algorithm 
llvm-svn: 182129
 2013-05-17 16:50:56 +00:00
Vincent Lejeune 4c81d4da6f R600: Use depth first scheduling algorithm 
It should increase PV substitution opportunities and lower gpr
usage (pending computations path are "flushed" sooner)

llvm-svn: 182128
 2013-05-17 16:50:44 +00:00
Vincent Lejeune e958c8e0d8 R600: Replace big texture opcode switch in scheduler by usesTC/usesVC 
llvm-svn: 182127
 2013-05-17 16:50:37 +00:00
Vincent Lejeune 519f21eed3 R600: Relax some vector constraints on Dot4. 
Dot4 now uses 8 scalar operands instead of 2 vectors one which allows register
coalescer to remove some unneeded COPY.
This patch also defines some structures/functions that can be used to handle
every vector instructions (CUBE, Cayman special instructions...) in a similar
fashion.

llvm-svn: 182126
 2013-05-17 16:50:32 +00:00
Vincent Lejeune d3eed66e8c R600: Improve texture handling 
llvm-svn: 182125
 2013-05-17 16:50:20 +00:00
Vincent Lejeune 4ebef18ab5 R600: Rename 128 bit registers. 
Almost all instructions that takes a 128 bits reg as input (fetch, export...)
have the abilities to swizzle their argument and output. Instead of printing
default swizzle for each 128 bits reg, rename T*.XYZW to T* and let instructions
print potentially optimized swizzles themselves.

llvm-svn: 182124
 2013-05-17 16:50:09 +00:00
Vincent Lejeune 0fca91d52e R600: Some factorization 
llvm-svn: 182123
 2013-05-17 16:50:02 +00:00
Vincent Lejeune f9f4e1e7db R600: Factorize Fetch size limit inside AMDGPUSubTarget 
llvm-svn: 182122
 2013-05-17 16:49:55 +00:00