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36 Commits

Author SHA1 Message Date
Evan Cheng a52c3b4b8b Fix a 80 col. violation. 
llvm-svn: 60901
 2008-12-11 22:02:02 +00:00
Dan Gohman 69cc2cbbff Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning. 
llvm-svn: 60487
 2008-12-03 18:15:48 +00:00
Evan Cheng 9c205bf03c Fix fuitos encoding. 
llvm-svn: 59344
 2008-11-15 00:40:57 +00:00
Evan Cheng 320902bcfc fsub{d|s} encoding bugs. 
llvm-svn: 59234
 2008-11-13 07:59:48 +00:00
Evan Cheng af644b50b4 Consolidate formats; fix FCMPED etc. encodings. 
llvm-svn: 59107
 2008-11-12 07:18:38 +00:00
Evan Cheng 4b6c7efbde Fix VFP conversion instruction encodings. 
llvm-svn: 59104
 2008-11-12 06:41:41 +00:00
Evan Cheng a0e2f26320 Fix encoding of single-precision VFP registers. 
llvm-svn: 59102
 2008-11-12 02:19:38 +00:00
Evan Cheng 97ccab888a Fix FMDRR encoding. 
llvm-svn: 59088
 2008-11-11 22:46:12 +00:00
Evan Cheng 8cbbcb1f2f Encode VFP load / store instructions. 
llvm-svn: 59084
 2008-11-11 21:48:44 +00:00
Evan Cheng 38c9a14a88 Encode VFP conversion instructions. 
llvm-svn: 59074
 2008-11-11 19:40:26 +00:00
Evan Cheng ac2af2fdb2 Encode VFP arithmetic instructions. 
llvm-svn: 59016
 2008-11-11 02:11:05 +00:00
Evan Cheng 47b546d75f Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug. 
llvm-svn: 58800
 2008-11-06 08:47:38 +00:00
Jim Grosbach a7cd7bc353 udpate header comment: s/VP/VFP/ 
llvm-svn: 56126
 2008-09-11 21:41:29 +00:00
Evan Cheng 0e7b00d79f Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF. 
llvm-svn: 48380
 2008-03-15 00:03:38 +00:00
Chris Lattner 9a249b0ce5 rename SDTRet -> SDTNone. 
Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td.

llvm-svn: 46017
 2008-01-15 22:02:54 +00:00
Chris Lattner 94de7bc3aa get def use info more correct. 
llvm-svn: 45821
 2008-01-10 05:12:37 +00:00
Evan Cheng 7250120177 Only mark instructions that load a single value without extension as isSimpleLoad = 1. 
llvm-svn: 45727
 2008-01-07 23:56:57 +00:00
Chris Lattner a4ce4f6987 rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate. 
llvm-svn: 45667
 2008-01-06 23:38:27 +00:00
Chris Lattner 10324d0175 rename isStore -> mayStore to more accurately reflect what it captures. 
llvm-svn: 45656
 2008-01-06 08:36:04 +00:00
Chris Lattner f4d55ec4e8 remove explicit isStore flags that are now inferrable. 
llvm-svn: 45653
 2008-01-06 05:55:01 +00:00
Chris Lattner f3ebc3f3d2 Remove attribution from file headers, per discussion on llvmdev. 
llvm-svn: 45418
 2007-12-29 20:36:04 +00:00
Evan Cheng 6e68381e02 Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled. 
llvm-svn: 44960
 2007-12-12 23:12:09 +00:00
Evan Cheng 3e18e504ae Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. 
llvm-svn: 41863
 2007-09-11 19:55:27 +00:00
Evan Cheng f7c6effc44 Initial JIT support for ARM by Raul Fernandes Herbster. 
llvm-svn: 40887
 2007-08-07 01:37:15 +00:00
Evan Cheng 94b5a80b93 Change instruction description to split OperandList into OutOperandList and 
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033
 2007-07-19 01:14:50 +00:00
Evan Cheng 9d41b311fb Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit. 
llvm-svn: 38501
 2007-07-10 18:08:01 +00:00
Evan Cheng 881248c4e1 No need for ccop anymore. 
llvm-svn: 37965
 2007-07-06 23:34:09 +00:00
Evan Cheng aa3b8014bd Each ARM use predicate operand is now made up of two components. The new component is the CPSR register. 
llvm-svn: 37895
 2007-07-05 07:13:32 +00:00
Evan Cheng e8c3cbf971 Mark these instructions clobbersPred. They modify the condition code register. 
llvm-svn: 37468
 2007-06-06 10:17:05 +00:00
Evan Cheng 19eeee41ca For VFP2 fldm, fstm instructions, the condition code is printed after the address mode and size specifier. e.g. fstmiaseq, not fstmeqias. 
llvm-svn: 37351
 2007-05-29 23:34:19 +00:00
Evan Cheng 0f7cbe8370 Add PredicateOperand to all ARM instructions that have the condition field. 
llvm-svn: 37066
 2007-05-15 01:29:07 +00:00
Evan Cheng 9c031c0ddf Switch BCC, MOVCCr, etc. to PredicateOperand. 
llvm-svn: 36948
 2007-05-08 21:08:43 +00:00
Evan Cheng d37c23745f This is no longer needed after enabling the DAG combiner xform. 
llvm-svn: 36909
 2007-05-07 21:29:41 +00:00
Dale Johannesen 89200ce0f0 Evan's patch to avoid FPreg->intreg copy for cvt; store to mem 
llvm-svn: 36693
 2007-05-03 20:54:42 +00:00
Chris Lattner 1c1082133c match a reassociated form of fnmul. This implements CodeGen/ARM/fnmul.ll 
llvm-svn: 36660
 2007-05-03 00:32:00 +00:00
Evan Cheng 10043e215b ARM backend contribution from Apple. 
llvm-svn: 33353
 2007-01-19 07:51:42 +00:00