34f040a575
Now that all ARM subtargets use frame index scavenging, the Thumb1 requires*
...
functions are not needed.
llvm-svn: 84587
2009-10-20 01:32:47 +00:00
84f6235b6f
Enable post-pass frame index register scavenging for ARM and Thumb2
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llvm-svn: 84585
2009-10-20 01:26:58 +00:00
484d2e9491
lower ARM::MOVi32imm properly.
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llvm-svn: 84583
2009-10-20 01:11:37 +00:00
43c5589a7e
add support for external symbols. The mc instprinter can now handle
...
reasonable code like Codegen/ARM/2009-02-27-SpillerBug.ll, producing
identical output except for superior formatting of constant pool entries.
llvm-svn: 84582
2009-10-20 00:56:16 +00:00
1b06acbd70
get fancy: support basic block operands. Yay for jumps.
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llvm-svn: 84579
2009-10-20 00:52:47 +00:00
85ab670644
add supprort for the 'sbit' operand, MOVi apparently has one.
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llvm-svn: 84577
2009-10-20 00:46:11 +00:00
19c52201bd
add support for instruction predicates.
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llvm-svn: 84575
2009-10-20 00:42:49 +00:00
2f69ed8f4c
implement printSORegOperand, add lowering for the nasty and despicable MOVi2pieces :)
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llvm-svn: 84573
2009-10-20 00:40:56 +00:00
772b2f84eb
Refs: A8-598.
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Leave Inst{11-8}, which represents the starting byte index of the extracted
result in the concatenation of the operands and is left unspecified.
Patch by Johnny Chen.
llvm-svn: 84572
2009-10-20 00:38:19 +00:00
68f495caad
Add missing encoding bits to NLdSt class of instructions.
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Patch by Johnny Chen.
llvm-svn: 84570
2009-10-20 00:19:08 +00:00
0b4a59fc07
X86 should ignore implicit regs when lowering to MCInst also,
...
no functionality change.
llvm-svn: 84567
2009-10-19 23:35:57 +00:00
bd531262f8
handle addmode4 modifiers, fix a fixme in printRegisterList
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by ignoring all implicit regs when lowering.
llvm-svn: 84566
2009-10-19 23:31:43 +00:00
d99b6974b9
simplify by using the twine form of GetOrCreateSymbol
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llvm-svn: 84565
2009-10-19 23:05:23 +00:00
f5f263f1b4
Enable allocation of R3 in Thumb1
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llvm-svn: 84563
2009-10-19 22:57:03 +00:00
d91c11091d
use EmitLabel instead of text emission
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llvm-svn: 84562
2009-10-19 22:51:16 +00:00
86dfd73c38
add a twine version of MCContext::GetOrCreateSymbol.
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llvm-svn: 84561
2009-10-19 22:49:00 +00:00
186c6b0834
lower the ARM::CONSTPOOL_ENTRY pseudo op, giving us constant pool entries
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like:
@ BB#1:
.align 2
LCPI1_0:
.long L_.str-(LPC0+8)
Note that proper indentation of the label :)
llvm-svn: 84558
2009-10-19 22:33:05 +00:00
5a5a3bc5d4
Adjust the scavenge register spilling to allow the target to choose an
...
appropriate restore location for the spill as well as perform the actual
save and restore.
The Thumb1 target uses this to make sure R12 is not clobbered while a spilled
scavenger register is live there.
llvm-svn: 84554
2009-10-19 22:27:30 +00:00
add5749ac8
add MCInstLower support for lowering ARM::PICADD, a pseudo op for pic stuffola.
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llvm-svn: 84553
2009-10-19 22:23:04 +00:00
ef2979b1da
add register list and hacked up addrmode #4 support, we now get this:
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_main:
stmsp! sp!, {r7, lr}
mov r7, sp
sub sp, sp, #4
mov r0, #0
str r0, [sp]
ldr r0, LCPI1_0
bl _printf
ldr r0, [sp]
mov sp, r7
ldmsp! sp!, {r7, pc}
Note the unhappy ldm/stm because of modifiers being ignored.
llvm-svn: 84546
2009-10-19 22:09:23 +00:00
f264f8a21c
revert r84540, fixing build breakage I didn't see because of
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broken makefile deps :(
llvm-svn: 84544
2009-10-19 21:59:25 +00:00
7ddfdc4133
add addrmode2 support, getting us up to:
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_main:
stm ,
mov r7, sp
sub sp, sp, #4
mov r0, #0
str r0, [sp]
ldr r0, LCPI1_0
bl _printf
ldr r0, [sp]
mov sp, r7
ldm ,
llvm-svn: 84543
2009-10-19 21:57:05 +00:00
889a6217fa
add jump tables, constant pools and some trivial global
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lowering stuff. We can now compile hello world to:
_main:
stm ,
mov r7, sp
sub sp, sp, #4
mov r0, #0
str r0,
ldr r0,
bl _printf
ldr r0,
mov sp, r7
ldm ,
Almost looks like arm code :)
llvm-svn: 84542
2009-10-19 21:53:00 +00:00
e3796a0fee
pass mangler in as a reference instead of a pointer.
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llvm-svn: 84540
2009-10-19 21:45:31 +00:00
8bd9b9d3fa
reduce #includes
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llvm-svn: 84536
2009-10-19 21:23:15 +00:00
89d47205b5
add printing support for SOImm operands, getting us to:
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_main:
stm ,
mov r7, sp
sub sp, sp, #4
mov r0, #0
str r0,
llvm-svn: 84535
2009-10-19 21:21:39 +00:00
93e3ef6536
wire up some basic printOperand goodness, giving us stuff like this before
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we abort:
_main:
stm ,
mov r7, sp
sub sp, sp,
mov r0,
str r0,
llvm-svn: 84532
2009-10-19 20:59:55 +00:00
78393d79a0
add the files that go with the previous rev
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llvm-svn: 84531
2009-10-19 20:21:05 +00:00
71eb077c15
wire up skeletal support for having llc print instructions
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through mcinst lowering -> mcinstprinter, when llc is passed
the -enable-arm-mcinst-printer flag. Currently this
is very "aborty".
llvm-svn: 84530
2009-10-19 20:20:46 +00:00
296544e15f
wire up ARM's printMCInst method. Now llvm-mc should be able to produce
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"something" when printing MCInsts, it will just be missing all the
operand info.
llvm-svn: 84528
2009-10-19 19:59:05 +00:00
a290778859
stub out a minimal ARMInstPrinter.
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llvm-svn: 84527
2009-10-19 19:56:26 +00:00
5db7b6a5d4
remove strings from instructions who are never asmprinted.
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All of these "subreg32" modifier instructions are handled
explicitly by the MCInst lowering phase. If they got to
the asmprinter, they would explode. They should eventually
be replace with correct use of subregs.
llvm-svn: 84526
2009-10-19 19:51:42 +00:00
8d2e3a28d6
simplify code, reducing string thrashing.
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llvm-svn: 84521
2009-10-19 18:49:14 +00:00
3334deb19b
switch hidden gv stubs to use MachineModuleInfoMachO instead of a custom map.
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llvm-svn: 84520
2009-10-19 18:44:38 +00:00
6462adcd20
use MachineModuleInfoMachO for non-lazy gv stubs instead of a private map.
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llvm-svn: 84519
2009-10-19 18:38:33 +00:00
24fcb826bd
remove dead map
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llvm-svn: 84513
2009-10-19 18:11:25 +00:00
84a493ca21
don't bother trying to avoid emitting redundant constant pool alignment directives.
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llvm-svn: 84512
2009-10-19 18:08:02 +00:00
66ebfab3ab
remove accidental comment.
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llvm-svn: 84510
2009-10-19 18:03:41 +00:00
e6da1826e8
emit .subsections_via_symbols through MCStreamer instead of textually.
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llvm-svn: 84509
2009-10-19 18:03:08 +00:00
ee9399acaa
cleanup doFinalization -> EmitEndOfAsmFile.
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llvm-svn: 84508
2009-10-19 17:59:19 +00:00
5ca7b345b9
PR 5245 - The imediate size target flag was not set on 3A-prefixed SSSE3 instructions.
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llvm-svn: 84506
2009-10-19 17:31:16 +00:00
033f01c922
Fix PR5247, "lock addq" pattern (and other atomics), it DOES modify EFLAGS.
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LLC was scheduling compares before the adds causing wrong branches to be taken
in programs, resulting in misoptimized code wherever atomic adds where used.
llvm-svn: 84485
2009-10-19 11:00:58 +00:00
18df82a20c
Add support for matching shuffle patterns with palignr.
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llvm-svn: 84459
2009-10-19 02:17:23 +00:00
c436631a9c
Turn on post-alloc scheduling for x86.
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llvm-svn: 84431
2009-10-18 19:57:27 +00:00
936d87b39d
Oops. I forgot to change the tests first. Disable post-alloc scheduling.
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llvm-svn: 84425
2009-10-18 18:31:31 +00:00
0e9d9ca855
-Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed
...
stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot
move above a store of spill slot #2 .
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.
llvm-svn: 84424
2009-10-18 18:16:27 +00:00
0b8db2dab7
Only fixed stack objects and spill slots should be get FixedStack PseudoSourceValue.
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llvm-svn: 84411
2009-10-18 06:27:36 +00:00
4729191bb2
Distinquish stack slots from other stack objects. They (and fixed objects) get FixedStack PseudoSourceValues.
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llvm-svn: 84326
2009-10-17 09:20:14 +00:00
8759585aba
Revert 84315 for now. Re-thinking the patch.
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llvm-svn: 84321
2009-10-17 07:53:04 +00:00
0818d87ed1
Rename getFixedStack to getStackObject. The stack objects represented are not
...
necessarily fixed. Only those will negative frame indices are "fixed."
llvm-svn: 84315
2009-10-17 06:22:26 +00:00
Jim Grosbach