9613a09e5c
Remove fixup_arm_thumb_ldst. The code was never calling the "fixup" stuff for
...
it. I.e., it was always an immediate value.
llvm-svn: 121932
2010-12-16 00:50:33 +00:00
637813a258
Add tSpill and tRestore to the opcodes to replace with tSTRi and tLDRi
...
respectively.
It may be a bug that these opcodes are getting this far into machine code
generation.
llvm-svn: 121931
2010-12-16 00:49:54 +00:00
f5b17c32d2
Add encodings for Thumb1 Spill and Restore pseudos.
...
llvm-svn: 121929
2010-12-16 00:38:41 +00:00
2c9d342f04
Enable TBAA by default.
...
llvm-svn: 121923
2010-12-15 23:58:44 +00:00
4467aa5294
Preserve TBAA tags when doing load PRE.
...
llvm-svn: 121921
2010-12-15 23:53:55 +00:00
bfef309d11
Thumb1 had two patterns for the same load-from-constant-pool instruction.
...
Canonicalize on tLDRpci and remove tLDRcp.
llvm-svn: 121920
2010-12-15 23:52:36 +00:00
347f4c32e8
Don't handle -arm-long-calls in fast isel for now.
...
llvm-svn: 121919
2010-12-15 23:47:29 +00:00
e7601e97e1
Start using SplitKit and MachineLoopRanges in RegAllocGreedy in preparation of
...
live range splitting around loops guided by register pressure.
So far, trySplit() simply prints a lot of debug output.
llvm-svn: 121918
2010-12-15 23:46:13 +00:00
5e97781386
Add MachineLoopRanges analysis.
...
A MachineLoopRange contains the intervals of slot indexes covered by the blocks
in a loop. This representation of the loop blocks is more efficient to compare
against interfering registers during register coalescing.
llvm-svn: 121917
2010-12-15 23:41:23 +00:00
7d3bde98f1
If we're changing the frame register to a physical register other than SP, we
...
need to use tLDRi and tSTRi instead of tLDRspi and tSTRspi respectively.
llvm-svn: 121915
2010-12-15 23:32:27 +00:00
6217ecd634
Whitespace cleanups.
...
llvm-svn: 121914
2010-12-15 23:31:24 +00:00
f991d4f587
Better fix for opt build
...
llvm-svn: 121910
2010-12-15 23:14:45 +00:00
be69d8e2f3
Only rr forms of ADD*_DB are commutable.
...
llvm-svn: 121908
2010-12-15 22:57:36 +00:00
1cf8881299
Add an InstCombine transform to recognize instances of manual overflow-safe addition
...
(performing the addition in a wider type and explicitly checking for overflow), and
fold them down to intrinsics. This currently only supports signed-addition, but could
be generalized if someone works out the magic constant formulas for other operations.
Fixes <rdar://problem/8558713>.
llvm-svn: 121905
2010-12-15 22:32:38 +00:00
15f96baa01
Fix opt -Werror build
...
llvm-svn: 121904
2010-12-15 22:21:20 +00:00
b7ff5a0f20
Teach machine cse to commute instructions.
...
llvm-svn: 121903
2010-12-15 22:16:21 +00:00
fa27a8621c
Add Neon VCVT instructions for f32 <-> f16 conversions.
...
Clang is now providing intrinsics for these and so we need to support them
in the backend. Radar 8068427.
llvm-svn: 121902
2010-12-15 22:14:12 +00:00
05b18f143f
Reapply r121886, and also update DecomposeGEPExpression to keep
...
it in sync.
llvm-svn: 121895
2010-12-15 20:49:55 +00:00
d02b65982e
Revert r121886. DecomposeGEPExpression needs to be kept
...
in sync.
llvm-svn: 121892
2010-12-15 20:39:25 +00:00
0c558b2080
Lower the MBlaze target specific calling conventions for "interrupt_handler"
...
and "save_volatiles" correctly. This completes the custom calling convention
functionality changes for the MBlaze backend that were started in 121888.
llvm-svn: 121891
2010-12-15 20:27:28 +00:00
949ab7889c
Strengthen GetUnderlyingObject using InstructionSimplify.
...
While LLVM's main design is that analysis code shouldn't
go out of its way to understand code which hasn't been
InstCombined, analysis utility routines like this can
find themselves being called in the middle of transform
passes when instcombine hasn't had a chance to run.
llvm-svn: 121886
2010-12-15 20:10:26 +00:00
a4fcd2418d
Move Value::getUnderlyingObject to be a standalone
...
function so that it can live in Analysis instead of
VMCore.
llvm-svn: 121885
2010-12-15 20:02:24 +00:00
fdb174b6ef
Add some special purpose register definitions to the MBlaze backend and cleanup some old, unused floating point register definitions.
...
llvm-svn: 121882
2010-12-15 19:35:36 +00:00
c8fa5fcc42
Fix typo in r121875.
...
llvm-svn: 121880
2010-12-15 19:24:24 +00:00
23477c2ee5
Tweak a few pseudo-inst pattern base classes.
...
llvm-svn: 121878
2010-12-15 19:03:16 +00:00
11678bd299
Clean up some of LVI:
...
* mergeIn now uses constant folding for constants that are provably not-equal.
* sink some sanity checks from the get*() methods into the mark*() methods, to ensure that we never have a constant/notconstant ConstantInt
* some textual cleanups, whitespace changes, removing "else" after return, that sort of thing.
llvm-svn: 121877
2010-12-15 18:57:18 +00:00
d42257ceef
The new t2LEApcrel* pseudo instructions need the size specified.
...
rdar://8768390
llvm-svn: 121876
2010-12-15 18:48:45 +00:00
622ad5170b
Implement cleanups suggested by Daniel.
...
llvm-svn: 121875
2010-12-15 18:48:27 +00:00
1066ef6b24
Fix build.
...
llvm-svn: 121872
2010-12-15 18:07:48 +00:00
28e769cc54
Detect and enumerate bypass loops.
...
Bypass loops have the current live range live through, but contain no uses or
defs. Splitting around a bypass loop can free registers for other uses inside
the loop by spilling the split range.
llvm-svn: 121871
2010-12-15 17:49:52 +00:00
4391f34aba
Separate SplitAnalysis::getSplitLoops().
...
This method returns the set of loops with uses that are candidates for
splitting.
llvm-svn: 121870
2010-12-15 17:41:19 +00:00
0a2c416894
Move Sub simplifications and additional Add simplifications out of
...
instcombine and into InstructionSimplify.
llvm-svn: 121861
2010-12-15 14:07:39 +00:00
019a418808
If we detect that the instruction we are simplifying is unreachable, arrange for
...
it to be replaced by undef rather than not replaced at all, the idea being that
this may reduce the amount of work done by whoever called InstructionSimplify.
llvm-svn: 121860
2010-12-15 11:02:22 +00:00
3d1803495e
Teach jump threading to "look through" a select when the branch direction of a terminator depends on it.
...
When it sees a promising select it now tries to figure out whether the condition of the select is known in any of the predecessors and if so it maps the operands appropriately.
llvm-svn: 121859
2010-12-15 09:51:20 +00:00
03e7576dee
Add fixups for Thumb LDR/STR instructions.
...
llvm-svn: 121858
2010-12-15 08:51:02 +00:00
844f6b6cfb
Relax alignment fragments.
...
With this we don't need the EffectiveSize field anymore. Without that field
LayoutFragment only updates offsets and we don't need to invalidate the
current fragment when it is relaxed (only the ones following it).
This is also a very small improvement in the accuracy of the layout info as
we now use the after relaxation size immediately.
llvm-svn: 121857
2010-12-15 08:45:53 +00:00
8911d03504
Patch by David Meyer to avoid a O(N^2) behaviour when relaxing fragments.
...
Since we now don't update addresses so early, we might relax a bit more than
we need to. This is simillar to the issue in PR8467.
llvm-svn: 121856
2010-12-15 07:39:29 +00:00
5174921b5b
add another overflow idiom
...
llvm-svn: 121854
2010-12-15 07:28:58 +00:00
2e33985300
add a note about overflow idiom recognition.
...
llvm-svn: 121853
2010-12-15 07:25:55 +00:00
f80f18a11a
Generalize an assert.
...
llvm-svn: 121851
2010-12-15 07:12:24 +00:00
27ecda1efd
add a shift/imul missed optimization
...
llvm-svn: 121850
2010-12-15 07:10:43 +00:00
aded09f27f
add a note about a SPEC hack that gcc mainline does.
...
llvm-svn: 121849
2010-12-15 06:38:24 +00:00
15090e1eb0
take care of some todos, transforming [us]mul_lohi into
...
a wider mul if the wider mul is legal.
llvm-svn: 121848
2010-12-15 06:04:19 +00:00
b86dceea1b
when transforming a MULHS into a wider MUL, there is no need to SRA the
...
result, the top bits are truncated off anyway, just use SRL.
llvm-svn: 121846
2010-12-15 05:51:39 +00:00
e893e2601e
make qsort predicate more conformant by returning 0 for equal values.
...
llvm-svn: 121838
2010-12-15 04:52:41 +00:00
832a5daab5
Reapply r121808 now that the missing patterns have been supplied.
...
llvm-svn: 121820
2010-12-15 01:03:19 +00:00
1171e9e81d
Add some missing patterns now that tLDRB and tLDRH are split into reg and
...
immediate versions.
llvm-svn: 121819
2010-12-15 00:58:57 +00:00
35609d97ae
Fix PR8790, another instance where unreachable code can cause instruction simplification to fail,
...
this case involve a select that simplifies to itself.
llvm-svn: 121817
2010-12-15 00:55:35 +00:00
15c85c916f
Cleanup trailing whitespace.
...
llvm-svn: 121816
2010-12-15 00:52:44 +00:00
20480d26e9
Revert r121808 until I can fix the build.
...
llvm-svn: 121815
2010-12-15 00:04:00 +00:00
eda5177ca6
thumb adr fixup needs alignment just like the t2 version.
...
llvm-svn: 121812
2010-12-14 23:47:35 +00:00
5ab38b59e6
Comments and cleaning.
...
llvm-svn: 121809
2010-12-14 23:42:48 +00:00
00adcd6ed9
Make the ISel selections for LDR/STR the same as before the LDRr/LDRi split. In
...
particular, we want
ldr r2, [r3]
to be equivalent to
ldr r2, [r3, #0 ]
and not
ldr r2, [r3, r0]
llvm-svn: 121808
2010-12-14 23:40:49 +00:00
0b7ca3a6a7
Simplify RegAllocGreedy's use of register aliases.
...
llvm-svn: 121807
2010-12-14 23:38:19 +00:00
47b93401d8
Simplify CCState's use of register aliases.
...
llvm-svn: 121806
2010-12-14 23:28:01 +00:00
be1c8d3a82
Simplify AggressiveAntiDepBreaker's use of register aliases.
...
llvm-svn: 121805
2010-12-14 23:23:15 +00:00
6a5bf7782a
Simplyfy RegAllocBasic by using getOverlaps instead of getAliasSet.
...
llvm-svn: 121801
2010-12-14 23:10:48 +00:00
509dc2a700
Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755
...
llvm-svn: 121798
2010-12-14 22:28:03 +00:00
6ea3053824
Fix comment.
...
llvm-svn: 121797
2010-12-14 22:26:49 +00:00
ce4f87b3ba
Multiclassify the LDR/STR encoding patterns. The only functionality difference
...
is the addition of the FoldableAsLoad & Rematerializable flags to some of the
load instructions. ARM has these flags set for them.
llvm-svn: 121794
2010-12-14 22:10:49 +00:00
19dc77cec6
Fix a minor bug in two-address pass. It was missing a commute opportunity.
...
regB = move RCX
regA = op regB, regC
RAX = move regA
where both regB and regC are killed. If regB is constrainted to non-compatible
physical registers but regC is not constrainted at all, then it's better to
commute the instruction.
movl %edi, %eax
shlq $32, %rcx
leaq (%rcx,%rax), %rax
=>
movl %edi, %eax
shlq $32, %rcx
orq %rcx, %rax
rdar://8762995
llvm-svn: 121793
2010-12-14 21:34:53 +00:00
d96bd53d04
trailing whitespace
...
llvm-svn: 121792
2010-12-14 21:28:29 +00:00
86a05d0bed
Move debugging code entirely within DEBUG(). Silences an unused variable
...
warning in the opt build.
llvm-svn: 121791
2010-12-14 21:14:55 +00:00
8c1fabe367
Refactor a bit for legibility.
...
llvm-svn: 121790
2010-12-14 21:10:47 +00:00
2fc6561102
trailing whitespace.
...
llvm-svn: 121789
2010-12-14 20:46:39 +00:00
96254146cf
Make sure to propagate the predicate operands for LEApcrel to ADR.
...
llvm-svn: 121788
2010-12-14 20:45:47 +00:00
f636a64bfe
Fix a small bug (typo?) in the fixup for Thumb1 CBZ/CBNZ instructions.
...
llvm-svn: 121784
2010-12-14 19:42:53 +00:00
5c3ad0d51e
Add LiveIntervalUnion print methods, RegAllocGreedy::trySplit debug spew.
...
llvm-svn: 121783
2010-12-14 19:38:49 +00:00
d5e38383e0
Use TRI::printReg instead of AbstractRegisterDescription when printing
...
LiveIntervalUnions.
llvm-svn: 121781
2010-12-14 18:53:47 +00:00
2dd1ee5fd5
Add TargetRegisterInfo::printReg() to pretty-print registers.
...
llvm-svn: 121780
2010-12-14 18:53:39 +00:00
41955ff958
ARM Fixups relative to thumb functions need to have the low bit of the value
...
set for interworking to work properly. rdar://8755956
llvm-svn: 121778
2010-12-14 18:46:57 +00:00
e7ee72087e
Q.seenAllInterferences() must be called after Q.collectInterferingVRegs().
...
llvm-svn: 121774
2010-12-14 17:47:36 +00:00
a9b9300bb8
MC/ARM: Fix-up fixup offset for fixup_arm_branch target specific fixup.
...
llvm-svn: 121772
2010-12-14 17:37:16 +00:00
e34793e960
Trailing whitespace
...
llvm-svn: 121769
2010-12-14 16:25:15 +00:00
6dd0c07622
Use the integer scheduling intrinsic for integer loads and stores.
...
llvm-svn: 121765
2010-12-14 12:33:05 +00:00
7499b452c1
- Insert new instructions before DomBlock's terminator,
...
which is simpler than finding a place to insert in BB.
- Don't perform the 'if condition hoisting' xform on certain
i1 PHIs, as it interferes with switch formation.
This re-fixes "example 7", without breaking the world hopefully.
llvm-svn: 121764
2010-12-14 08:46:09 +00:00
335f0e4ad4
fix two significant issues with FoldTwoEntryPHINode:
...
first, it can kick in on blocks whose conditions have been
folded to a constant, even though one of the edges will be
trivially folded.
second, it doesn't clean up the "if diamond" that it just
eliminated away. This is a problem because other simplifycfg
xforms kick in depending on the order of block visitation,
causing pointless work.
llvm-svn: 121762
2010-12-14 08:01:53 +00:00
dc20a7d38c
remove the instsimplify logic I added in r121754. It is apparently
...
breaking the selfhost builds, though I can't fathom how.
llvm-svn: 121761
2010-12-14 07:53:03 +00:00
9ac168d0ab
clean up logic, convert std::set to SmallPtrSet, handle the case
...
when all 2-entry phis are simplified away.
llvm-svn: 121760
2010-12-14 07:41:39 +00:00
9fd838d31b
tidy up a bit, move DEBUG down to when we commit to doing the transform so we
...
don't print it unless the xform happens.
llvm-svn: 121758
2010-12-14 07:23:10 +00:00
b42d293faa
use SimplifyInstruction instead of reimplementing part of it.
...
llvm-svn: 121757
2010-12-14 07:20:29 +00:00
fb73de482c
simplify GetIfCondition by using getSinglePredecessor.
...
llvm-svn: 121756
2010-12-14 07:15:21 +00:00
0f4d67bd88
use AddPredecessorToBlock in 3 places instead of a manual loop.
...
llvm-svn: 121755
2010-12-14 07:09:42 +00:00
a07cc6f4fd
make FoldTwoEntryPHINode use instsimplify a bit, make
...
GetIfCondition faster by avoiding pred_iterator. No
really interesting change.
llvm-svn: 121754
2010-12-14 07:00:00 +00:00
afd2a8cfbb
remove the dead (and terrible) llvm::RemoveSuccessor function.
...
llvm-svn: 121753
2010-12-14 06:51:55 +00:00
d7beca3782
improve DEBUG's a bit, switch to eraseFromParent() to simplify
...
code a bit, switch from constant folding to instsimplify.
llvm-svn: 121751
2010-12-14 06:17:25 +00:00
5a9d59d918
reapply my recent change that disables a piece of the switch formation
...
work, but fixes 400.perlbmk.
llvm-svn: 121749
2010-12-14 05:57:30 +00:00
092a7bdf9f
The tLDR et al instructions were emitting either a reg/reg or reg/imm
...
instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.
The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.
There are some obvious cleanups here, which will happen shortly.
llvm-svn: 121747
2010-12-14 03:36:38 +00:00
c177813755
bfi A, (and B, C1), C2) -> bfi A, B, C2 iff C1 & C2 == C1. rdar://8458663
...
llvm-svn: 121746
2010-12-14 03:22:07 +00:00
eba9095df2
Remove unused vector.
...
llvm-svn: 121741
2010-12-14 00:58:47 +00:00
903b6d3261
Try reassigning all virtual register interferences, not just those with lower
...
spill weight. Filter out fixed registers instead.
Add support for reassigning an interference that was assigned to an alias.
llvm-svn: 121737
2010-12-14 00:37:49 +00:00
3d7b8066aa
Add stub for RAGreedy::trySplit.
...
llvm-svn: 121736
2010-12-14 00:37:44 +00:00
6d375e5637
Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering much later, which makes the entire
...
process cleaner.
llvm-svn: 121735
2010-12-14 00:36:49 +00:00
3e5648896e
Fix recent buildbot breakage by pulling SimplifyCFG back to its state as of r121694, the most recent state
...
where I'm confident there were no crashes or miscompilations. XFAIL the test added since then for now.
llvm-svn: 121733
2010-12-13 23:49:28 +00:00
0e909c5f9c
First cut of ARM/MC/ELF PIC relocations.
...
Test has fixme, to move to .s -> .o test when AsmParser works better.
llvm-svn: 121732
2010-12-13 23:16:07 +00:00
651eaa02b8
Remove the rest of the *_sfp Neon instruction patterns.
...
Use the same COPY_TO_REGCLASS approach as for the 2-register *_sfp instructions.
This change made a big difference in the code generated for the
CodeGen/Thumb2/cross-rc-coalescing-2.ll test: The coalescer is still doing
a fine job, but some instructions that were previously moved outside the loop
are not moved now. It's using fewer VFP registers now, which is generally
a good thing, so I think the estimates for register pressure changed and that
affected the LICM behavior. Since that isn't obviously wrong, I've just
changed the test file. This completes the work for Radar 8711675.
llvm-svn: 121730
2010-12-13 23:02:37 +00:00
aae0862172
Simplify N2VSPat, removing some unnecessary type arguments.
...
llvm-svn: 121729
2010-12-13 23:02:31 +00:00
a6e5d5694a
temporarily disable part of my previous patch, which causes an iterator invalidation issue, causing a crash on some versions of perlbmk.
...
llvm-svn: 121728
2010-12-13 23:02:19 +00:00
3cb55a1d23
Update a comment.
...
llvm-svn: 121727
2010-12-13 22:53:18 +00:00
9a4d42855d
Revert r121721, which broke buildbots.
...
llvm-svn: 121726
2010-12-13 22:51:08 +00:00
Bill Wendling