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23 Commits

Author SHA1 Message Date
Yunzhong Gao 4467f33e3c Fixing Intel format of the vshufpd instruction. 
Phabricator code review is located at: http://llvm-reviews.chandlerc.com/D1759

llvm-svn: 191481
 2013-09-27 01:44:23 +00:00
David Majnemer aa34d79ab5 [ms-inline asm] Support offsets after segment registers 
Summary: MASM let's you do stuff like 'MOV FS:20, EAX' and 'MOV EAX, FS:20'

Reviewers: craig.topper, rnk

Reviewed By: rnk

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D1470

llvm-svn: 189407
 2013-08-27 21:56:17 +00:00
Craig Topper a7316c2e64 Add test cases for the various instruction alias and Intel syntax fixes that have gone in lately. 
llvm-svn: 187188
 2013-07-26 05:39:33 +00:00
Benjamin Kramer af6c3b7002 X86: Make the cmov aliases work with intel syntax too. 
llvm-svn: 183907
 2013-06-13 15:45:24 +00:00
Chad Rosier edb1dc8498 [x86AsmParser] It's valid to stop parsing an operand at an immediate. 
rdar://13854369 and PR15944

llvm-svn: 181564
 2013-05-09 23:48:53 +00:00
Chad Rosier 53e5768351 Add test case for PR15779, which has previously been fixed. 
llvm-svn: 180058
 2013-04-22 22:30:01 +00:00
Chad Rosier f8fb2bc2f3 [ms-inline asm] Apply the condition code mnemonic aliases to both the Intel and 
AT&T dialect.  Test case for r179804 as well.
rdar://13674398 and PR13340.

llvm-svn: 179813
 2013-04-18 23:16:12 +00:00
Chad Rosier 3124627aa8 [ms-inline asm] Add support for the minus unary operator. Previously, we were 
unable to handle cases such as __asm mov eax, 8*-8.

This patch also attempts to simplify the state machine.  Further, the error
reporting has been improved.  Test cases included, but more will be added to
the clang side shortly.
rdar://13668445

llvm-svn: 179719
 2013-04-17 21:01:45 +00:00
Chad Rosier 4a7005e976 [ms-inline asm] Add support for numeric displacement expressions in bracketed 
memory operands.

Essentially, this layers an infix calculator on top of the parsing state
machine.  The scale on the index register is still expected to be an immediate

 __asm mov eax, [eax + ebx*4]

and will not work with more complex expressions.  For example,

 __asm mov eax, [eax + ebx*(2*2)]

The plus and minus binary operators assume the numeric value of a register is
zero so as to not change the displacement.  Register operands should never
be an operand for a multiply or divide operation; the scale*indexreg
expression is always replaced with a zero on the operand stack to prevent
such a case.
rdar://13521380

llvm-svn: 178881
 2013-04-05 16:28:55 +00:00
Chad Rosier 5c118fd2ec [ms-inline asm] Extend support for parsing Intel bracketed memory operands that 
have an arbitrary ordering of the base register, index register and displacement.
rdar://12527141

llvm-svn: 172484
 2013-01-14 22:31:35 +00:00
Craig Topper 01deb5f2df Make x86 asm parser to check for xmm vs ymm for index register in gather instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas. 
llvm-svn: 160420
 2012-07-18 04:11:12 +00:00
Devang Patel 63fe5697f4 Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320] 
llvm-svn: 149142
 2012-01-27 19:48:28 +00:00
Devang Patel cf893a437e Intel syntax: Robustify parsing of memory operand's displacement experssion. 
llvm-svn: 148737
 2012-01-23 22:35:25 +00:00
Devang Patel e660fdd953 Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI] 
llvm-svn: 148721
 2012-01-23 20:20:06 +00:00
Devang Patel 880bc1644b Intel syntax: Parse segment registers. 
llvm-svn: 148712
 2012-01-23 18:31:58 +00:00
Devang Patel ce6a2ca8c8 Intel syntax: Robustify register parsing. 
llvm-svn: 148591
 2012-01-20 22:32:05 +00:00
Devang Patel de47cced25 Process instructions after match to select alternative encoding which may be more desirable. 
llvm-svn: 148431
 2012-01-18 22:42:29 +00:00
Devang Patel c9ed518792 Intel syntax: Fix parser match class to check memory operand size. 
llvm-svn: 148338
 2012-01-17 21:48:03 +00:00
Devang Patel a7143b6a2b Intel syntax: Parse "BYTE PTR [RDX + RCX]" 
llvm-svn: 148334
 2012-01-17 21:25:10 +00:00
Devang Patel 8b39be79ad Intel syntax: Do not unncessarily create plus expression for memory operand displacement. 
llvm-svn: 148321
 2012-01-17 19:08:07 +00:00
Devang Patel a77c03be54 Intel syntax: Ignore mnemonic aliases. 
llvm-svn: 148316
 2012-01-17 18:30:45 +00:00
Devang Patel 41b9ddeb7a Intel syntax: Robustify memory operand parsing. 
llvm-svn: 148312
 2012-01-17 18:00:18 +00:00
Devang Patel 5d85276e30 Add new test. 
llvm-svn: 148128
 2012-01-13 18:45:31 +00:00