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4255 Commits

Author SHA1 Message Date
Chris Lattner 0dcdd83c0e This was meant to go in 
llvm-svn: 24900
 2005-12-21 07:50:26 +00:00
Chris Lattner f431ad4477 Rewrite FP stackifier support in the X86InstrInfo.td file, splitting patterns 
that were overloaded to work before and after the stackifier runs.  With the
new clean world, it is possible to write patterns for these instructions: woo!

This also adds a few simple patterns here and there, though there are a lot
still missing.  These should be easy to add though. :)

See the comments under "Floating Point Stack Support" for more details on
the new world order.

This patch as absolutely no effect on the generated code, woo!

llvm-svn: 24899
 2005-12-21 07:47:04 +00:00
Chris Lattner 988827a482 Wrap some long lines: no functionality change 
llvm-svn: 24898
 2005-12-21 05:34:58 +00:00
Chris Lattner 72575d882b remove dead code 
llvm-svn: 24896
 2005-12-21 05:27:51 +00:00
Evan Cheng a2f308fc3e Remove ISD::RET select code. Now tblgen'd. 
llvm-svn: 24889
 2005-12-21 02:41:57 +00:00
Evan Cheng a74ce62746 * Added lowering hook for external weak global address. It inserts a load 
for Darwin.
* Added lowering hook for ISD::RET. It inserts CopyToRegs for the return
  value (or store / fld / copy to ST(0) for floating point value). This
  eliminate the need to write C++ code to handle RET with variable number
  of operands.

llvm-svn: 24888
 2005-12-21 02:39:21 +00:00
Evan Cheng 5c0b4df483 SSE2 floating point load / store patterns. SSE2 fp to int conversion patterns. 
llvm-svn: 24886
 2005-12-20 22:59:51 +00:00
Evan Cheng 82285c55aa Flip the meaning of FPContractions to reflect Requires<[]> change. 
llvm-svn: 24884
 2005-12-20 20:08:53 +00:00
Chris Lattner fc94dff7dc Run lower-switch after lower-invoke. 
Only run lower-allocations and lower-select for the simple isel

llvm-svn: 24881
 2005-12-20 08:00:11 +00:00
Chris Lattner 10c7f67d78 Reserve G1 for frame offset stuff and use it to handle large stack frames. 
For example, instead of emitting this:

test:
        save -40112, %o6, %o6   ;; imm too large
        add %i6, -40016, %o0    ;; imm too large
        call caller
        nop
        restore %g0, %g0, %g0
        retl
        nop

emit this:

test:
        sethi 4194264, %g1
        or %g1, 848, %g1
        save %o6, %g1, %o6
        sethi 4194264, %g1
        add %g1, %i6, %g1
        add %i1, 944, %o0
        call caller
        nop
        restore %g0, %g0, %g0
        retl
        nop

which doesn't cause the assembler to barf.

llvm-svn: 24880
 2005-12-20 07:56:31 +00:00
Evan Cheng 5815a6e455 Added X86 readport patterns. 
llvm-svn: 24879
 2005-12-20 07:38:38 +00:00
Evan Cheng 6af02635a7 Added a hook to print out names of target specific DAG nodes. 
llvm-svn: 24877
 2005-12-20 06:22:03 +00:00
Nate Begeman b11b8e44fa Pattern-match return. Includes gross hack! 
llvm-svn: 24874
 2005-12-20 00:26:01 +00:00
Nate Begeman c126397a69 Fix a couple of the FIXMEs, thanks to suggestion from Chris. This allows 
us to load and store vectors directly at a pointer (offset of zero) by
using r0 as the base register.  This also requires some asm printer work
to satisfy the darwin assembler.

For
void %foo(<4 x float> * %a) {
entry:
  %tmp1 = load <4 x float> * %a;
  %tmp2 = add <4 x float> %tmp1, %tmp1
  store <4 x float> %tmp2, <4 x float> *%a
  ret void
}

We now produce:
_foo:
        lvx v0, 0, r3
        vaddfp v0, v0, v0
        stvx v0, 0, r3
        blr

Instead of:
_foo:
        li r2, 0
        lvx v0, r2, r3
        vaddfp v0, v0, v0
        stvx v0, r2, r3
        blr

llvm-svn: 24872
 2005-12-19 23:40:42 +00:00
Nate Begeman 8e6a8af205 Convert load/store over to being pattern matched 
llvm-svn: 24871
 2005-12-19 23:25:09 +00:00
Evan Cheng 6fc31046aa X86 conditional branch support. 
llvm-svn: 24870
 2005-12-19 23:12:38 +00:00
Evan Cheng 1d9b671de0 It's essential we clear CodeGenMap after isel every basic block! 
llvm-svn: 24867
 2005-12-19 22:36:02 +00:00
Chris Lattner 7767a654b0 Fix pifft by correcting the case when a i64/f64 straddles O5 and memory: 
we were storing into [FP+88] instead of [FP+92].
Improve codegen by emitting [FP+92], instead of emitting a copy of FP into
another GPR which wouldn't be coallesced because FP isn't register allocated.

llvm-svn: 24859
 2005-12-19 07:57:53 +00:00
Chris Lattner 631c9df853 don't emit 'add %o6, 0, %o6' instructions 
llvm-svn: 24857
 2005-12-19 02:51:12 +00:00
Chris Lattner 5b9c9f9d36 Fix calls to functions returning i64 
llvm-svn: 24856
 2005-12-19 02:15:51 +00:00
Chris Lattner 655fac2c95 Correct bool truncstore operand order 
llvm-svn: 24855
 2005-12-19 02:06:50 +00:00
Chris Lattner 2c792ccc62 add the other bool zextload as well 
llvm-svn: 24854
 2005-12-19 01:44:58 +00:00
Chris Lattner 766170c6ee implement zextload bool 
llvm-svn: 24853
 2005-12-19 01:43:04 +00:00
Chris Lattner 9be456300e mark some unsupported ops as unsupported 
llvm-svn: 24852
 2005-12-19 01:39:40 +00:00
Chris Lattner e59941810a Fix syntax for indirect calls. This fixes Olden/mst 
llvm-svn: 24850
 2005-12-19 01:22:53 +00:00
Chris Lattner bead785656 Keep stack frames 8-byte aligned. This fixes olden/voronoi 
llvm-svn: 24849
 2005-12-19 01:15:13 +00:00
Chris Lattner 9078c84654 apparently rdy isn't actually a psuedo instruction. Use rd %y 
llvm-svn: 24848
 2005-12-19 00:53:02 +00:00
Chris Lattner d2e885e321 add fneg/fabs support for doubles 
llvm-svn: 24847
 2005-12-19 00:50:12 +00:00
Chris Lattner 14ee61ef00 Various cleanups to this pass, no functionality change 
llvm-svn: 24846
 2005-12-19 00:46:20 +00:00
Chris Lattner d2a07eebcd add bool truncstores 
llvm-svn: 24845
 2005-12-19 00:19:21 +00:00
Chris Lattner 15bd5ea92f Elimiante SP and FP, which weren't members of the IntRegs register class 
llvm-svn: 24844
 2005-12-19 00:06:52 +00:00
Chris Lattner f5f80cb947 The sun assembler only supports .xword in V9 mode. 
llvm-svn: 24842
 2005-12-18 23:36:45 +00:00
Chris Lattner 1ac15547d6 Configure the asmwriter to allow constant pools to be printed correctly 
llvm-svn: 24841
 2005-12-18 23:35:05 +00:00
Chris Lattner 030672f16b add support for integer extloads 
llvm-svn: 24840
 2005-12-18 23:18:37 +00:00
Chris Lattner c70ed7721b Add support for undef 
llvm-svn: 24839
 2005-12-18 23:10:57 +00:00
Chris Lattner 4c3c3ac218 Add support for calls to external symbols 
llvm-svn: 24838
 2005-12-18 23:07:11 +00:00
Chris Lattner 388f3043b0 we have no memcpy 
llvm-svn: 24837
 2005-12-18 23:00:27 +00:00
Chris Lattner c65cd5a03e Fix a crash on a call with no arguments 
llvm-svn: 24836
 2005-12-18 22:57:47 +00:00
Chris Lattner 2f5fb6a720 This is handled by the autogen'd code 
llvm-svn: 24834
 2005-12-18 21:06:11 +00:00
Chris Lattner 1958690ff2 Change return lowering so that we can autogen the matching code. 
llvm-svn: 24832
 2005-12-18 21:03:04 +00:00
Chris Lattner 02e9904ee5 Implement Calls for V8. This would be completely autogenerated except for 
a small bug in tblgen.  When that is fixed, we can remove the ISD::Call case
in Select.

llvm-svn: 24830
 2005-12-18 15:55:15 +00:00
Chris Lattner a0be18c9a4 Implement the full V8 ABI for incoming arguments. 
llvm-svn: 24825
 2005-12-18 13:33:06 +00:00
Chris Lattner 8d1db078cb Push ops list, asm string, and pattern all the way up to InstV8. Move the 
InstV8 class to the InstrFormats file where it belongs.

llvm-svn: 24824
 2005-12-18 08:21:00 +00:00
Chris Lattner 7cee2c9a5b Give V8 select_cc, in the spirit of the PPC backend 
llvm-svn: 24823
 2005-12-18 08:13:54 +00:00
Chris Lattner 9de2958138 remove some unused instructions 
llvm-svn: 24822
 2005-12-18 07:15:17 +00:00
Chris Lattner a9f0d108b1 V8 doesn't have FP extload 
llvm-svn: 24821
 2005-12-18 07:13:32 +00:00
Chris Lattner d6806875d0 simplifications, fix typo 
llvm-svn: 24820
 2005-12-18 07:09:06 +00:00
Chris Lattner c5609aab11 add a node, for completeness 
llvm-svn: 24819
 2005-12-18 07:05:21 +00:00
Chris Lattner 4492b1b7a0 Add frameindex support 
Add support for copying (e.g. returning) doubles
Add support for F<->I instructions

llvm-svn: 24818
 2005-12-18 06:59:57 +00:00
Chris Lattner 9dcfe37e76 Tighten up some checks 
llvm-svn: 24817
 2005-12-18 06:40:34 +00:00
Nate Begeman 53c1f75090 Since extload can also be used by FP, split STDIntExtLoad into two parts, 
one for use with extload, one for use with sextload and zextload, which
are integer only.

llvm-svn: 24814
 2005-12-18 02:48:48 +00:00
Chris Lattner 5580e69df6 Add constant pool support, including folding into addresses. 
Pretty print addresses a bit, to not print [%r1+%g0]: just print [%r1]

llvm-svn: 24813
 2005-12-18 02:37:35 +00:00
Chris Lattner 726075fdf8 Teach the addressing mode stuff to fold "%lo" into 'ri' addressing modes, 
allowing us to compile this:

to this:

%G1 = external global int
%G2 = external global int
void %test() {
        %X = load int* %G1
        store int %X, int* %G2
        ret void
}

test:
        save -96, %sp, %sp
        sethi %hi(G1), %l0
        ld [%l0+%lo(G1)], %l0
        sethi %hi(G2), %l1
        st %l0, [%l1+%lo(G2)]
        restore %g0, %g0, %g0
        retl
        nop

instead of this:

test:
        save -96, %sp, %sp
        sethi %hi(G1), %l0
        or %g0, %lo(G1), %l1
        ld [%l1+%l0], %l0
        sethi %hi(G2), %l1
        or %g0, %lo(G2), %l2
        st %l0, [%l2+%l1]
        restore %g0, %g0, %g0
        retl
        nop

llvm-svn: 24812
 2005-12-18 02:27:00 +00:00
Chris Lattner a983c3df1c Add initial support for global variables, and fix a bug in addr mode selection 
where we didn't select the operands.

llvm-svn: 24811
 2005-12-18 02:10:39 +00:00
Chris Lattner a49b652a62 Claiming that branch targets are registers is not very wholesome. Change them 
to be basic blocks.  Also, add uncond branches.

llvm-svn: 24810
 2005-12-18 01:46:58 +00:00
Chris Lattner b29957500e Add unordered comparisons 
llvm-svn: 24809
 2005-12-18 01:41:39 +00:00
Chris Lattner e58481be36 Add patterns to the rest of the int condbranches and some of the fp branches 
llvm-svn: 24808
 2005-12-18 01:38:19 +00:00
Chris Lattner 9cf4bb2867 Add initial conditional branch support. This doesn't actually work yet due 
to a bug in the scheduler.

llvm-svn: 24807
 2005-12-18 01:20:35 +00:00
Chris Lattner 00759eac78 Eliminate CMPri, which is a synonym for SUBCCri 
llvm-svn: 24805
 2005-12-17 23:52:08 +00:00
Chris Lattner 5a6b03c1b8 add fneg,fabs,fsqrt instructions 
llvm-svn: 24803
 2005-12-17 23:20:27 +00:00
Chris Lattner 32f19262d5 Add patterns for fround/fextend and the funny fsmuld instruction 
llvm-svn: 24802
 2005-12-17 23:14:30 +00:00
Chris Lattner 06952dfced Add FP +,-,*,/ 
llvm-svn: 24801
 2005-12-17 23:10:46 +00:00
Chris Lattner 89078880f2 Give patterns to F3_3 instructions 
llvm-svn: 24800
 2005-12-17 23:05:35 +00:00
Chris Lattner 829572cdca Implement 64-bit add/sub, make sure to receive and return 64-bit args with 
the right halves in the right regs

llvm-svn: 24799
 2005-12-17 22:55:57 +00:00
Chris Lattner ebfa06a2de implement div and rem 
llvm-svn: 24798
 2005-12-17 22:39:19 +00:00
Chris Lattner 8eaf9f4cb3 implement MULHU/MULHS for 64-bit multiplies 
llvm-svn: 24797
 2005-12-17 22:30:00 +00:00
Chris Lattner 4abe9528f9 Add patterns for multiply, simplify Y register handling stuff, add RDY instruction 
llvm-svn: 24796
 2005-12-17 22:22:53 +00:00
Chris Lattner 2616a0b56f Make the addressing modes smarter 
llvm-svn: 24795
 2005-12-17 21:25:27 +00:00
Chris Lattner 19ff62dc67 remove some unused instructions 
llvm-svn: 24794
 2005-12-17 21:13:50 +00:00
Chris Lattner e39ab718c0 add andn/orn/xorn patterns. This allows us to compile this: 
long %test(ubyte, short, long %X, long %Y) {
  %A = xor long %X, -1
  %B = and long %Y, %A
  ret long %B
}

to this:

test:
        save -96, %sp, %sp
        andn %i4, %i2, %i0
        andn %i5, %i3, %i1
        restore %g0, %g0, %g0
        retl
        nop

instead of this:

test:
        save -96, %sp, %sp
        xor %i2, -1, %l0
        xor %i3, -1, %l1
        and %i4, %l0, %i0
        and %i5, %l1, %i1
        restore %g0, %g0, %g0
        retl
        nop

The simpleisel emits:  :(

test:
        save -96, %sp, %sp
        or %g0, -1, %l0
        or %g0, -1, %l0
        or %g0, -1, %l0
        or %g0, -1, %l1
        xor %i2, %l0, %l0
        xor %i3, %l1, %l1
        and %i4, %l0, %i0
        and %i5, %l1, %i1
        restore %g0, %g0, %g0
        retl
        nop

llvm-svn: 24793
 2005-12-17 21:05:49 +00:00
Chris Lattner ea752cc50a Add support for 64-bit arguments 
llvm-svn: 24792
 2005-12-17 20:59:06 +00:00
Chris Lattner 6be83f9959 Sparc doesn't have sext_inreg 
llvm-svn: 24791
 2005-12-17 20:50:42 +00:00
Chris Lattner d10995cb26 add patterns for FP stores 
llvm-svn: 24790
 2005-12-17 20:47:16 +00:00
Chris Lattner 490a6edf52 Add [reg+reg] integer stores 
llvm-svn: 24789
 2005-12-17 20:44:36 +00:00
Chris Lattner b57bb13253 Add store patterns 
llvm-svn: 24788
 2005-12-17 20:42:55 +00:00
Chris Lattner 233e044738 add truncstore 
llvm-svn: 24787
 2005-12-17 20:42:29 +00:00
Chris Lattner 7e7c355154 add fp load patterns, switch rest of loads and stores to use addrmodes 
llvm-svn: 24786
 2005-12-17 20:32:47 +00:00
Chris Lattner c4f3a7adea Add integer load[r+r] forms. 
llvm-svn: 24785
 2005-12-17 20:26:45 +00:00
Chris Lattner 1c02c45f18 Rename load/store instructions to include an RI suffix 
llvm-svn: 24784
 2005-12-17 20:18:49 +00:00
Chris Lattner 4fa86e1d55 Add patterns for the rest of the loads. Add 'ri' suffixes to the load and store insts 
llvm-svn: 24783
 2005-12-17 20:18:24 +00:00
Chris Lattner 5d15f9ed60 Add basic addressing mode support and one load. 
llvm-svn: 24782
 2005-12-17 20:04:49 +00:00
Chris Lattner db8e888fb5 eliminate some redundancy 
llvm-svn: 24781
 2005-12-17 19:47:05 +00:00
Chris Lattner 5e68639009 Use a combination of sethi and or to build arbitrary immediates. 
llvm-svn: 24780
 2005-12-17 19:41:43 +00:00
Chris Lattner 8546257435 Use sethi to build large immediates with zeros at the bottom 
llvm-svn: 24779
 2005-12-17 19:37:00 +00:00
Chris Lattner 7b6f2e879d Add shift and small immediate support 
llvm-svn: 24778
 2005-12-17 19:07:57 +00:00
Chris Lattner 30f924e3ca Add some basic reg-reg instructions 
llvm-svn: 24777
 2005-12-17 18:53:33 +00:00
Chris Lattner 2edb4b7f99 Add empty patterns to all F3_1 instructions 
llvm-svn: 24776
 2005-12-17 18:49:14 +00:00
Evan Cheng 1d71248392 Darwin API issue: indirect load of external and weak symbols. 
llvm-svn: 24775
 2005-12-17 09:13:43 +00:00
Chris Lattner 866cef563b Add some simple integer patterns. This allows us to compile this: 
int %test(int %A) {
  %B = add int %A, 1
  %C = xor int %B, 123
  ret int %C
}

into this:

test:
        save -96, %sp, %sp
        add %i0, 1, %l0
        xor %l0, 123, %i0
        restore %g0, %g0, %g0
        retl
        nop

for example.  I guess it would make sense to add reg/reg versions too.

llvm-svn: 24774
 2005-12-17 08:26:38 +00:00
Chris Lattner 80a3875bc1 Implement ret with operand, giving us this: 
int %test(int %A) {
  ret int %A
}

llvm-svn: 24773
 2005-12-17 08:15:09 +00:00
Chris Lattner 1136b7a2e0 Add a pattern for 'ret'. This now compiles: 
void %test() { ret void }

:)

llvm-svn: 24772
 2005-12-17 08:08:42 +00:00
Chris Lattner 1549e4d590 Add empty patterns for F3_2 instructions 
llvm-svn: 24771
 2005-12-17 08:06:43 +00:00
Chris Lattner 9f1c860e1e Implement LowerArguments, at least for the first 6 integer args 
llvm-svn: 24770
 2005-12-17 08:03:24 +00:00
Chris Lattner 4f34e9f7ff Add the framework for a dag-dag isel 
llvm-svn: 24769
 2005-12-17 07:47:01 +00:00
Evan Cheng f3b16bc5a0 Remove a few lines of dead code. 
llvm-svn: 24768
 2005-12-17 07:18:44 +00:00
Chris Lattner 69b5d17f92 asmprinter done, added crucial missing step 
llvm-svn: 24767
 2005-12-17 07:17:59 +00:00
Chris Lattner 55f9dbe1ea Use the AsmPrinter for global variable init printing. This eliminates a 
bunch of code and causes V8 to start using the fancy .asciz directive that
the sun assembler supports.

llvm-svn: 24766
 2005-12-17 07:17:08 +00:00
Chris Lattner fb7fd98cd4 Switch constant pool printing over to use the Shared AsmPrinter version 
llvm-svn: 24765
 2005-12-17 07:11:43 +00:00
Chris Lattner b808c8e2e4 Use the shared AsmPrinter code for some basic stuff. No functionality 
change except for fewer .section directives emitted

llvm-svn: 24764
 2005-12-17 07:04:29 +00:00
Evan Cheng 7087cd275b Added an idea about any_extend for performance tuning. 
llvm-svn: 24763
 2005-12-17 06:54:43 +00:00
Chris Lattner 9e2af046e4 Convert the remaining instructions over, branches and calls. Fix a couple 
minor bugs

llvm-svn: 24762
 2005-12-17 06:54:41 +00:00
Chris Lattner 6b669e2680 convert FP instructions to use an asmstring and operand list, allowing FP 
programs to work on V8 again

llvm-svn: 24761
 2005-12-17 06:32:52 +00:00
Evan Cheng bc7708c0e8 Added truncate. 
llvm-svn: 24760
 2005-12-17 02:02:50 +00:00
Evan Cheng b06925d1dd Added anyext, modelled as zext on X86. 
llvm-svn: 24759
 2005-12-17 01:47:57 +00:00
Evan Cheng 6b76009393 Added some isel ideas. 
llvm-svn: 24757
 2005-12-17 01:25:19 +00:00
Evan Cheng cb19390ead Added support for cmp, test, and conditional move instructions. 
llvm-svn: 24756
 2005-12-17 01:24:02 +00:00
Evan Cheng 0f68322992 Only lower SELECT when using DAG based isel. 
llvm-svn: 24755
 2005-12-17 01:22:13 +00:00
Evan Cheng 225a4d0d6d X86 lowers SELECT to a cmp / test followed by a conditional move. 
llvm-svn: 24754
 2005-12-17 01:21:05 +00:00
Jim Laskey 7c462768ed Added source file/line correspondence for dwarf (PowerPC only at this point.) 
llvm-svn: 24748
 2005-12-16 22:45:29 +00:00
Chris Lattner 887af88ce3 Weak and linkonce global vars should still have a .globl emitted for them 
llvm-svn: 24747
 2005-12-16 21:46:14 +00:00
Nate Begeman 672578bd94 Add a second vector type to the VRRC register class, and fix some patterns 
so that tablegen can infer all types.

llvm-svn: 24746
 2005-12-16 09:19:13 +00:00
Chris Lattner 9f2c3a7c4e add some notes 
llvm-svn: 24745
 2005-12-16 07:20:53 +00:00
Chris Lattner fa55745cbc Add a couple more instrs 
llvm-svn: 24744
 2005-12-16 07:18:48 +00:00
Chris Lattner e082426ae7 remove some dead code 
llvm-svn: 24743
 2005-12-16 07:16:02 +00:00
Chris Lattner 70310906e7 asmprint pseudo instrs 
llvm-svn: 24742
 2005-12-16 07:13:26 +00:00
Chris Lattner 68d064a3a6 Autogenerate asmprinter for F3_2 instructions 
llvm-svn: 24741
 2005-12-16 07:10:02 +00:00
Chris Lattner 1e777082a0 Switch F3_1 instructions over to use AsmStrings 
llvm-svn: 24740
 2005-12-16 06:52:00 +00:00
Chris Lattner 4870224a56 Plug in basic hooks for an autogenerated asm printer to fill in. 
llvm-svn: 24739
 2005-12-16 06:34:17 +00:00
Chris Lattner 34e80f0114 Add operand info for F3_[12] instructions, getting V8 back to basic functionality. 
With this, Regression/CodeGen/SparcV8/basictest.ll now passes.  Lets hear it
for regression tests :)

llvm-svn: 24738
 2005-12-16 06:25:42 +00:00
Chris Lattner b527f48acd Remove JIT support, which doesn't work. 
llvm-svn: 24736
 2005-12-16 06:06:07 +00:00
Chris Lattner 1e1ca1e9a5 add some simple operand info 
llvm-svn: 24735
 2005-12-16 06:02:58 +00:00
Chris Lattner 575751151c Update the darwin handling of linkonce & weak functions and GV stubs. This 
should work in all permutations.

llvm-svn: 24728
 2005-12-16 00:22:14 +00:00
Chris Lattner 9f62a2a51d Don't globalize internal functions 
llvm-svn: 24727
 2005-12-16 00:07:30 +00:00
Evan Cheng 74151ba279 * Promote all 1 bit entities to 8 bit. 
* Handling extload (1 bit -> 8 bit) and remove C++ code that handle 1 bit
zextload.

llvm-svn: 24726
 2005-12-15 19:49:23 +00:00
Evan Cheng 305c6a73b5 Added frameindex, constpool, globaladdr, and externalsym as root nodes of 
leaaddr.

llvm-svn: 24724
 2005-12-15 08:31:04 +00:00
Evan Cheng a2ebc62862 Added constpool, frameindex, and externalsym nodes. 
llvm-svn: 24723
 2005-12-15 08:29:48 +00:00
Evan Cheng 00fcb0017e Handling zero extension of 1 bit value. 
llvm-svn: 24722
 2005-12-15 01:02:48 +00:00
Evan Cheng bc9344477e Use MOV8rm to load 1 bit value. 
llvm-svn: 24721
 2005-12-15 00:59:17 +00:00
Nate Begeman 808f7a8abb Remove a now unused statistic. 
llvm-svn: 24720
 2005-12-14 22:56:16 +00:00
Nate Begeman e37cb604c1 Use the new predicate support that Evan Cheng added to remove some code 
from the DAGToDAG cpp file.  This adds pattern support for vector and
scalar fma, which passes test/Regression/CodeGen/PowerPC/fma.ll, and
does the right thing in the presence of -disable-excess-fp-precision.

Allows us to match:
void %foo(<4 x float> * %a) {
entry:
  %tmp1 = load <4 x float> * %a;
  %tmp2 = mul <4 x float> %tmp1, %tmp1
  %tmp3 = add <4 x float> %tmp2, %tmp1
  store <4 x float> %tmp3, <4 x float> *%a
  ret void
}

As:

_foo:
        li r2, 0
        lvx v0, r2, r3
        vmaddfp v0, v0, v0, v0
        stvx v0, r2, r3
        blr

Or, with llc -disable-excess-fp-precision,

_foo:
        li r2, 0
        lvx v0, r2, r3
        vxor v1, v1, v1
        vmaddfp v1, v0, v0, v1
        vaddfp v0, v1, v0
        stvx v0, r2, r3
        blr

llvm-svn: 24719
 2005-12-14 22:54:33 +00:00
Evan Cheng 023aef2f31 Fixed a typo: line 2323: MOVSX16rm8 -> MOVZX16rm8. This was the cause fo 12/14/2005 hbd failure. 
llvm-svn: 24717
 2005-12-14 22:28:18 +00:00
Evan Cheng 3db275d996 Added predicate !NoExcessFPPrecision to FMADD, FMADDS, FMSUB, and FMSUBS. 
llvm-svn: 24716
 2005-12-14 22:07:12 +00:00
Evan Cheng d296a43f96 Added support to specify predicates. 
llvm-svn: 24715
 2005-12-14 22:02:59 +00:00
Evan Cheng b8be9d1596 Fixed extload type profile. The 4th operand is a ValueType node with type 
OtherVT, it cannot be compare to type of 1st operand which is an integer type.

llvm-svn: 24713
 2005-12-14 19:40:54 +00:00
Evan Cheng c273900dd8 Added sext and zext patterns. 
llvm-svn: 24705
 2005-12-14 02:22:27 +00:00
Evan Cheng 683d8515b1 Added sextld + zextld DAG nodes. 
llvm-svn: 24703
 2005-12-14 02:21:01 +00:00
Nate Begeman 40f081d8e0 Add support for fmul node of type v4f32. 
void %foo(<4 x float> * %a) {
entry:
  %tmp1 = load <4 x float> * %a;
  %tmp2 = mul <4 x float> %tmp1, %tmp1
  store <4 x float> %tmp2, <4 x float> *%a
  ret void
}

Is selected to:

_foo:
        li r2, 0
        lvx v0, r2, r3
        vxor v1, v1, v1
        vmaddfp v0, v0, v0, v1
        stvx v0, r2, r3
        blr

llvm-svn: 24701
 2005-12-14 00:34:09 +00:00
Nate Begeman 69caef2b78 Prepare support for AltiVec multiply, divide, and sqrt. 
llvm-svn: 24700
 2005-12-13 22:55:22 +00:00
Evan Cheng 229f0ee6d7 Add load + store folding srl and sra patterns. 
llvm-svn: 24696
 2005-12-13 07:24:22 +00:00
Chris Lattner 87079884d1 Use the shared asmprinter code for printing special llvm globals 
llvm-svn: 24695
 2005-12-13 06:32:50 +00:00
Chris Lattner 4d80f6e52e Add ELF and darwin support for static ctors and dtors 
llvm-svn: 24693
 2005-12-13 04:53:51 +00:00
Chris Lattner 54a11df95d reindent a loop, unswitch a loop. No functionality changes 
llvm-svn: 24692
 2005-12-13 04:33:58 +00:00
Evan Cheng acec857b1a Beautify a few patterns. 
llvm-svn: 24690
 2005-12-13 02:40:18 +00:00
Evan Cheng 89c6db4baf Some shl patterns which do load + store folding. 
llvm-svn: 24689
 2005-12-13 02:34:51 +00:00
Evan Cheng 108beceb0f A few helper fragments for loads. e.g. (i8 (load addr:$src)) -> (loadi8 addr:$src). Only to improve readibility. 
llvm-svn: 24688
 2005-12-13 01:57:51 +00:00
Evan Cheng ddd5ae5a22 Add and, or, and xor patterns which fold load + stores. 
llvm-svn: 24687
 2005-12-13 01:41:36 +00:00
Evan Cheng e5a94a03e2 Add inc + dec patterns which fold load + stores. 
llvm-svn: 24686
 2005-12-13 01:02:47 +00:00
Evan Cheng bde9e6fca6 Add neg and not patterns which fold load + stores. 
llvm-svn: 24685
 2005-12-13 00:54:44 +00:00
Evan Cheng c414d563f0 Missed a couple redundant explicit type casts. 
llvm-svn: 24684
 2005-12-13 00:25:07 +00:00
Evan Cheng 62e6808aa5 Fix some bad choice of names: i16SExt8 ->i16immSExt8, etc. 
llvm-svn: 24683
 2005-12-13 00:14:11 +00:00