69ac08c683
nasty paste-o, calls passing more than 8 arguments along were having
...
args >8 put into the wrong place
llvm-svn: 25027
2005-12-27 10:17:03 +00:00
5bd1c2783b
Restore some happiness to the JIT
...
llvm-svn: 25026
2005-12-27 06:25:50 +00:00
962dcbd572
Fix alpha regressions.
...
llvm-svn: 25025
2005-12-27 03:53:58 +00:00
8258489ca4
Fix a problem duraid pointed out to me compiling kc++ with -enable-x86-fastcc
...
llvm-svn: 25024
2005-12-27 03:02:18 +00:00
14c53b45f5
Added field noResults to Instruction.
...
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.
llvm-svn: 25017
2005-12-26 09:11:45 +00:00
f520093eb3
add br pattern, unify JSR and BSR ISel instrs, and add BSR support for DAG
...
llvm-svn: 25011
2005-12-25 17:36:48 +00:00
6b240e55d1
unbreak calls, a few more tests should run. Tomorrow: bugpoint!
...
llvm-svn: 25010
2005-12-25 14:09:08 +00:00
06dcc199f0
we don't feed our call instructions extra operands
...
llvm-svn: 25009
2005-12-25 14:07:01 +00:00
0fce613eff
All that just to lower div and rem
...
llvm-svn: 25008
2005-12-25 01:34:27 +00:00
0dc12c38e5
support targetexternalsym
...
llvm-svn: 25005
2005-12-24 23:36:59 +00:00
782b654e6f
Let the helper functions know about X86::FR32RegClass and X86::FR64RegClass.
...
llvm-svn: 25004
2005-12-24 09:48:35 +00:00
5b18ed9e60
All addressing modes are now exposed. The only remaining relocated forms
...
are for function prologue.
TODO: move external symbols over to using RelLit.
: have a pattern that matches constpool|globaladdr
: have a pattern that matches (add x imm) -> x, imm or (...) -> ..., 0
llvm-svn: 25003
2005-12-24 08:29:32 +00:00
b9aaea3564
Unify the patterns for loads and stores. Now offset addressing should be
...
supported. This almost completes memory operations.
llvm-svn: 25002
2005-12-24 07:34:33 +00:00
4621488965
Let's see if we can break things.
...
Lower GOT relative addresses to Lo and HI.
Update both ISels to select them when they can.
Saves instructions here and there.
llvm-svn: 25001
2005-12-24 05:36:33 +00:00
636e1aed43
move loads and stores over. Smart addr selection comming
...
llvm-svn: 25000
2005-12-24 03:41:56 +00:00
9aea6e4691
Fix one of the things in the todo file, and get a bit closer to folding
...
constant offsets from statics into the address arithmetic.
llvm-svn: 24999
2005-12-24 01:00:15 +00:00
9ae486047e
* Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead.
...
* Added a pseudo instruction (for each target) that represent "return void".
This is a workaround for lack of optional flag operand (return void is not
lowered so it does not have a flag operand.)
llvm-svn: 24997
2005-12-23 22:14:32 +00:00
4f52796f79
not a good idea
...
llvm-svn: 24991
2005-12-23 07:37:47 +00:00
5c59d49630
More X86 floating point patterns.
...
llvm-svn: 24990
2005-12-23 07:31:11 +00:00
8be8067b19
Operand 1 of TRUNCSTORE can be any of integer and floating point types.
...
llvm-svn: 24989
2005-12-23 07:30:30 +00:00
55823ae03f
fix something-o
...
llvm-svn: 24987
2005-12-23 07:08:39 +00:00
5427aab5f8
implement vaarg. Varargs now should work.
...
llvm-svn: 24986
2005-12-23 06:37:38 +00:00
5ee896aad9
implement vastart. The dag isel compiles this:
...
void test3(va_list Y);
void test2(int F, ...) {
va_list X;
va_start(X, F);
test3(X);
}
into this:
test2:
save -104, %o6, %o6
st %i5, [%i6+88]
st %i4, [%i6+84]
st %i3, [%i6+80]
st %i2, [%i6+76]
st %i1, [%i6+72]
add %i6, 72, %o0
st %o0, [%i6+-4]
call test3
nop
restore %g0, %g0, %g0
retl
nop
The simple isel emits:
test2:
save -96, %o6, %o6
st %i0, [%i6+68]
st %i1, [%i6+72]
st %i2, [%i6+76]
st %i3, [%i6+80]
st %i4, [%i6+84]
st %i5, [%i6+88]
or %g0, 1, %l0
or %g0, 4, %l1
umul %l0, %l1, %l0
add %l0, 7, %l0
and %l0, -8, %l0
sub %o6, %l0, %o6
add %o6, 96, %l0
add %i6, 72, %l1
st %l1, [%l0]
ld [%l0], %o0
call test3
nop
restore %g0, %g0, %g0
retl
nop
llvm-svn: 24985
2005-12-23 06:24:04 +00:00
6e6d5a1fa1
remove benchmark list, remove issues addressed by the dag-dag isel
...
llvm-svn: 24984
2005-12-23 06:09:30 +00:00
30107e65c8
make sure bit_convert's are expanded
...
llvm-svn: 24979
2005-12-23 05:15:23 +00:00
c46fc2482c
make sure bit_converts are expanded
...
llvm-svn: 24978
2005-12-23 05:13:35 +00:00
5ce81edbf6
fix the int<->fp instructions, which apparently take a single float register
...
to represent the int part (because it's always 32-bits)
llvm-svn: 24976
2005-12-23 05:00:16 +00:00
c9849274bd
Use BIT_CONVERT to simplify this code
...
llvm-svn: 24975
2005-12-23 02:31:39 +00:00
f474034432
Simplify some code by using BIT_CONVERT
...
llvm-svn: 24974
2005-12-23 00:59:59 +00:00
4c141d047c
clean up .td file by using evan's new FLAG thing
...
llvm-svn: 24967
2005-12-22 21:18:39 +00:00
177d7af5d5
remove dead code
...
llvm-svn: 24965
2005-12-22 21:16:08 +00:00
6b0325aa26
fix handling of weak linkage
...
llvm-svn: 24964
2005-12-22 21:15:17 +00:00
ffe3542726
move some random notes out of my email into someplace useful
...
llvm-svn: 24956
2005-12-22 17:19:28 +00:00
644e7db818
this is a hack, which may or may not hang around. In short:
...
whimper out of doing things the Right Way, and hack up a generic
'BRCALL' instruction, that gets generated when calls are lowered.
This gets selected by hand in the DAG isel, where it gets turned
into real (i.e. in tablegen) br.call instructions.
BUG: this dies on void calls, but seems to work otherwise?
llvm-svn: 24952
2005-12-22 13:29:14 +00:00
3692fa14b8
we can't do this directly in lowering, so we need this case
...
llvm-svn: 24951
2005-12-22 07:14:45 +00:00
3608ab87c0
oops, back this out
...
llvm-svn: 24950
2005-12-22 07:13:51 +00:00
b1d57fb175
we can't all have brains now, can we
...
llvm-svn: 24948
2005-12-22 06:41:39 +00:00
d0c146d59f
this should take care of calls to varadic functions, but it doesn.,t
...
BUG: calling printf(string, float) will load the float into the wrong
register, completely forget about loading the string, etce
llvm-svn: 24947
2005-12-22 06:39:57 +00:00
a8de8a5db4
we need to emit the getf.d instruction in lowering, so add it
...
to IA64ISD
llvm-svn: 24946
2005-12-22 06:38:38 +00:00
5ccf76fed3
I shoulda done this a *long* time ago (tm): implement calls properly,
...
i.e. r1/r12/rp are saved/restored regardless of scheduling/luck
TODO: calls to external symbols, indirect (function descriptor) calls,
performance (we're being paranoid right now)
BUG: the code for handling calls to vararg functions breaks if FP
args are passed (this will make printf() go haywire so a bunch of
tests will fail)
BUG: this seems to trigger some legalize nastiness
llvm-svn: 24942
2005-12-22 04:07:40 +00:00
8f6c86fe3b
kill SelectCALL() in the DAG isel, we handle this in lowering now, like
...
SPARCv8. (we copy sparcv8's workaround for tablegen not being nice about
ISD::CALL/TAILCALL)
llvm-svn: 24941
2005-12-22 03:58:17 +00:00
a743e00e7a
update tablegen files - nothing to see here
...
llvm-svn: 24939
2005-12-22 03:56:03 +00:00
dfad8ed54e
Bye bye HACKTROCITY.
...
llvm-svn: 24935
2005-12-22 02:26:21 +00:00
62fef13143
Added special flag node FLAG.
...
llvm-svn: 24934
2005-12-22 02:25:14 +00:00
1872908f3b
Lefted out TargetLowering::
...
llvm-svn: 24922
2005-12-21 23:14:54 +00:00
9cdc16c6d3
* Fix a GlobalAddress lowering bug.
...
* Teach DAG combiner about X86ISD::SETCC by adding a TargetLowering hook.
llvm-svn: 24921
2005-12-21 23:05:39 +00:00
02767195bb
Oops. Accidentally deleted RET pattern. It's still needed for return void;
...
llvm-svn: 24920
2005-12-21 22:22:16 +00:00
9e296bee9a
Disengage DEBUG_LOC from non-PPC targets.
...
llvm-svn: 24919
2005-12-21 20:51:37 +00:00
c1583dbd63
* Added support for X86 RET with an additional operand to specify number of
...
bytes to pop off stack.
* Added support for X86 SETCC.
llvm-svn: 24917
2005-12-21 20:21:51 +00:00
81f2653e45
add some nodes, forgot to commit this last night :(
...
llvm-svn: 24901
2005-12-21 16:22:46 +00:00
0dcdd83c0e
This was meant to go in
...
llvm-svn: 24900
2005-12-21 07:50:26 +00:00
f431ad4477
Rewrite FP stackifier support in the X86InstrInfo.td file, splitting patterns
...
that were overloaded to work before and after the stackifier runs. With the
new clean world, it is possible to write patterns for these instructions: woo!
This also adds a few simple patterns here and there, though there are a lot
still missing. These should be easy to add though. :)
See the comments under "Floating Point Stack Support" for more details on
the new world order.
This patch as absolutely no effect on the generated code, woo!
llvm-svn: 24899
2005-12-21 07:47:04 +00:00
988827a482
Wrap some long lines: no functionality change
...
llvm-svn: 24898
2005-12-21 05:34:58 +00:00
72575d882b
remove dead code
...
llvm-svn: 24896
2005-12-21 05:27:51 +00:00
a2f308fc3e
Remove ISD::RET select code. Now tblgen'd.
...
llvm-svn: 24889
2005-12-21 02:41:57 +00:00
a74ce62746
* Added lowering hook for external weak global address. It inserts a load
...
for Darwin.
* Added lowering hook for ISD::RET. It inserts CopyToRegs for the return
value (or store / fld / copy to ST(0) for floating point value). This
eliminate the need to write C++ code to handle RET with variable number
of operands.
llvm-svn: 24888
2005-12-21 02:39:21 +00:00
5c0b4df483
SSE2 floating point load / store patterns. SSE2 fp to int conversion patterns.
...
llvm-svn: 24886
2005-12-20 22:59:51 +00:00
82285c55aa
Flip the meaning of FPContractions to reflect Requires<[]> change.
...
llvm-svn: 24884
2005-12-20 20:08:53 +00:00
fc94dff7dc
Run lower-switch after lower-invoke.
...
Only run lower-allocations and lower-select for the simple isel
llvm-svn: 24881
2005-12-20 08:00:11 +00:00
10c7f67d78
Reserve G1 for frame offset stuff and use it to handle large stack frames.
...
For example, instead of emitting this:
test:
save -40112, %o6, %o6 ;; imm too large
add %i6, -40016, %o0 ;; imm too large
call caller
nop
restore %g0, %g0, %g0
retl
nop
emit this:
test:
sethi 4194264, %g1
or %g1, 848, %g1
save %o6, %g1, %o6
sethi 4194264, %g1
add %g1, %i6, %g1
add %i1, 944, %o0
call caller
nop
restore %g0, %g0, %g0
retl
nop
which doesn't cause the assembler to barf.
llvm-svn: 24880
2005-12-20 07:56:31 +00:00
5815a6e455
Added X86 readport patterns.
...
llvm-svn: 24879
2005-12-20 07:38:38 +00:00
6af02635a7
Added a hook to print out names of target specific DAG nodes.
...
llvm-svn: 24877
2005-12-20 06:22:03 +00:00
b11b8e44fa
Pattern-match return. Includes gross hack!
...
llvm-svn: 24874
2005-12-20 00:26:01 +00:00
c126397a69
Fix a couple of the FIXMEs, thanks to suggestion from Chris. This allows
...
us to load and store vectors directly at a pointer (offset of zero) by
using r0 as the base register. This also requires some asm printer work
to satisfy the darwin assembler.
For
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = add <4 x float> %tmp1, %tmp1
store <4 x float> %tmp2, <4 x float> *%a
ret void
}
We now produce:
_foo:
lvx v0, 0, r3
vaddfp v0, v0, v0
stvx v0, 0, r3
blr
Instead of:
_foo:
li r2, 0
lvx v0, r2, r3
vaddfp v0, v0, v0
stvx v0, r2, r3
blr
llvm-svn: 24872
2005-12-19 23:40:42 +00:00
8e6a8af205
Convert load/store over to being pattern matched
...
llvm-svn: 24871
2005-12-19 23:25:09 +00:00
6fc31046aa
X86 conditional branch support.
...
llvm-svn: 24870
2005-12-19 23:12:38 +00:00
1d9b671de0
It's essential we clear CodeGenMap after isel every basic block!
...
llvm-svn: 24867
2005-12-19 22:36:02 +00:00
7767a654b0
Fix pifft by correcting the case when a i64/f64 straddles O5 and memory:
...
we were storing into [FP+88] instead of [FP+92].
Improve codegen by emitting [FP+92], instead of emitting a copy of FP into
another GPR which wouldn't be coallesced because FP isn't register allocated.
llvm-svn: 24859
2005-12-19 07:57:53 +00:00
631c9df853
don't emit 'add %o6, 0, %o6' instructions
...
llvm-svn: 24857
2005-12-19 02:51:12 +00:00
5b9c9f9d36
Fix calls to functions returning i64
...
llvm-svn: 24856
2005-12-19 02:15:51 +00:00
655fac2c95
Correct bool truncstore operand order
...
llvm-svn: 24855
2005-12-19 02:06:50 +00:00
2c792ccc62
add the other bool zextload as well
...
llvm-svn: 24854
2005-12-19 01:44:58 +00:00
766170c6ee
implement zextload bool
...
llvm-svn: 24853
2005-12-19 01:43:04 +00:00
9be456300e
mark some unsupported ops as unsupported
...
llvm-svn: 24852
2005-12-19 01:39:40 +00:00
e59941810a
Fix syntax for indirect calls. This fixes Olden/mst
...
llvm-svn: 24850
2005-12-19 01:22:53 +00:00
bead785656
Keep stack frames 8-byte aligned. This fixes olden/voronoi
...
llvm-svn: 24849
2005-12-19 01:15:13 +00:00
9078c84654
apparently rdy isn't actually a psuedo instruction. Use rd %y
...
llvm-svn: 24848
2005-12-19 00:53:02 +00:00
d2e885e321
add fneg/fabs support for doubles
...
llvm-svn: 24847
2005-12-19 00:50:12 +00:00
14ee61ef00
Various cleanups to this pass, no functionality change
...
llvm-svn: 24846
2005-12-19 00:46:20 +00:00
d2a07eebcd
add bool truncstores
...
llvm-svn: 24845
2005-12-19 00:19:21 +00:00
15bd5ea92f
Elimiante SP and FP, which weren't members of the IntRegs register class
...
llvm-svn: 24844
2005-12-19 00:06:52 +00:00
f5f80cb947
The sun assembler only supports .xword in V9 mode.
...
llvm-svn: 24842
2005-12-18 23:36:45 +00:00
1ac15547d6
Configure the asmwriter to allow constant pools to be printed correctly
...
llvm-svn: 24841
2005-12-18 23:35:05 +00:00
030672f16b
add support for integer extloads
...
llvm-svn: 24840
2005-12-18 23:18:37 +00:00
c70ed7721b
Add support for undef
...
llvm-svn: 24839
2005-12-18 23:10:57 +00:00
4c3c3ac218
Add support for calls to external symbols
...
llvm-svn: 24838
2005-12-18 23:07:11 +00:00
388f3043b0
we have no memcpy
...
llvm-svn: 24837
2005-12-18 23:00:27 +00:00
c65cd5a03e
Fix a crash on a call with no arguments
...
llvm-svn: 24836
2005-12-18 22:57:47 +00:00
2f5fb6a720
This is handled by the autogen'd code
...
llvm-svn: 24834
2005-12-18 21:06:11 +00:00
1958690ff2
Change return lowering so that we can autogen the matching code.
...
llvm-svn: 24832
2005-12-18 21:03:04 +00:00
02e9904ee5
Implement Calls for V8. This would be completely autogenerated except for
...
a small bug in tblgen. When that is fixed, we can remove the ISD::Call case
in Select.
llvm-svn: 24830
2005-12-18 15:55:15 +00:00
a0be18c9a4
Implement the full V8 ABI for incoming arguments.
...
llvm-svn: 24825
2005-12-18 13:33:06 +00:00
8d1db078cb
Push ops list, asm string, and pattern all the way up to InstV8. Move the
...
InstV8 class to the InstrFormats file where it belongs.
llvm-svn: 24824
2005-12-18 08:21:00 +00:00
7cee2c9a5b
Give V8 select_cc, in the spirit of the PPC backend
...
llvm-svn: 24823
2005-12-18 08:13:54 +00:00
9de2958138
remove some unused instructions
...
llvm-svn: 24822
2005-12-18 07:15:17 +00:00
a9f0d108b1
V8 doesn't have FP extload
...
llvm-svn: 24821
2005-12-18 07:13:32 +00:00
d6806875d0
simplifications, fix typo
...
llvm-svn: 24820
2005-12-18 07:09:06 +00:00
c5609aab11
add a node, for completeness
...
llvm-svn: 24819
2005-12-18 07:05:21 +00:00
4492b1b7a0
Add frameindex support
...
Add support for copying (e.g. returning) doubles
Add support for F<->I instructions
llvm-svn: 24818
2005-12-18 06:59:57 +00:00
9dcfe37e76
Tighten up some checks
...
llvm-svn: 24817
2005-12-18 06:40:34 +00:00
Duraid Madina