Commit Graph

21195 Commits

Author SHA1 Message Date
Andrew Kaylor b2c1ee2a96 Updating XFAILs for recent GOT tests
llvm-svn: 192022
2013-10-05 01:56:50 +00:00
Andrew Kaylor 4968ca50e8 Adding tests for multiple GOTs with MCJIT
llvm-svn: 192021
2013-10-05 01:53:19 +00:00
Manman Ren b3388601fb Debug Info: In DIBuilder, the derived-from field of a DW_TAG_pointer_type
is updated to use DITypeRef.

Move isUnsignedDIType and getOriginalTypeSize from DebugInfo.h to be static
helper functions in DwarfCompileUnit. We already have a static helper function
"isTypeSigned" in DwarfCompileUnit, and a pointer to DwarfDebug is added to
resolve the derived-from field. All three functions need to go across link
for derived-from fields, so we need to get hold of a type identifier map.

A pointer to DwarfDebug is also added to DbgVariable in order to resolve the
derived-from field.

Debug info verifier is updated to check a derived-from field is a TypeRef.
Verifier will not go across link for derived-from fields, in debug info finder,
we go across the link to add derived-from fields to types.

Function getDICompositeType is only used by dragonegg and since dragonegg does
not generate identifier for types, we use an empty map to resolve the
derived-from field.

When printing a derived-from field, we use DITypeRef::getName to either return
the type identifier or getName of the DIType.

A paired commit at clang is required due to changes to DIBuilder.

llvm-svn: 192018
2013-10-05 01:43:03 +00:00
Venkatraman Govindaraju 30781deb1c [Sparc] Respect hasHardQuad parameter correctly when lowering SINT_TO_FP with fp128 operand.
llvm-svn: 192015
2013-10-05 00:31:41 +00:00
Adrian Prantl f01b562a15 Debug info: Don't crash in SelectionDAGISel when a vreg that is being
pointed to by a dbg_value belonging to a function argument is eliminated
during instruction selection.
rdar://problem/15094721.

llvm-svn: 192011
2013-10-05 00:08:27 +00:00
Venkatraman Govindaraju 84f1523cac [Sparc] Correct the floating point conditional code mapping in GetOppositeBranchCondition().
llvm-svn: 192006
2013-10-04 23:54:30 +00:00
Hal Finkel f5a3eaea55 UpdatePHINodes in BasicBlockUtils should not crash on duplicate predecessors
UpdatePHINodes has an optimization to reuse an existing PHI node, where it
first deletes all of its entries and then replaces them. Unfortunately, in the
case where we had duplicate predecessors (which are allowed so long as the
associated PHI entries have the same value), the loop removing the existing PHI
entries from the to-be-reused PHI would assert (if that PHI was not the one
which had the duplicates).

llvm-svn: 192001
2013-10-04 23:41:05 +00:00
Jack Carter 13d5f753f8 reverting per request
llvm-svn: 191992
2013-10-04 22:52:31 +00:00
Eric Christopher 6b8209b6b7 Use addFlag to add the enum class attribute.
This has the side effect of using DW_FORM_flag_present on dwarf4 and above.

llvm-svn: 191991
2013-10-04 22:40:10 +00:00
Reed Kotler 1b5b5c95cc Support tblockaddr for static compilation in Mips16.
llvm-svn: 191986
2013-10-04 22:01:40 +00:00
Rafael Espindola dc9fe0af85 Fix object file writing in llvm-lto on Windows.
We were writing in text mode.

Patch by Greg Bedwell.

llvm-svn: 191985
2013-10-04 21:40:54 +00:00
Jack Carter 721726adfc [MC][AsmParser] Hook for post assembly file processing
This patch handles LLVM standalone assembler (llvm-mc) ELF flag setting based on input file
directive processing.

Mips assembly requires processing inline directives that directly and
indirectly affect the output ELF header flags. This patch handles one
".abicalls".

To process these directives we are following the model the code generator
uses by storing state in a container as we go through processing and when
we detect the end of input file processing, AsmParser is notified and we
update the ELF header flags through a MipsELFStreamer method with a call from
MCTargetAsmParser::emitEndOfAsmFile(MCStreamer &OutStreamer).

This patch will allow other targets the same functionality.

Jack

llvm-svn: 191982
2013-10-04 21:26:15 +00:00
Akira Hatanaka 55504b4ac9 [mips] Fix a bug in MipsLongBranch::replaceBranch, which was erasing
instructions in delay slots along with the original branch instructions.

llvm-svn: 191978
2013-10-04 20:51:40 +00:00
Arnold Schwaighofer 698d4ac8a8 SLPVectorizer: Sort inputs to commutative binary operations
Sort the operands of the other entries in the current vectorization root
according to the first entry's operands opcodes.

%conv0 = uitofp ...
%load0 = load float ...

= fmul %conv0, %load0
= fmul %load0, %conv1
= fmul %load0, %conv2

Make sure that we recursively vectorize <%conv0, %conv1, %conv2> and <%load0,
%load0, %load0>.

This makes it more likely to obtain vectorizable trees. We have to be careful
when we sort that we don't destroy 'good' existing ordering implied by source
order.

radar://15080067

llvm-svn: 191977
2013-10-04 20:39:16 +00:00
Eric Christopher e595bae4a4 Temporarily revert r191792 as it is causing some LTO debug failures
on platforms with relocations in debug info and also temporarily
revert r191800 due to conflicts with the revert of r191792.

llvm-svn: 191967
2013-10-04 17:08:38 +00:00
Matthias Braun 2f169f900b ARM: optimizeSelect has to consider the previous register class
optimizeSelect folds (predicated) copy instructions, it must not ignore
the original register class of the operand when replacing the register
with the copies dest register.

llvm-svn: 191963
2013-10-04 16:52:56 +00:00
Matthias Braun c22630e164 ARM: do not add a regmask for TAILJUMPs
The jump doesn't really kill the registers, the following call does but
we never get back anyway.
This avoids some verify-machineinstrs problems when TAILJUMPs are
if-converted.

llvm-svn: 191962
2013-10-04 16:52:54 +00:00
Matthias Braun da621165ca ARM: preserve undef flag in pseudo instruction expanders
Copy over the whole register machine operand instead of creating a new one
with an incomplete set of flags.

llvm-svn: 191961
2013-10-04 16:52:51 +00:00
Rafael Espindola ebc256cad9 Fix this test.
llvm-svn: 191958
2013-10-04 14:53:58 +00:00
Jiangning Liu ac5fd7e5d3 Implement aarch64 neon instruction set AdvSIMD (3V elem).
llvm-svn: 191944
2013-10-04 09:20:44 +00:00
David Blaikie 309ffe4016 DebugInfo: Fix ordering of members after r191928
In the case (shown in the attached test) where a member function
definition was emitted into debug info the following could occur:

1) build the debug info for the member function definition
2) in (1), build the debug info for the member function declaration
3) construct and add the member function declaration DIE
4) add it to its context
5) build its context (the type it is a member of)
6) construct the members and add them to the type
7) except don't add member functions because "getOrCreateSubprogram"
adds the function to its parent anyway
8) except we're only partway through building this subprogram
declaration so it hasn't been added yet - but we returned the partially
constructed DIE (since it's already in the MDNode->DIE mapping to avoid
infinitely recursing trying to create the member function DIE)
9) once the type is constructed, add the member function to it
10) now the members are out of order (the member function being defined
is listed as the last member, even though it was declared as the first)

To avoid this, construct the context of the subprogram DIE before we
query to see if it exists. That way we never end up creating it before
creating its context and ending up in this situation.

Alternatively, the type construction that visits/builds all the members
could call something like getOrCreateSubprogram, but that doesn't ever
do the "add to context" step. Then the type building code would always
be responsible for adding members (and the subprogram "addToContextDIE"
would no-op because the context building would have added the subprogram
declaration to the type/context DIE already).

(the test cases updated were overly-sensitive to offsets or abbreviation
numbers. We don't have a nice way to make these tests more robust as yet
- multiline FileCheck matches would be required)

llvm-svn: 191939
2013-10-04 01:39:59 +00:00
Andrew Kaylor 1b2cfb6495 Adding support and tests for multiple module handling in lli
llvm-svn: 191938
2013-10-04 00:49:38 +00:00
Richard Mitton c250824772 Fixed a bug with section names containing special characters.
Changed the dwarf aranges code to not use getLabelEndName, as it turns out it's not reliable to call that given user-defined section names. Section names can have characters in that aren't representable as symbol names.

The dwarf-aranges test case has been updated to include a special character, to check this.

This fixes pr17416.

llvm-svn: 191932
2013-10-03 22:07:08 +00:00
Owen Anderson 5797bfd4a3 Pull fptrunc's upwards through selects when one of the select's selectands was a constant. This has a number of benefits, including producing small immediates (easier to materialize, smaller constant pools) as well as being more likely to allow the fptrunc to fuse with a preceding instruction (truncating selects are unusual).
llvm-svn: 191929
2013-10-03 21:08:05 +00:00
Rafael Espindola cda2911caa Optimize linkonce_odr unnamed_addr functions during LTO.
Generalize the API so we can distinguish symbols that are needed just for a DSO
symbol table from those that are used from some native .o.

The symbols that are only wanted for the dso symbol table can be dropped if
llvm can prove every other dso has a copy (linkonce_odr) and the address is not
important (unnamed_addr).

llvm-svn: 191922
2013-10-03 18:29:09 +00:00
Matt Arsenault bfa37e546d Make gep i8* X, -(ptrtoint Y) transform work with address spaces
llvm-svn: 191920
2013-10-03 18:15:57 +00:00
Eric Christopher c948b9df23 Make sure we emit a section for pubnames even if that section is
going to be empty. This is particularly important for the gnu
pubnames case since we're emitting a relocation to the section.

llvm-svn: 191915
2013-10-03 17:41:20 +00:00
Logan Chien b7ec8214bf [arm] Enhance the test case by checking .fpu directive.
llvm-svn: 191891
2013-10-03 12:18:56 +00:00
Amara Emerson 52cfb6a99a [ARM] Warn on deprecated IT blocks in v8 AArch32 assembly.
Patch by Artyom Skrobov.

llvm-svn: 191885
2013-10-03 09:31:51 +00:00
Alexey Samsonov 4436bf03e9 Remove wild .debug_aranges entries generated from unimportant labels
r191052 added emitting .debug_aranges to Clang, but this
functionality is broken: it uses all MC labels added in DWARF Asm
printer, including the labels for build relocations between
different DWARF sections, like .Lsection_line or .Ldebug_loc0.

As a result, if any DIE .debug_info would contain "DW_AT_location=0x123"
attribute, .debug_aranges would also contain a range starting from 0x123,
breaking tools that rely on this section.

This patch fixes this by using only MC labels that corresponds to the
addresses in the user program.

llvm-svn: 191884
2013-10-03 08:54:43 +00:00
Craig Topper 9e3e38ae3f Add XOP disassembler support. Fixes PR13933.
llvm-svn: 191874
2013-10-03 05:17:48 +00:00
Craig Topper af4b2eec9e Remove duplicated test cases that occurred when I applied the same patch file to my model twice.
llvm-svn: 191873
2013-10-03 04:27:14 +00:00
Craig Topper b01cd1aa74 Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao.
llvm-svn: 191871
2013-10-03 04:16:45 +00:00
Matt Arsenault 0be1cb1c7b Don't use runtime bounds check between address spaces.
Don't vectorize with a runtime check if it requires a
comparison between pointers with different address spaces.
The values can't be assumed to be directly comparable.
Previously it would create an illegal bitcast.

llvm-svn: 191862
2013-10-02 22:38:17 +00:00
Andrew Kaylor c483237f06 Fixing lli-child-target build
llvm-svn: 191861
2013-10-02 22:27:23 +00:00
Matt Arsenault e64c7c7530 Fix missing CHECK-LABELs
llvm-svn: 191853
2013-10-02 20:29:00 +00:00
Yi Jiang 8fd1a806d5 Apply slp vectorization on fully-vectorizable tree of height 2
llvm-svn: 191852
2013-10-02 20:20:39 +00:00
Benjamin Kramer b9add84ef6 SLPVectorizer: Make store chain finding more aggressive with GetUnderlyingObject.
This recursively strips all GEPs like the existing code. It also handles bitcasts and
other operations that do not change the pointer value.

llvm-svn: 191847
2013-10-02 19:06:06 +00:00
Andrew Kaylor c2ebf3f517 Adding out-of-process execution support to lli.
At this time only Unix-based systems are supported.  Windows has stubs and should re-route to the simulated mode.

Thanks to Sriram Murali for contributions to this patch.

llvm-svn: 191843
2013-10-02 17:12:36 +00:00
Tom Stellard d3e916eb6a StructurizeCFG: Add dependency on LowerSwitch pass
Switch instructions were crashing the StructurizeCFG pass, and it's
probably easier anyway if we don't need to handle them in this pass.

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 191841
2013-10-02 17:04:59 +00:00
Rafael Espindola d18b7c1744 Try harder to disable the LTO tests on windows.
llvm-svn: 191836
2013-10-02 15:47:30 +00:00
Chandler Carruth ea56494625 Remove the very substantial, largely unmaintained legacy PGO
infrastructure.

This was essentially work toward PGO based on a design that had several
flaws, partially dating from a time when LLVM had a different
architecture, and with an effort to modernize it abandoned without being
completed. Since then, it has bitrotted for several years further. The
result is nearly unusable, and isn't helping any of the modern PGO
efforts. Instead, it is getting in the way, adding confusion about PGO
in LLVM and distracting everyone with maintenance on essentially dead
code. Removing it paves the way for modern efforts around PGO.

Among other effects, this removes the last of the runtime libraries from
LLVM. Those are being developed in the separate 'compiler-rt' project
now, with somewhat different licensing specifically more approriate for
runtimes.

llvm-svn: 191835
2013-10-02 15:42:23 +00:00
Alexey Samsonov 31540172d0 Remove "localize global" optimization
Summary:
As discussed in http://llvm-reviews.chandlerc.com/D1754,
this optimization isn't really valid for C, and fires too rarely anyway.

Reviewers: rafael, nicholas

Reviewed By: nicholas

CC: rnk, llvm-commits, nicholas

Differential Revision: http://llvm-reviews.chandlerc.com/D1769

llvm-svn: 191834
2013-10-02 15:31:34 +00:00
Rafael Espindola ae22e3f1ef Add test I forgot to git add in r191824.
llvm-svn: 191831
2013-10-02 14:49:41 +00:00
Rafael Espindola 366296c0ef Disable this test on Win32 for now.
llvm-svn: 191830
2013-10-02 14:48:35 +00:00
Chandler Carruth 40689dc08f Don't layout items in a list in columns. That requires changing every
line just to add or remove a single element. What I wouldn't give to
have clang-format here an be able to format this more densely without
caring...

Re-group and sort the entries while here to make the whole thing more
clear.

llvm-svn: 191828
2013-10-02 14:31:21 +00:00
Rafael Espindola dafc53dde1 Add a -exported-symbol option to llvm-lto.
Patch by Tom Roeder.

llvm-svn: 191825
2013-10-02 14:12:56 +00:00
Rafael Espindola d38f9af213 Enable building LTO on WIN32.
Enable building the LTO library (.lib and.dll) and llvm-lto.exe on Windows with
MSVC and Mingw as well as re-enabling the associated test.

Patch by Greg Bedwell!

llvm-svn: 191823
2013-10-02 14:04:38 +00:00
Elena Demikhovsky 34586e7d41 AVX-512: fixed a bug in getLoadStoreRegOpcode() for AVX-512 target
llvm-svn: 191818
2013-10-02 12:20:42 +00:00
Manman Ren 9a0a67035e Debug Info: In DIBuilder, the derived-from field of a DW_TAG_pointer_type
is updated to use DITypeRef.

Move isUnsignedDIType and getOriginalTypeSize from DebugInfo.h to be static
helper functions in DwarfCompileUnit. We already have a static helper function
"isTypeSigned" in DwarfCompileUnit, and a pointer to DwarfDebug is added to
resolve the derived-from field. All three functions need to go across link
for derived-from fields, so we need to get hold of a type identifier map.

A pointer to DwarfDebug is also added to DbgVariable in order to resolve the
derived-from field.

Debug info verifier is updated to check a derived-from field is a TypeRef.
Verifier will not go across link for derived-from fields, in debug info finder,
we go across the link to add derived-from fields to types.

Function getDICompositeType is only used by dragonegg and since dragonegg does
not generate identifier for types, we use an empty map to resolve the
derived-from field.

When printing a derived-from field, we use DITypeRef::getName to either return
the type identifier or getName of the DIType.

A paired commit at clang is required due to changes to DIBuilder.

llvm-svn: 191800
2013-10-01 23:45:54 +00:00
Manman Ren 79b887f3e3 Remove triple from type unique testing cases.
llvm-svn: 191794
2013-10-01 20:27:56 +00:00
Manman Ren 512dc5660a Try to fix native-arm bot
llvm-svn: 191793
2013-10-01 20:23:12 +00:00
Manman Ren 8990d7ee84 Debug Info: remove duplication of DIEs when a DIE is part of the type system
and it is shared across CUs.

We add a few maps in DwarfDebug to map MDNodes for the type system to the
corresponding DIEs: MDTypeNodeToDieMap, MDSPNodeToDieMap, and
MDStaticMemberNodeToDieMap. These DIEs can be shared across CUs, that is why we
keep the maps in DwarfDebug instead of CompileUnit.

Sometimes, when we try to add an attribute to a DIE, the DIE is not yet added
to its owner yet, so we don't know whether we should use ref_addr or ref4.
We create a worklist that will be processed during finalization to add
attributes with the correct form (ref_addr or ref4).

We add addDIEEntry to DwarfDebug to be a wrapper around DIE->addValue. It checks
whether we know the correct form, if not, we update the worklist
(DIEEntryWorklist).

A testing case is added to show that we only create a single DIE for a type
MDNode and we use ref_addr to refer to the type DIE.

llvm-svn: 191792
2013-10-01 19:52:23 +00:00
Vincent Lejeune a4da6fb535 R600: add a pass that merges clauses.
llvm-svn: 191790
2013-10-01 19:32:58 +00:00
Vincent Lejeune 0b342d6f74 R600: Put PRED_X instruction in its own clause
llvm-svn: 191789
2013-10-01 19:32:49 +00:00
Vincent Lejeune 269708b98d R600: Enable -verify-machineinstrs in some tests.
llvm-svn: 191788
2013-10-01 19:32:38 +00:00
Matt Arsenault 517d84e268 Don't merge tiny functions.
It's silly to merge functions like these:

define void @foo(i32 %x) {
  ret void
}

define void @bar(i32 %x) {
  ret void
}

to get

define void @bar(i32) {
  tail call void @foo(i32 %0)
  ret void
}

llvm-svn: 191786
2013-10-01 18:05:30 +00:00
Preston Gurd a75d6cb89f Add test case for PR16785.
Thanks for Dimitry Andric, Rafael Espindola, and Benjamin Kramer
for providing and progressively reducing the test case!

llvm-svn: 191782
2013-10-01 17:02:48 +00:00
Richard Sandiford b63e300b67 [SystemZ] Add comparisons of high words and memory
llvm-svn: 191777
2013-10-01 15:00:44 +00:00
Richard Sandiford a9ac0e0f75 [SystemZ] Add comparisons of large immediates using high words
There are no corresponding patterns for small immediates because they would
prevent the use of fused compare-and-branch instructions.

llvm-svn: 191775
2013-10-01 14:56:23 +00:00
Richard Sandiford 42a694f44e [SystemZ] Add immediate addition involving high words
llvm-svn: 191774
2013-10-01 14:53:46 +00:00
Richard Sandiford 2cac763544 [SystemZ] Extend test-under-mask support to high GR32s
llvm-svn: 191773
2013-10-01 14:41:52 +00:00
Richard Sandiford 3ad5a15b72 [SystemZ] Extend 32-bit RISBG optimizations to high words
This involves using RISB[LH]G, whereas the equivalent z10 optimization
uses RISBG.

llvm-svn: 191770
2013-10-01 14:36:20 +00:00
Richard Sandiford 2896d044bd [SystemZ] Extend pseudo conditional 8- and 16-bit stores to high words
As the comment says, we always want to use STOC for 32-bit stores.

llvm-svn: 191767
2013-10-01 14:33:55 +00:00
Tim Northover d840745829 ARM: support interrupt attribute
This function-attribute modifies the callee-saved register list and function
epilogue (specifically the return instruction) so that a routine is suitable
for use as an interrupt-handler of the specified type without disrupting
user-mode applications.

rdar://problem/14207019

llvm-svn: 191766
2013-10-01 14:33:28 +00:00
Richard Sandiford 96f013b827 [SystemZ] Add test missing from r191764.
llvm-svn: 191765
2013-10-01 14:31:50 +00:00
Richard Sandiford 7028428c2c [SystemZ] Allow integer AND involving high words
llvm-svn: 191762
2013-10-01 14:20:41 +00:00
Richard Sandiford 5718dacbdd [SystemZ] Allow integer XOR involving high words
llvm-svn: 191759
2013-10-01 14:08:44 +00:00
Richard Sandiford 6e96ac600f [SystemZ] Allow integer OR involving high words
llvm-svn: 191755
2013-10-01 13:22:41 +00:00
Richard Sandiford 1a56931b22 [SystemZ] Allow integer insertions with a high-word destination
llvm-svn: 191753
2013-10-01 13:18:56 +00:00
Richard Sandiford 7c5c0eabc9 [SystemZ] Allow selects with a high-word destination
llvm-svn: 191751
2013-10-01 13:10:16 +00:00
Richard Sandiford 012402346f [SystemZ] Add patterns to load a constant into a high word (IIHF)
Similar to low words, we can use the shorter LLIHL and LLIHH if it turns
out that the other half of the GR64 isn't live.

llvm-svn: 191750
2013-10-01 13:02:28 +00:00
Richard Sandiford 21235a256f [SystemZ] Add register zero extensions involving at least one high word
llvm-svn: 191746
2013-10-01 12:49:07 +00:00
Joey Gouly ad98f1671d [ARM] Introduce the 'sevl' instruction in ARMv8.
This also removes the restriction on the immediate field of the 'hint'
instruction.

llvm-svn: 191744
2013-10-01 12:39:11 +00:00
Richard Sandiford 5469c39a26 [SystemZ] Add truncating high-word stores (STCH and STHH)
llvm-svn: 191743
2013-10-01 12:22:49 +00:00
Richard Sandiford 0d46b1a30f [SystemZ] Add zero-extending high-word loads (LLCH and LLHH)
llvm-svn: 191742
2013-10-01 12:19:08 +00:00
Benjamin Kramer 58f1ced564 SCEVExpander: Fix a regression I introduced by to eagerly adding RAII objects.
PR17425.

llvm-svn: 191741
2013-10-01 12:17:11 +00:00
Richard Sandiford 89e160d975 [SystemZ] Add sign-extending high-word loads (LBH and LHH)
llvm-svn: 191740
2013-10-01 12:11:47 +00:00
Richard Sandiford 0755c93b0c [SystemZ] Use upper words of GR64s for codegen
This just adds the basics necessary for allocating the upper words to
virtual registers (move, load and store).  The move support is parameterised
in a way that makes it easy to handle zero extensions, but the associated
zero-extend patterns are added by a later patch.

The easiest way of testing this seemed to be add a new "h" register
constraint for high words.  I don't expect the constraint to be useful
in real inline asms, but it should work, so I didn't try to hide it
behind an option.

llvm-svn: 191739
2013-10-01 11:26:28 +00:00
Richard Sandiford a26a4b4f60 [SystemZ] Reapply: Add definitions of LFH and STFH
Originally committed as r191661, but reverted because it changed the matching
order of comparisons on some hosts.  That should have been fixed by r191735.

llvm-svn: 191738
2013-10-01 10:31:04 +00:00
Daniel Sanders 0210dd4b93 [mips][msa] Added support for matching mod_[us] from normal IR (i.e. not intrinsics)
llvm-svn: 191737
2013-10-01 10:22:35 +00:00
Vladimir Medic 2b953d0b39 This patch adds aliases for Mips sub instruction with immediate operands. Corresponding test cases are added.
llvm-svn: 191734
2013-10-01 09:48:56 +00:00
Elena Demikhovsky 3b75f5d282 AVX-512: Added X86vzmovl patterns
llvm-svn: 191733
2013-10-01 08:38:02 +00:00
Eric Christopher 9a08f9e561 Add the DW_AT_GNU_ranges_base attribute if we've emitted any ranges
into the debug_ranges section.

llvm-svn: 191721
2013-10-01 00:43:36 +00:00
Matt Arsenault 21981a1a0d Use CHECK-LABEL
llvm-svn: 191713
2013-09-30 23:31:55 +00:00
Eric Christopher 39eebfada6 The DW_AT_GNU_pubnames/pubtypes attributes are actually form
SEC_OFFSET from the beginning of the section so go ahead and emit
a label at the beginning of each one.

llvm-svn: 191710
2013-09-30 23:14:16 +00:00
Eric Christopher 494bdcc453 Add llvm-readobj to the list of programs to find in the freshly built
toolchain.

Patch by Richard Pennington.

llvm-svn: 191706
2013-09-30 21:55:01 +00:00
Matt Arsenault 8468062c6e Use right address space size in InstCombineCompares
The test's output doesn't change, but this ensures
this is actually hit with a different address space.

llvm-svn: 191701
2013-09-30 21:11:01 +00:00
Matt Arsenault 06adecabe7 Constant fold ptrtoint + compare with address spaces
llvm-svn: 191699
2013-09-30 21:06:18 +00:00
Tilmann Scheller 34b4126769 [ARM] Fix Thumb(-2) diagnostic tests.
Changing the diagnostic message for out of range branch targets in 191686 broke the tests.

The diagnostic message for out of range branch targets was changed to be more consistent with the other diagnostics.
 

llvm-svn: 191691
2013-09-30 18:50:51 +00:00
Manman Ren adf4cc171e TBAA: update tbaa format from scalar format to struct-path aware format.
llvm-svn: 191690
2013-09-30 18:17:55 +00:00
Manman Ren 1047fe452f TBAA: remove !tbaa from testing cases when they are not needed.
llvm-svn: 191689
2013-09-30 18:17:35 +00:00
Jack Carter 8ff70e3e26 [mips][msa] Direct Object Emission for I8 instructions.
This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b.


Patch by Matheus Almeida

llvm-svn: 191688
2013-09-30 18:05:18 +00:00
Jack Carter c3b25686b9 [mips][msa] Direct Object Emission for I5 instructions.
This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}.


Patch by Matheus Almeida

llvm-svn: 191687
2013-09-30 17:58:07 +00:00
Jack Carter 92e6e0f171 [mips][msa] Direct Object Emission for 2R instructions.
This patch adds Direct Object Emission support for 2R instructions: nloc.{b,h,w}, nlzc.{b,h,w}, pcnt.{b,w,d}.  


Patch by Matheus Almeida

llvm-svn: 191685
2013-09-30 17:52:33 +00:00
Jack Carter 6eed9cc6a8 [PATCH 1/4] [mips][msa] Source register of FILL instructions is GPR
and not an MSA register

Patch by Matheus Almeida

llvm-svn: 191684
2013-09-30 17:43:04 +00:00
Tilmann Scheller 0e1dd8c176 [ARM] Use FileCheck instead of grep for ARM LDRD negative tests.
llvm-svn: 191683
2013-09-30 17:31:26 +00:00
Rafael Espindola cbef8e60e3 Revert "Enable building LTO on WIN32."
This reverts commit r191670.

It was causing build failures on the msvc bots:

http://bb.pgr.jp/builders/ninja-clang-i686-msc17-R/builds/5166/steps/compile/logs/stdio

llvm-svn: 191679
2013-09-30 16:32:51 +00:00
Tilmann Scheller 255722beb8 [ARM] Assembler: ARM LDRD with writeback requires the base register to be different from the destination registers.
See ARM ARM A8.8.72.

Violating this constraint results in unpredictable behavior.

llvm-svn: 191678
2013-09-30 16:11:48 +00:00
Benjamin Kramer d36f1abefd IRBuilder: Add RAII objects to reset insertion points or fast math flags.
Inspired by the object from the SLPVectorizer. This found a minor bug in the
debug loc restoration in the vectorizer where the location of a following
instruction was attached instead of the location from the original instruction.

llvm-svn: 191673
2013-09-30 15:39:48 +00:00
Rafael Espindola e693181c10 Enable building LTO on WIN32.
Enable building the LTO library (.lib and.dll) and llvm-lto.exe on Windows with
MSVC and Mingw as well as re-enabling the associated test.

Patch by Greg Bedwell!

llvm-svn: 191670
2013-09-30 15:28:14 +00:00
Joey Gouly d51a35c6a0 Fix a bug in InstCombine where it attempted to cast a Value* to an Instruction*
when it was actually a Constant*.

There are quite a few other casts to Instruction that might have the same problem,
but this is the only one I have a test case for.

llvm-svn: 191668
2013-09-30 14:18:35 +00:00
Tilmann Scheller 38c4ef68d8 [ARM] Assembler: Add more negative tests for ARM LDRD.
llvm-svn: 191664
2013-09-30 13:04:22 +00:00
Richard Sandiford a25f268c25 [SystemZ] Revert r191661: Add definitions of LFH and STFH
For some reason, adding definitions for these load and store
instructions changed whether some of the build bots matched
comparisons as signed or unsigned.

llvm-svn: 191663
2013-09-30 12:01:35 +00:00
Richard Sandiford d30ac3a125 [SystemZ] Add definitions of LFH and STFH
llvm-svn: 191661
2013-09-30 10:50:33 +00:00
Craig Topper 93a3d5973d Add a few more FMA4 disassembler test cases to match the scalar set with regards to combinations of L and W-bits.
llvm-svn: 191650
2013-09-30 02:50:51 +00:00
Craig Topper ed59dd34fd Various x86 disassembler fixes.
Add VEX_LIG to scalar FMA4 instructions.
Use VEX_LIG in some of the inheriting checks in disassembler table generator.
Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts.
Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set.
Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases.
Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms.

llvm-svn: 191649
2013-09-30 02:46:36 +00:00
Benjamin Kramer 155c9d5d97 ObjectSizeOffsetEvaluator: Don't run into infinite recursion if we have a cyclic GEP.
Those can occur in dead code. PR17402.

llvm-svn: 191644
2013-09-29 19:39:13 +00:00
Craig Topper c047fe3b5a Revert accidental commit.
llvm-svn: 191633
2013-09-29 08:35:51 +00:00
Craig Topper 3aef88b1c7 Change type of XOP flag in code emitters to a bool. Remove a some unneeded cases from switch.
llvm-svn: 191632
2013-09-29 08:33:34 +00:00
Benjamin Kramer d75c8ebdd1 Add a test that large offsets on GEPs on 32 bits targets are handled correctly.
llvm-svn: 191628
2013-09-28 21:27:49 +00:00
Robert Wilhelm f0cfb83bb4 Fix spelling intruction -> instruction.
llvm-svn: 191610
2013-09-28 11:46:15 +00:00
Tom Stellard 0351ea2010 R600: Fix handling of NAN in comparison instructions
We were completely ignoring the unorder/ordered attributes of condition
codes and also incorrectly lowering seto and setuo.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 191603
2013-09-28 02:50:50 +00:00
Manman Ren 209b17cdaa AutoUpgrade: upgrade from scalar TBAA format to struct-path aware TBAA format.
We treat TBAA tags as struct-path aware TBAA format when the first operand
is a MDNode and the tag has 3 or more operands.

llvm-svn: 191593
2013-09-28 00:22:27 +00:00
Akira Hatanaka af4211ad94 [mips] Make sure loads from lazy-binding entries do not get CSE'd or hoisted out
of loops.

Previously, two consecutive calls to function "func" would result in the
following sequence of instructions:

1. load $16, %got(func)($gp) // load address of lazy-binding stub.
2. move $25, $16
3. jalr $25                  // jump to lazy-binding stub.
4. nop
5. move $25, $16
6. jalr $25                  // jump to lazy-binding stub again.

With this patch, the second call directly jumps to func's address, bypassing
the lazy-binding resolution routine:

1. load $25, %got(func)($gp) // load address of lazy-binding stub.
2. jalr $25                  // jump to lazy-binding stub.
3. nop
4. load $25, %got(func)($gp) // load resolved address of func.
5. jalr $25                  // directly jump to func.

llvm-svn: 191591
2013-09-28 00:12:32 +00:00
Matt Arsenault 31cfc78f81 Use right pointer type in DebugIR
llvm-svn: 191576
2013-09-27 22:26:25 +00:00
Rui Ueyama 4ebe2ba32c Resurrect lit.local.cfg to un-break hexagon buildbot.
llvm-svn: 191565
2013-09-27 21:26:38 +00:00
Matt Arsenault 29f31735a2 Fix SLPVectorizer using wrong address space for load/store
llvm-svn: 191564
2013-09-27 21:24:57 +00:00
Rui Ueyama c2bed42904 Re-submit r191472 with a fix for big endian.
llvm-objdump: Dump COFF import table if -private-headers option is given.
llvm-svn: 191557
2013-09-27 21:04:00 +00:00
Justin Bogner 4a9ac8cd75 InstCombine: Only foldSelectICmpAndOr for integer types
Currently foldSelectICmpAndOr asserts if the "or" involves a vector
containing several of the same power of two. We can easily avoid this by
only performing the fold on integer types, like foldSelectICmpAnd does.

Fixes <rdar://problem/15012516>

llvm-svn: 191552
2013-09-27 20:35:39 +00:00
Yunzhong Gao b8bbcbfcc8 Adding intrinsics to the llvm backend for TBM instruction set.
Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750

llvm-svn: 191539
2013-09-27 18:38:42 +00:00
Manman Ren 0ed04fc9ab TBAA: handle scalar TBAA format and struct-path aware TBAA format.
Remove the command line argument "struct-path-tbaa" since we should not depend
on command line argument to decide which format the IR file is using. Instead,
we check the first operand of the tbaa tag node, if it is a MDNode, we treat
it as struct-path aware TBAA format, otherwise, we treat it as scalar TBAA
format.

When clang starts to use struct-path aware TBAA format no matter whether
struct-path-tbaa is no, and we can auto-upgrade existing bc files, the support
for scalar TBAA format can be dropped.

Existing testing cases are updated to use the struct-path aware TBAA format.

llvm-svn: 191538
2013-09-27 18:34:27 +00:00
Justin Bogner ca9bd8fac1 Transforms: Use getFirstNonPHI to set the insertion point for PHIs
We were previously using getFirstInsertionPt to insert PHI
instructions when vectorizing, but getFirstInsertionPt also skips past
landingpads, causing this to generate invalid IR.

We can avoid this issue by using getFirstNonPHI instead.

llvm-svn: 191526
2013-09-27 15:30:25 +00:00
Richard Sandiford 067817ee05 [SystemZ] Rein back the use of block operations
The backend tries to use block operations like MVC, NC, OC and XC for
simple scalar operations.  For correctness reasons, it rejects any case
in which the regions might partially overlap.  However, for performance
reasons, it should also reject cases where the regions might be equal,
since the instruction might then not use the fast path.

This fixes a performance regression seen in bzip2.  We may want to limit
the optimisation even more in future, or even remove it entirely, but I'll
try with this for now.

llvm-svn: 191525
2013-09-27 15:29:20 +00:00
Richard Sandiford 54b369166f [SystemZ] Improve handling of PC-relative addresses
The backend previously folded offsets into PC-relative addresses
whereever possible.  That's the right thing to do when the address
can be used directly in a PC-relative memory reference (using things
like LRL).  But if we have a register-based memory reference and need
to load the PC-relative address separately, it's better to use an anchor
point that could be shared with other accesses to the same area of the
variable.

Fixes a FIXME.

llvm-svn: 191524
2013-09-27 15:14:04 +00:00
Daniel Sanders 6098b33515 [mips][msa] Implemented insert.d intrinsic.
This intrinsic is lowered into an equivalent INSERT_VECTOR_ELT which is
further lowered into a sequence of insert.w's on MIPS32.

llvm-svn: 191521
2013-09-27 13:36:54 +00:00
Tilmann Scheller 1aebfa0a9b ARM: Teach assembler to enforce constraints for ARM LDRD destination register operands.
As specified in A8.8.72/A8.8.73/A8.8.74 in the ARM ARM, all variants of the ARM LDRD instruction have the following two constraints:

LDRD<c> <Rt>, <Rt2>, ...

(a) Rt must be even-numbered and not r14
(b) Rt2 must be R(t+1)

If those two constraints are not met the result of executing the instruction will be unpredictable.

Constraint (b) was already enforced, this commit adds support for constraint (a).

Fixes rdar://14479793.

llvm-svn: 191520
2013-09-27 13:28:17 +00:00
Daniel Sanders c72593e69a [mips][msa] Implemented fill.d intrinsic.
This intrinsic is lowered into an equivalent BUILD_VECTOR which is further
lowered into a sequence of insert.w's on MIPS32.

llvm-svn: 191519
2013-09-27 13:20:41 +00:00
Daniel Sanders 7f3d946fb7 [mips][msa] Implemented copy_[us].d intrinsic.
This intrinsic is lowered into equivalent copy_s.w instructions during
legalization.

llvm-svn: 191518
2013-09-27 13:04:21 +00:00
Daniel Sanders a515070eb3 [mips][msa] Implemented insert_vector_elt for v4f32 and v2f64.
For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is
later expanded to appropriate insve.[wd] insns.

llvm-svn: 191515
2013-09-27 12:31:32 +00:00
Daniel Sanders 39bb8ba023 [mips][msa] Implemented extract_vector_elt for v4f32 or v2f64
For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may
be expanded to subregister copies and/or instructions as appropriate.

llvm-svn: 191514
2013-09-27 12:17:32 +00:00
Andrea Di Biagio 63192f635e Remove superfluous comment accidentally checked-in.
llvm-svn: 191513
2013-09-27 12:13:58 +00:00
Daniel Sanders 9ea9ff2da7 [mips][msa] Added support for MSA registers to copyPhysReg
llvm-svn: 191512
2013-09-27 12:03:51 +00:00
Daniel Sanders 7e51fe19d5 [mips][msa] Added support for matching splati from normal IR (i.e. not intrinsics)
Updated some of the vshf since they (correctly) emit splati's now

llvm-svn: 191511
2013-09-27 11:48:57 +00:00
Andrea Di Biagio 56ce9c4e78 Re-apply the change from r191393 with fix for pr17380.
This change fixes the problem reported in pr17380 and re-add the dagcombine 
transformation ensuring that the value types are always legal if the 
transformation is triggered after Legalization took place.

Added the test case from pr17380.

llvm-svn: 191509
2013-09-27 11:37:05 +00:00
Tilmann Scheller 88c8f16558 ARM: Teach assembler to enforce constraint for Thumb2 LDRD (literal/immediate) destination register operands.
LDRD<c> <Rt>, <Rt2>, <label>
LDRD<c> <Rt>, <Rt2>, [<Rn>{, #+/-<imm>}]
LDRD<c> <Rt>, <Rt2>, [<Rn>], #+/-<imm>
LDRD<c> <Rt>, <Rt2>, [<Rn>, #+/-<imm>]!

As specified in A8.8.72/A8.8.73 in the ARM ARM, the T1 encoding has a constraint which enforces that Rt != Rt2.

If this constraint is not met the result of executing the instruction will be unpredictable.

Fixes rdar://14479780.

llvm-svn: 191504
2013-09-27 10:30:18 +00:00
Daniel Sanders 1b1e25b7c5 [mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode.
llvm-svn: 191498
2013-09-27 10:08:31 +00:00
Daniel Sanders 36c671e2c7 [mips][msa] Expand all truncstores and loadexts for MSA as well as DSP
llvm-svn: 191496
2013-09-27 09:44:59 +00:00
Daniel Sanders f4f1a872ca [mips][msa] Added missing check in performSRACombine
Reviewers: jacksprat, dsanders

Reviewed By: dsanders

Differential Revision: http://llvm-reviews.chandlerc.com/D1755

llvm-svn: 191495
2013-09-27 09:25:29 +00:00
Yunzhong Gao 4467f33e3c Fixing Intel format of the vshufpd instruction.
Phabricator code review is located at: http://llvm-reviews.chandlerc.com/D1759

llvm-svn: 191481
2013-09-27 01:44:23 +00:00
Rui Ueyama 333d28a0bb Revert "llvm-objdump: Dump COFF import table if -private-headers option is given."
This reverts commit r191472 because it's failing on BE machine.

llvm-svn: 191480
2013-09-27 01:29:36 +00:00
Rui Ueyama 5b1adbaad9 llvm-objdump: Dump COFF import table if -private-headers option is given.
This is a patch to add capability to llvm-objdump to dump COFF Import Table
entries, so that we can write tests for LLD checking Import Table contents.

llvm-objdump did not print anything but just file name if the format is COFF
and -private-headers option is given. This is a patch adds capability for
dumping DLL Import Table, which is specific to the COFF format.

In this patch I defined a new iterator to iterate over import table entries.
Also added a few functions to COFFObjectFile.cpp to access fields of the entry.

Differential Revision: http://llvm-reviews.chandlerc.com/D1719

llvm-svn: 191472
2013-09-27 00:07:01 +00:00
Adrian Prantl 6ac40036f1 MCParser/Debug info: Accept line number 0 as a legitimate value, since
CFE produces it to indicate artificial locations.
c.f.: DWARF standard, Table 6.2:
line -- An unsigned integer indicating a source line number. Lines are numbered beginning at 1. The compiler may emit the value 0 in cases where an instruction cannot be attributed to any source line.

llvm-svn: 191471
2013-09-26 23:37:11 +00:00
Jack Carter cb8b40b08d [mips][msa] Direct Object Emission for 3RF instructions.
Patch by Matheus Almeida

llvm-svn: 191461
2013-09-26 21:31:43 +00:00
Weiming Zhao 286304a317 Fix PR 17372: Emitting PLD for stack address for ARM Thumb2
t2PLDi12, t2PLDi8, t2PLDs was omitted in Thumb2InstrInfo.
This patch fixes it.

llvm-svn: 191441
2013-09-26 17:25:10 +00:00
Bill Schmidt cea1596205 [PowerPC] Fix PR17354: Generate nop after local calls for PIC code.
When generating code for shared libraries, even local calls may be
intercepted, so we need a nop after the call for the linker to fix up the
TOC.  Test case adapted from the one provided in PR17354.

llvm-svn: 191440
2013-09-26 17:09:28 +00:00
Andrea Di Biagio 549d6605a0 Revert r191393 since it caused pr17380.
llvm-svn: 191438
2013-09-26 16:54:01 +00:00
Venkatraman Govindaraju 4c0cdd734c [Sparc] Implements exception handling in SPARC with DwarfCFI.
llvm-svn: 191432
2013-09-26 15:11:00 +00:00
Venkatraman Govindaraju 3816d43a9a Implements parsing and emitting of .cfi_window_save in MC.
llvm-svn: 191431
2013-09-26 14:49:40 +00:00
Amara Emerson b4ad2f396a [ARM] Use the load-acquire/store-release instructions optimally in AArch32.
Patch by Artyom Skrobov.

llvm-svn: 191428
2013-09-26 12:22:36 +00:00