Commit Graph

368216 Commits

Author SHA1 Message Date
Mehdi Amini afd729edee Add definition for static constexpr member (NFC)
Fix the build for some toolchain and config.
2020-10-05 16:56:27 +00:00
Andrzej Warzynski 8d51d37e06 [flang] Introduce DiagnosticConsumer classes in libflangFrontend
Currently Flang uses TextDiagnostic, TextDiagnosticPrinter &
TestDiagnosticBuffer classes from Clang (more specifically, from
libclangFrontend). This patch introduces simplified equivalents of these
classes in Flang (i.e. it removes the dependency on libclangFrontend).

Flang only needs these diagnostics classes for the compiler driver
diagnostics. This is unlike in Clang in which similar diagnostic classes
are used for e.g. Lexing/Parsing/Sema diagnostics. For this reason, the
implementations introduced here are relatively basic. We can extend them
in the future if this is required.

This patch also enhances how the diagnostics are printed. In particular,
this is the diagnostic that you'd get _before_  the changes introduced here
(no text formatting):

```
$ bin/flang-new
error: no input files
```

This is the diagnostic that you get _after_ the changes introduced here
(in terminals that support it, the text is formatted - bold + red):

```
$ bin/flang-new
flang-new: error: no input files
```

Tests are updated accordingly and options related to enabling/disabling
color diagnostics are flagged as supported by Flang.

Reviewed By: sameeranjoshi, CarolineConcatto

Differential Revision: https://reviews.llvm.org/D87774
2020-10-05 17:46:44 +01:00
Joseph Huber 1dce692de1 Revert "[OpenMP] Add Error Handling for Conflicting Pointer Sizes for Target Offload"
Reverting because detecting architecture size doesn't work on all
platforms.

This reverts commit eaf73293cb.
2020-10-05 12:35:39 -04:00
Cameron McInally 9642ded8ba [SVE] Lower fixed length VECREDUCE_AND operation
Differential Revision: https://reviews.llvm.org/D88707
2020-10-05 11:28:38 -05:00
Simon Pilgrim 5ba084c42f [InstCombine] Extend 'shift with constants' vector tests
Added missing test coverage for shl(add(and(lshr(x,c1),c2),y),c1) -> add(and(x,c2<<c1),shl(y,c1)) combine

Rename tests as 'foo' and 'bar' isn't very extensible

Added vector tests with undefs and nonuniform constants
2020-10-05 17:22:15 +01:00
Simon Pilgrim 2efd9fd699 [InstCombine] Add or(shl(v,and(x,bw-1)),lshr(v,bw-and(x,bw-1))) funnel shift tests
If we know the shift amount is less than the bitwidth we should be able to convert this to a funnel shift
2020-10-05 17:22:14 +01:00
Simon Pilgrim 0ac210e580 [X86] isTargetShuffleEquivalent - merge duplicate array accesses. NFCI. 2020-10-05 17:22:14 +01:00
Louis Dionne d5a6da84a3 [libc++/abi] Revert "[libc++] Move the weak symbols list to libc++abi"
This reverts commit c7d4aa711a. I am still investigating the issue,
but it looks like that commit has an interaction with ld64 that causes
new/delete weak re-exports not to work properly anymore. This is weird
because this commit did not touch the exports of new/delete -- I am
still investigating.
2020-10-05 11:42:13 -04:00
Christian Sigg 665371d0b2 [mlir] Split alloc-like op LLVM lowerings into base and separate derived classes.
The previous code did the lowering to alloca, malloc, and aligned_malloc
in a single class with different code paths that are somewhat difficult to
follow.

This change moves the common code to a base class and has a separte
derived class per lowering target that contains the specifics.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D88696
2020-10-05 17:36:01 +02:00
Michael Kruse c3f12dd606 [docs] Revise loop terminology reference.
Motivated by D88183, this seeks to clarify the current loop nomenclature with added illustrations, examples for possibly unexpected situations (infinite loops not part of the "parent" loop, logical loops sharing the same header, ...), and clarification on what other sources may consider a loop. The current document also has multiple errors that are fixed here.

Some selected errors:
 * Loops a defined as strongly-connected components. A component a partition of all nodes, i.e. a subloop can never be a component. That is, the document as it currently is only covers top-level loops, even it also uses the term SCC for subloops.
 * "a block can be the header of two separate loops at the same time" (it is considered a single loop by LoopInfo)
 * "execute before some interesting event happens" (some interesting event is not well-defined)

Reviewed By: baziotis, Whitney

Differential Revision: https://reviews.llvm.org/D88408
2020-10-05 10:28:04 -05:00
Wenlei He 89e8a8b223 Revert SVML support for sqrt
As was brought up in D87169 by @craig.topper we shouldn't map llvm.sqrt to svml since there is a faster native instruction.
https://software.intel.com/sites/landingpage/IntrinsicsGuide/#text=_mm_sqrt_p&expand=5824,5823,5356,5823,5825,5365,5356

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D88620
2020-10-05 08:13:11 -07:00
Joseph Huber eaf73293cb [OpenMP] Add Error Handling for Conflicting Pointer Sizes for Target Offload
Summary:
This patch adds an error to Clang that detects if OpenMP offloading is
used between two architectures with incompatible pointer sizes. This
ensures that the data mapping can be done correctly and solves an issue
in code generation generating the wrong size pointer. This patch adds a
new lit substitution, %omp_powerpc_triple that, if the system is 32-bit or
64-bit, sets the powerpc triple accordingly. This was required to fix
some OpenMP tests that automatically populated the target architecture.

Reviewers: jdoerfert

Subscribers: cfe-commits guansong sstefan1 yaxunl delcypher

Tags: OpenMP clang LLVM

Differential Revision: https://reviews.llvm.org/D88594
2020-10-05 11:02:13 -04:00
Joachim Protze 34b34e90fc [OpenMP][Tests] NFC: fix flaky test failure caused by rare scheduling
The worker thread can start execution of the task before creation of the second task
Fixes the spurious failure reported in https://reviews.llvm.org/D61657
2020-10-05 16:55:32 +02:00
Jonas Paulsson 34b61d6cd5 [SystemZ] Add support for .insn directives for vector instructions.
Support VRI, VRR, VRS, VRV, VRX, VSI instruction formats with the .insn
directive.

Review: Ulrich Weigand
Differential Revision: https://reviews.llvm.org/D88357
2020-10-05 16:53:13 +02:00
Sam Tebbs 2573cf3c3d [ARM]Fold select_cc(vecreduce_[u|s][min|max], x) into VMINV or VMAXV
This folds a select_cc or select(set_cc) of a max or min vector reduction with a scalar value into a VMAXV or VMINV.

    Differential Revision: https://reviews.llvm.org/D87836
2020-10-05 15:51:28 +01:00
Nicolas Vasilache 346b9d1772 [mlir][Linalg] Canonicalize TensorCastOp away when it feeds a LinalgOp.
This canonicalization is the counterpart of MemRefCastOp -> LinalgOp but on tensors.

This is needed to properly canonicalize post linalg tiling on tensors.

Differential Revision: https://reviews.llvm.org/D88729
2020-10-05 14:48:21 +00:00
Florian Hahn 348d85a6c7 [VPlan] Clean up uses/operands on VPBB deletion.
Update the code responsible for deleting VPBBs and recipes to properly
update users and release operands.

This is another preparation for D84680 & following patches towards
enabling modeling def-use chains in VPlan.
2020-10-05 14:43:52 +01:00
Simon Pilgrim 7a932f4f4c [Parser] ParseMicrosoftAsmStatement - Replace bit '|' operator with logical '||' operator. (PR47071)
Fixes static analysis warning.
2020-10-05 14:23:28 +01:00
Haojian Wu 1425c72236 [clangd] Add isKeyword function.
This will be used in rename for doing basic name validation.

Differential Revision: https://reviews.llvm.org/D88810
2020-10-05 15:11:24 +02:00
David Green ff86acbb79 [LV] Regenerate test. NFC
This just reruns the update script to add the new
[[LOOP0:!llvm.loop !.*]] checks to remove them from
other diffs.
2020-10-05 13:46:15 +01:00
Simon Pilgrim 2cd7b0e130 [ValueTracking] canCreateUndefOrPoison - use APInt to check bounds instead of getZExtValue().
Fixes OSS Fuzz #26135
2020-10-05 13:45:27 +01:00
Gabor Marton 007dd12d54 [ASTImporter][AST] Fix structural equivalency crash on dependent FieldDecl
Differential Revision: https://reviews.llvm.org/D88665
2020-10-05 14:06:09 +02:00
Carl Ritson 707c3d4d42 [AMDGPU][RegAlloc][SplitKit] Pre-commit test for D88821 2020-10-05 20:35:42 +09:00
Dmitry Preobrazhensky e70e7d1019 [TableGen] Added a function for identification of unsupported opcodes.
This change implements generation of a function which may be used by a backend to check if a given instruction is supported for a specific subtarget.

Reviewers: sdesmalen

Differential Revision: https://reviews.llvm.org/D88214
2020-10-05 14:23:41 +03:00
Haojian Wu 96c8a17c80 [clangd] Remove unused using-decls in TypeHierarchyTests, NFC. 2020-10-05 13:14:53 +02:00
Haojian Wu 7f05fe1aee [AST][RecoveryExpr] Fix a crash on undeduced type.
We should not capture the type if the function return type is undeduced.

Reviewed By: adamcz

Differential Revision: https://reviews.llvm.org/D87350
2020-10-05 12:52:04 +02:00
David Spickett 71cf97e95b Reland "[lldb] Don't send invalid region addresses to lldb server"
This reverts commit c65627a1fe.

The test immediately after the new invalid symbol test was
failing on Windows. This was because when we called
VirtualQueryEx to get the region info for 0x0,
even if it succeeded we would call GetLastError.

Which must have picked up the last error that was set while
trying to lookup "not_an_address". Which happened to be 2.
("The system cannot find the file specified.")

To fix this only call GetLastError when we know VirtualQueryEx
has failed. (when it returns 0, which we were also checking for anyway)

Also convert memory region to an early return style
to make the logic clearer.

Reviewed By: labath, stella.stamenova

Differential Revision: https://reviews.llvm.org/D88229
2020-10-05 11:50:29 +01:00
Sebastian Neubauer 6a089ce0e4 [AMDGPU] Use tablegen for argument indices
Use tablegen generic tables to get the index of image intrinsic
arguments.
Before, the computation of which image intrinsic argument is at which
index was scattered in a few places, tablegen, the SDag instruction
selection and GlobalISel. This patch changes that, so only tablegen
contains code to compute indices and the ImageDimIntrinsicInfo table
provides these information.

Differential Revision: https://reviews.llvm.org/D86270
2020-10-05 11:50:52 +02:00
Nicolas Vasilache d52211e384 [mlir] Fix SubViewOp doc in .td 2020-10-05 05:44:41 -04:00
Kazushi (Jam) Marukawa 5b5e78a431 [VE] Support register and frame-index pair correctly
Support register and frame-index pair correctly as operands of
generic load/store instrucitons, e.g. LD1BZXrri, STLrri, and etc.
Add regression tests also.

Differential Revision: https://reviews.llvm.org/D88779
2020-10-05 18:36:53 +09:00
Benjamin Kramer 6e2b267d1c Promote transpose from linalg to standard dialect
While affine maps are part of the builtin memref type, there is very
limited support for manipulating them in the standard dialect. Add
transpose to the set of ops to complement the existing view/subview ops.
This is a metadata transformation that encodes the transpose into the
strides of a memref.

I'm planning to use this when lowering operations on strided memrefs,
using the transpose to remove the stride without adding a dependency on
linalg dialect.

Differential Revision: https://reviews.llvm.org/D88651
2020-10-05 10:58:20 +02:00
Jay Foad 16778b19f2 [AMDGPU] Make bfe patterns divergence-aware
This tends to increase code size but more importantly it reduces vgpr
usage, and could avoid costly readfirstlanes if the result needs to be
in an sgpr.

Differential Revision: https://reviews.llvm.org/D88580
2020-10-05 09:55:10 +01:00
Jay Foad 0d5989bb24 [AMDGPU] Split R600 and GCN bfe patterns
This is in preparation for making the GCN patterns divergence-aware.
NFC.

Differential Revision: https://reviews.llvm.org/D88579
2020-10-05 09:55:10 +01:00
Gabriel Hjort Åkerlund 64b879ae2a [TableGen][GlobalISel] add handling of nested *_SUBREG
When nesting INSERT_SUBREG and EXTRACT_SUBREG, GlobalISelEmitter would
fail to find the register class of the nested node. This patch fixes
that for registers with subregs.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D88487
2020-10-05 10:42:18 +02:00
Haojian Wu 3423d5c9da [AST][RecoveryExpr] Popagate the error-bit from a VarDecl's initializer to DeclRefExpr.
The error-bit was missing, if a DeclRefExpr (which refers to a VarDecl
with a contains-errors initializer).

It could cause different violations in clang -- the DeclRefExpr is value-dependent,
but not contains-errors, `ABC<DeclRefExpr>` could produce a non-error
and non-dependent type in non-template context, which will lead to
crashes in constexpr evaluation.

Reviewed By: sammccall

Differential Revision: https://reviews.llvm.org/D86048
2020-10-05 10:35:29 +02:00
Markus Lavin a3caf7f610 [DebugInfo] Improve dbg preservation in LSR.
Use SCEV to salvage additional @llvm.dbg.value that have turned into
referencing undef after transformation (and traditional
salvageDebugInfo). Before transformation compute SCEV for each
@llvm.dbg.value in the loop body and store it (along side its current
DIExpression). After transformation update those @llvm.dbg.value now
referencing undef by comparing its stored SCEV to the SCEV of the
current loop-header PHI-nodes. Allow match with offset by inserting
compensation code in the DIExpression.

Fixes : PR38815

Differential Revision: https://reviews.llvm.org/D87494
2020-10-05 09:55:16 +02:00
Alexey Baturo cf4aa68388 [RISCV][ASAN] mark asan as supported for RISCV64 and enable tests
[11/11] patch series to port ASAN for riscv64

These changes allow using ASAN on RISCV64 architecture.
The majority of existing tests are passing. With few exceptions (see below).
Tests we run on qemu and on "HiFive Unleashed" board.

Tests run:

```
Asan-riscv64-inline-Test  - pass
Asan-riscv64-inline-Noinst-Test  - pass
Asan-riscv64-calls-Noinst-Test  - pass
Asan-riscv64-calls-Test  - pass
```

Lit tests:

```
RISCV64LinuxConfig (282 supported, few failures)
RISCV64LinuxDynamicConfig (289 supported, few failures)
```

Lit failures:

```
TestCases/malloc_context_size.cpp - asan works, but backtrace misses some calls
TestCases/Linux/malloc_delete_mismatch.cpp - asan works, but backtrace misses some calls
TestCases/Linux/static_tls.cpp - "Can't guess glibc version" (under debugging)
TestCases/asan_and_llvm_coverage_test.cpp - missing libclang_rt.profile-riscv64.a
```

These failures are under debugging currently and shall be addressed in a
subsequent commits.

Depends On D87581

Reviewed By: eugenis, vitalybuka

Differential Revision: https://reviews.llvm.org/D87582
2020-10-05 10:38:30 +03:00
Jonas Devlieghere a58b20e5a4 [llvm] Rename DwarfFile to DWARFFile to fix ODR violation (NFC)
Rename the DwarfFile class in DWARFLinker to DWARFFile. This is
consistent with the other DWARF classes and avoids a ODR violation with
the DwarfFile class in AsmPrinter.
2020-10-04 23:46:36 -07:00
Michał Górny e8beb6988b [lldb] [test/Register] Attempt to fix x86-fp-read.test on Darwin
Darwin seems to use stmmN instead of stN. Use a regex to accept both.

Also try to actually clear st(7).

Differential revision: https://reviews.llvm.org/D88795
2020-10-04 23:04:40 -07:00
Craig Topper b18026114a [X86] MWAITX_SAVE_RBX should not have EBX as an implicit use.
RBX was copied to a virtual register before this instruction
was created. And the EBX input for the final MWAITX is still
in a virtual register. So EBX isn't read by this pseudo.
2020-10-04 20:34:31 -07:00
David Blaikie 6d0be74af5 llvm-dwarfdump: Don't try to parse rnglist tables when dumping CUs
It's not possible to do this in complete generality - a CU using a
sec_offset DW_AT_ranges has no way of knowing where its rnglists
contribution starts, so should not attempt to parse any full rnglist
table/header to do so. And even using FORM_rnglistx there's no need to
parse the header - the offset can be computed using the CU's DWARF
format (32 or 64) to compute offset entry sizes, and then the list
parsed at that offset without ever trying to find a rnglist contribution
header immediately prior to the rnglists_base.
2020-10-04 19:18:14 -07:00
Yaxun (Sam) Liu e372c1d762 [HIP] Fix -fgpu-allow-device-init option
The option needs to be passed to both host and device compilation.

Differential Revision: https://reviews.llvm.org/D88550
2020-10-04 22:13:05 -04:00
Yaxun (Sam) Liu 5b551b79d3 [HIP] Fix default output file for -E
By convention the default output file for -E is "-" (stdout).
This is expected by tools like ccache, which uses output
of -E to determine if a file and its dependence has changed.

Currently clang does not use stdout as default output file for -E
for HIP, which causes ccache not working.

This patch fixes that.

Differential Revision: https://reviews.llvm.org/D88730
2020-10-04 22:03:16 -04:00
Yaxun (Sam) Liu 9756a402f2 Recommit "[HIP] Add option --gpu-instrument-lib="
recommit 64f7790e7d after
fixing hip-device-libs.hip.
2020-10-04 21:41:43 -04:00
Yaxun (Sam) Liu fef0ebbc0b Revert "[HIP] Add option --gpu-instrument-lib="
This reverts commit 64f7790e7d due
to regression in hip-device-libs.hip.
2020-10-04 21:27:29 -04:00
Yaxun (Sam) Liu 64f7790e7d [HIP] Add option --gpu-instrument-lib=
Add an option --gpu-instrument-lib= to allow users to specify
an instrument device library. This is for supporting -finstrument
in device code for debugging/profiling tools.

Differential Revision: https://reviews.llvm.org/D88557
2020-10-04 21:16:36 -04:00
David Blaikie 92c45e4ee2 llvm-dwarfdump: Add support for DW_RLE_startx_endx 2020-10-04 17:50:43 -07:00
Craig Topper 4b38ceb0eb [X86] Remove MWAITX_SAVE_EBX pseudo instruction. Always save/restore the full %rbx register even in gnux32.
ebx/rbx only needs to be saved when 64-bit registers are supported
anyway. It should be fine to save/restore the whole rbx register
even in gnux32 where the base is technically just ebx.

This matches what we do for cmpxchg16b where rbx is saved/restored
regardless of gnux32.
2020-10-04 16:28:15 -07:00
David Blaikie 628a319475 llvm-dwarfdump: Print addresses in debug_line to the parsed address size 2020-10-04 16:05:49 -07:00
Yuanfang Chen 2c94d88e07 [NewPM] collapsing nested pass mangers of the same type
This is one of the reason for extra invalidations in D84959. In
practice, I don't think we have use cases needing this. This simplifies
the pipeline a bit and prune corner cases when considering
invalidations.

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D85676
2020-10-04 15:57:13 -07:00