ce4e629fdf
Add emulation methods for "ORR (immediate)" and "ORR (register)".
...
Add Encoding T3 of "MOV (register)" to EmulateMOVRdRm() method and fixed
some bugs in EmulateMOVRdImm() and EmulateMOVRdRm() methods.
llvm-svn: 125992
2011-02-18 23:41:11 +00:00
27d1032b60
Add code to emulate LDRB (literal) Arm instruction.
...
llvm-svn: 125975
2011-02-18 22:24:22 +00:00
d1fd6963f5
Add emulation methods for "ADC (immediate)" and "ADC (register)".
...
Plus add a helper method ReadCoreReg(uint32_t regnum, bool *success) to simplify
coding a bit.
llvm-svn: 125961
2011-02-18 21:13:05 +00:00
489517c4a4
Add code to emulate LDRB (immediate, Thumb) instruction.
...
llvm-svn: 125959
2011-02-18 21:06:04 +00:00
faba5dd4ae
Add emulation methods for "AND (immediate)" and "AND (register)".
...
Plus add macro definitions for APSR_C and APSR_V to simplify code.
llvm-svn: 125947
2011-02-18 19:32:20 +00:00
a1bf8db478
Add code to emulate LDR (register) Arm instruction.
...
llvm-svn: 125945
2011-02-18 18:52:37 +00:00
f401d69c85
Fix typo.
...
llvm-svn: 125812
2011-02-18 01:26:39 +00:00
fc9d00beb7
Add emulation of Encoding A1 "A8.6.6 ADD (register)" and "A8.6.5 ADD (immediate, ARM)".
...
llvm-svn: 125809
2011-02-18 01:22:22 +00:00
29c9b64096
Add code to emulate LDR (immediate,ARM) instruction.
...
llvm-svn: 125808
2011-02-18 00:55:53 +00:00
ae147cafa9
Finished renamings to make the emulation method names consistent case-wise.
...
llvm-svn: 125801
2011-02-18 00:07:39 +00:00
a18ae1ffde
Some renamings to make the emulation method names consistent case-wise.
...
llvm-svn: 125800
2011-02-18 00:02:28 +00:00
d4926266f3
Removed redundant entry EmulateTBB() (there's an existing one EmulateTB()) and fixed some typos
...
in section headings.
llvm-svn: 125796
2011-02-17 23:44:53 +00:00
2a7e05a3d7
Fix a bug in EmulateTB() (TBB, TBH) where the branch length should be "twice"
...
the value of the byte/halfword returned from the table.
llvm-svn: 125793
2011-02-17 23:27:44 +00:00
16443905f3
Add header declarations for the remaining instructions we need to
...
emulate, to cover those that can change the PC.
llvm-svn: 125791
2011-02-17 23:09:13 +00:00
34dd9ba9c7
Refactoring. Abstracted the set flags operation into its own helper method
...
WriteFlags() and renamed WriteCoreRegisterWithFlags() to WriteCoreRegOptionalFlags().
Modified the call sites to use the helper methods.
llvm-svn: 125788
2011-02-17 22:37:12 +00:00
fc5c19dec5
A8.6.6 ADD (register)
...
Renamed EmulateAddRdnRm() to EmulateAddReg(), and added Encoding T1 to it.
Where Encoding T2 can potentially modify the PC, causing a brnach.
llvm-svn: 125782
2011-02-17 22:03:29 +00:00
2789706059
Add EmulateTB() method to emulate "Table Branch Byte" and "Table Branch Halfword"
...
operations for Thumb2.
llvm-svn: 125767
2011-02-17 19:34:27 +00:00
032d2dd576
Add stubs for pseudocode functions "MemA[]" amd "MemU[]", corresponding to aligned
...
and unaligned memory accesses. The new stub functions are MemARead, MemAWrite,
MemURead, and MemUWrite. At the moment these stubs just call ReadMemoryUnsigned or
WriteMemoryUnsigned, but we can fill them out further later if we decide we need
more accurate emulation of the memory system.
Replaced all the direct calls to ReadMemoryUnsigned and WriteMemoryUnsigned in
EmulateInstructionARM.cpp with calls to the appropriate new stub function.
llvm-svn: 125766
2011-02-17 19:20:40 +00:00
0f60574fd7
Move Align(val, alignment) utility function to ARMUtils.h.
...
llvm-svn: 125753
2011-02-17 17:31:08 +00:00
e19e4fc8dc
Add comment for the helper method WriteCoreRegisterWithFlags().
...
llvm-svn: 125703
2011-02-17 01:49:00 +00:00
0c64b5bbb6
Refactoring. Wrap the following pseudocode from the ARM Architecture Reference Manul:
...
// if d == 15 then // Can only occur for encoding A1
// ALUWritePC(result); // setflags is always FALSE here
// else
// R[d] = result;
// if setflags then
// APSR.N = result<31>;
// APSR.Z = IsZeroBit(result);
// APSR.C = carry;
// // APSR.V unchanged
into a helper method WriteCoreRegisterWithFlags, and modified the existing methods
to take advantage of it.
Plus add two emulation methods (declaration only for now) for ORR (immediate) and ORR (register).
llvm-svn: 125701
2011-02-17 01:35:27 +00:00
4890c85e0a
Add emulation methods for ROR (immediate), ROR (register), and RRX.
...
Turns out that they can be funneled through the helper methods
EmulateShiftImm()/ EmulateShiftReg() as well.
Modify EmulateShiftImm() to handle SRType_ROR and SRType_RRX.
And fix a typo in the impl of utility Shift_C() in ARMUtils.h.
llvm-svn: 125689
2011-02-16 22:14:44 +00:00
eaf2e4fdf1
Add code to emulate STRB (Thumb) instruction.
...
llvm-svn: 125686
2011-02-16 20:22:22 +00:00
14571f4b67
Add encoding entries for LSL (immediate and register) and LSR (immediate and register) to
...
ARM and Thumb opcode tables.
llvm-svn: 125683
2011-02-16 19:27:43 +00:00
4b22e7e67a
Add tagging for EmulateLDRRtRnImm().
...
llvm-svn: 125671
2011-02-16 18:35:47 +00:00
0f03baa539
Minor comment change.
...
llvm-svn: 125634
2011-02-16 01:31:20 +00:00
22deaa5a1a
Add emulation methods for LSL (immediate), LSL (register), LSR (immediate), and LSR (register).
...
Create two helper methods EmulateShiftImm() and EmulateShiftReg() and have ASR, LSL, and LSR
delegate to the helper methods which take an extra ARM_ShifterType parameter.
The opcodes tables have not been updated yet to reflect these new entries.
llvm-svn: 125633
2011-02-16 01:27:54 +00:00
5b5396ba77
Add documentation tags for LDM/STM instruction families.
...
Add code to emulate STR (register) Arm instruction.
llvm-svn: 125623
2011-02-16 00:33:43 +00:00
a79703db79
Section heading for EmulateB().
...
llvm-svn: 125620
2011-02-16 00:17:18 +00:00
7484e4e337
Add section headings corresponding to some of the ARM/Thumb emulation methods for better documentation.
...
llvm-svn: 125618
2011-02-16 00:06:18 +00:00
531dbfa5d8
A8.6.14 ASR (register)
...
Add EmulateASRReg() Encodings T1, T2, and A1 to the opcodes tables.
llvm-svn: 125614
2011-02-15 23:22:46 +00:00
f199eea579
Add eContextRegisterLoad instruction emulation context.
...
Add code to emulate STR (Immediate, Thumb) instruction.
llvm-svn: 125610
2011-02-15 22:53:54 +00:00
514487e806
Made lldb_private::ArchSpec contain much more than just an architecture. It
...
now, in addition to cpu type/subtype and architecture flavor, contains:
- byte order (big endian, little endian)
- address size in bytes
- llvm::Triple for true target triple support and for more powerful plug-in
selection.
llvm-svn: 125602
2011-02-15 21:59:32 +00:00
f976896b83
Remove the "Register ®" parameter from the BXWritePC(), LoadWritePC(), and ALUWritePC()
...
methods of EmulateInstructionARM class. The context data structure should provide sufficient
information already.
llvm-svn: 125596
2011-02-15 21:08:58 +00:00
6f93f63955
Fix wrong mask and encoding for T2 of ASR (immediate).
...
llvm-svn: 125593
2011-02-15 20:14:02 +00:00
a4afff97ad
A8.6.14 ASR (immediate)
...
Add EmulateASRImm() Encodings T1, T2, and A1 to the opcodes tables.
llvm-svn: 125592
2011-02-15 20:10:55 +00:00
6e12e117d4
Add code to emulate STMIB Arm instruction.
...
llvm-svn: 125580
2011-02-15 18:42:15 +00:00
5e38f35fe3
Add code to emulate STMDB Arm instruction.
...
Add some bit-mask fixes to code for getting register bits for various LDM and STM instructions.
llvm-svn: 125578
2011-02-15 18:10:01 +00:00
ef55e4c174
Remove the unnecessary assignment of m_inst_cpsr inside EvaluateInstruction(),
...
because it's already been done within ReadInstruction().
llvm-svn: 125569
2011-02-15 17:31:33 +00:00
efb309619a
Add code to emulate the STMDA Arm instruction.
...
llvm-svn: 125542
2011-02-15 00:19:42 +00:00
557520b996
Add missing logic (if BadReg(d) then UNPREDICTABLE;) for Encoding T2 of EmulateMovRdImm().
...
llvm-svn: 125533
2011-02-14 23:33:58 +00:00
5623dc3559
Fix build warning (unused variable).
...
llvm-svn: 125531
2011-02-14 23:21:24 +00:00
eccad4d005
- Rearrange instruction emulation contexts to use a union for the
...
various types and numbers of arguments rather than trying to keep a
constant number of arguments for all the types.
- Also create a Register type within the instructions, to hold
register type and number.
- Modify EmulateInstructionArm.cpp to use the new register and context
types in all the instruction emulation functions.
- Add code to emulate the STM Arm instruction.
llvm-svn: 125528
2011-02-14 23:03:21 +00:00
c3ba12d8e8
Add entries for EmulateMovRdImm() -- "MOV (immediate)" -- Encodings T1 & T2 into g_thumb_opcodes
...
table. Modify EmulateInstructionARM::EvaluateInstruction() so that if the cpsr has changed
during evaluate instruction, we flush out the change into m_inst_cpsr in preparation for the next
instruction.
llvm-svn: 125524
2011-02-14 22:04:25 +00:00
86776147ff
Add impl for EmulateMvnRdImm() -- "MVN (immediate)". Plus zero out the arg0 field of
...
the context of eContextImmediate type, since the immediate value is known from the
argument value to WriteRegisterUnsigned() callback already.
llvm-svn: 125518
2011-02-14 20:39:01 +00:00
b3b8e0ffc2
Add entries for Encodings T1 and A1 of "MVN (immediate)" to g_arm_opcodes and g_thumb_opcodes
...
tables. The corresponding EmulateMvnRdImm() method impl is empty for now.
llvm-svn: 125425
2011-02-12 01:27:26 +00:00
1173fbdc4b
Add helper methods InITBlock() and LastInITBlock() to EmulateInstructionARM class
...
instead of calling out to m_it_session.InITBlock()/LastInITBlock(), which simplifies
the coding a bit.
llvm-svn: 125421
2011-02-12 00:50:05 +00:00
a222c04588
Add EmulateBXRm() ("Branch and Exchange") to both g_arm_opcodes and g_thumb_opcodes table.
...
llvm-svn: 125418
2011-02-12 00:10:51 +00:00
7b37670d56
- Add three more instruction contexts to EmulateInstruction:
...
eContextAdjustBaseRegister, eContextRegisterStore and
eContextWriteMemoryRandomBits.
- Implement a version of WriteBits32UnknownToMemory for writing to memory.
- Modify EmulateLDM, EmulateLDMDA, EmulateLDMDB and EmulateLDMIB to use the
eContextAdjustBaseRegister context when appropriate.
- Add code to emulate the STM/STMIA/STMEA Arm instruction.
llvm-svn: 125414
2011-02-11 22:49:54 +00:00
a61541663c
Add EmulateCmpRnRm() for Encodings T1 & T2 to the g_thumb_opcodes table to emulate
...
CMP (register) operations.
llvm-svn: 125413
2011-02-11 21:53:58 +00:00
c6ca7bb67a
Rearraned some emulate instruction entries under the appropriate category.
...
llvm-svn: 125405
2011-02-11 21:23:32 +00:00
f1075ce0e6
Handle the case of interworking branch for EmulateLDMDA.
...
llvm-svn: 125392
2011-02-11 19:37:03 +00:00
298251cd9b
Add Thumb2 LDR (literal) instruction into the g_thumb_opcodes table.
...
Change the method name from *LDRRdPCRelative to *LDRRtPCRelative to be compliant
with the ARM Arch Manual which uses Rt for the destination register.
llvm-svn: 125390
2011-02-11 19:12:30 +00:00
bce7ad6b48
Fix build.
...
llvm-svn: 125379
2011-02-11 18:11:22 +00:00
485b4d8352
Add new instruction context, eContextWriteRegisterRandomBits.
...
Add new utility function, WriteBits32Unknown
Modify the LDM* instruction emulation functions to call WriteBits32Unknown.
Add missing overview comments to the LDM* instruction emulation functions.
Add code to emulate LDMDA Arm instruction.
llvm-svn: 125377
2011-02-11 17:59:55 +00:00
c7af6fe3bd
Add an entry for CMP (immediate) (Encoding T1) to the g_thumb_opcodes table.
...
llvm-svn: 125333
2011-02-11 02:02:56 +00:00
37c48b02a4
Add a helper method AddWithCarry() to the EmulateInstructionARM class.
...
llvm-svn: 125329
2011-02-11 01:29:53 +00:00
c843a78efc
Namings are important. Renamed Bits32(const uint32_t val, uint32_t bit) to Bit32(val, bit) and
...
SetBits32(uint32_t &bits, uint32_t bit, uint32_t val) to SetBit32(bits, bit, val).
llvm-svn: 125312
2011-02-10 21:39:01 +00:00
101f6efb8a
Some refactorings to use the convenience function: Bits32(const uint32_t value, const uint32_t bit).
...
llvm-svn: 125303
2011-02-10 19:54:05 +00:00
992b48c4be
Add some comment markers.
...
llvm-svn: 125302
2011-02-10 19:40:42 +00:00
0cfda5bbb5
Add a generic EmulateMovRdRm() method and modify/add entries to the g_thumb_opcodes
...
table. Also add some more defines and convenience functions.
llvm-svn: 125300
2011-02-10 19:29:03 +00:00
77224a5422
Rearrange the order of g_thumb_opcodes entries.
...
llvm-svn: 125295
2011-02-10 18:13:23 +00:00
cc13e4c62e
Add EmulateLDRRtRnImm() for EncodingT1 of LDR (immediate, Thumb) to the g_thumb_opcodes table,
...
and a helper method UnalignedSupport().
llvm-svn: 125258
2011-02-10 01:52:38 +00:00
1cabebe7bc
Add a new member variable m_new_inst_cpsr to catch the to-be-updated state
...
of the CPSR during the course of executing an opcode, and modified SelectInstrSet()
to update this variable instead of the original m_inst_cpsr, which should be
the cached copy of the CPSR at the beginning of executing the opcode.
llvm-svn: 125244
2011-02-09 23:59:17 +00:00
edf55ae52a
Add EmulateAddRdnRm() for EncodingT2 of ADD(register) to the g_thumb_opcodes table,
...
and a helper method ALUWritePC(Context&, uint32_t).
llvm-svn: 125241
2011-02-09 23:43:29 +00:00
0ce4a83c44
Modified existing Emulate* methods to call LoadWritePC(context, data) where appropriate to
...
effect an interworking branch if the ArchVersion() is ARMv5T and above.
llvm-svn: 125227
2011-02-09 22:02:17 +00:00
8bba644bf4
Modified EmulatePop impl to use the helper method LoadWritePC(context, data) since if PC
...
is in the list of registers to be load and we're in ARMv5T and above, this is an interworking branch.
llvm-svn: 125212
2011-02-09 19:30:49 +00:00
cc707657f9
If the CPSR is changed due to switching between ARM and Thumb ISETSTATE,
...
we want to record it and issue a WriteRegister callback so the clients
can track the mode changes accordingly.
llvm-svn: 125209
2011-02-09 19:11:32 +00:00
000aeb89ae
Patch from Kirk Beitz to make things compile on MinGW minus the putenv part.
...
llvm-svn: 125199
2011-02-09 17:41:27 +00:00
7eaacc517b
Add some helper methods to the EmulateInstructionARM class as a first step in the
...
refactorings of EmulateInstructionARM.cpp file, which will be modified later to
take advantage of these helper methods.
llvm-svn: 125148
2011-02-09 01:00:31 +00:00
123b89b67f
Add code to emulate the LDMIB Arm instruction.
...
Modify code for LDM and LDMDB instructions to only
create one context and to reuse it, rather than
creating multiple contexts.
llvm-svn: 125139
2011-02-08 23:56:10 +00:00
108a363318
Fix typos.
...
llvm-svn: 125138
2011-02-08 23:49:37 +00:00
03feace9d0
Add EmulateCB() entry to the g_thumb_opcodes table to represent "Compare and Branch
...
on NonZero and Compare and Branch on Zero" operations.
llvm-svn: 125134
2011-02-08 23:21:57 +00:00
cdb58e1236
Add code to emulate LDMDB Arm instruction.
...
llvm-svn: 125133
2011-02-08 23:16:02 +00:00
7aa01cfd64
Add code to emulate the LDM ARM instruction.
...
llvm-svn: 125118
2011-02-08 22:24:38 +00:00
181376f29f
Add missing implementation for "BL, BLX (immediate)" Encoding T1 and an entry for "bl <label>"
...
into g_thumb_opcodes table.
llvm-svn: 125112
2011-02-08 20:36:34 +00:00
86e48b6940
Add missing implementation for "BL, BLX (immediate)" Encoding A1.
...
llvm-svn: 125103
2011-02-08 18:58:31 +00:00
a3990398a3
Add implementation for EmulateInstructionARM::EmulateB() and fixed two typos in g_thumb_opcodes
...
as pointed out By Caroline. Refactored a little bit by adding two new helper methods to the
EmulateInstructionARM class:
o BranchWritePC()
o BXWritePC()
llvm-svn: 125059
2011-02-08 00:06:35 +00:00
05a975d777
Add EmulateInstructionARM::EmulateB entries to the g_arm_opcodes and g_thumb_opcodes
...
tables. EmulateB() has empty impl. and needs to be filled in later.
llvm-svn: 125048
2011-02-07 20:11:47 +00:00
95e314260e
Header patch, virtual dtor patch and missed UUID patch from Kirk Beitz.
...
llvm-svn: 124931
2011-02-05 02:56:16 +00:00
56902044a7
Handle the thumb branch instructions which have their cond bits embedded in the instruction stream.
...
llvm-svn: 124925
2011-02-05 01:39:52 +00:00
6e2acff0be
Add EmulateInstructionARM::EmulateIT() to the g_thumb_opcodes table,
...
to represent the the 'If Then' instruction which makes up to four following
instructions (the IT block)conditional.
Hook up ITSession utility class as a member variable of EmulateInstructionARM.
llvm-svn: 124915
2011-02-05 00:46:10 +00:00
ea745e86c8
Add a utility class ITSession to maintain the ITState for the Thumb ISA.
...
llvm-svn: 124906
2011-02-04 23:02:47 +00:00
b52193787d
Add EmulateInstructionARM::EmulateSVC() to the g_arm_opcodes and g_thumb_opcodes tables,
...
to represent the supervisor call instruction (previosuly software interrupt).
llvm-svn: 124840
2011-02-04 00:40:18 +00:00
d07a57f222
Add EmulateBLXImmediate() and EmulateBLXRm() to the g_arm_opcodes and g_thumb_opcodes tables,
...
which represent "bl <label>", "blx <label>", and "blx <Rm>" instructions.
llvm-svn: 124710
2011-02-02 01:13:56 +00:00
2684ccccda
Remove the 'lldb_private::' namespace resolution operator.
...
llvm-svn: 124671
2011-02-01 18:51:48 +00:00
3d9011d6dd
Add EmulateVPOP() to the g_arm_opcodes and g_thumb_opcodes tables, which represents
...
an operation to load multiple extension registers from the stack.
llvm-svn: 124670
2011-02-01 18:35:28 +00:00
c46f94d490
Cleaned up the EmulateInstructionARM to have the evaluate instruction
...
callbacks use member functions.
llvm-svn: 124636
2011-02-01 00:49:32 +00:00
c1dfd93e1e
Made the EmulateInstruction class into a plug-in interface and moved the
...
source files around into the places they need to go.
llvm-svn: 124631
2011-02-01 00:04:43 +00:00
Johnny Chen