Commit Graph

5334 Commits

Author SHA1 Message Date
thomasraoux 3fc0fbefc8 [mlir][vector] Move transferOp on tensor opt to folder/canonicalization
Move the existing optimization for transfer op on tensor to folder and
canonicalization. This handles the write after write case and read after write
and also add write after read case.

Differential Revision: https://reviews.llvm.org/D100597
2021-04-16 08:13:10 -07:00
Mats Petersson 517c3aee4d [OpenMP IRBuilder, MLIR] Add support for OpenMP do schedule dynamic
The implementation supports static schedule for Fortran do loops. This
implements the dynamic variant of the same concept.

Reviewed By: Meinersbur

Differential Revision: https://reviews.llvm.org/D97393
2021-04-16 16:09:49 +01:00
Javier Setoain b739bada9d [mlir][ArmSVE] Cleanup dialect registration
ArmSVE dialect is behind the recent changes in how the Vector dialect
interacts with backend vector dialects and the MLIR -> LLVM IR
translation module. This patch cleans up ArmSVE initialization within
Vector and removes the need for an LLVMArmSVE dialect.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D100171
2021-04-16 15:56:51 +02:00
Nicolas Vasilache caa159f044 [mlir][python] Add simple debugging and printing helpers
Differential Revision: https://reviews.llvm.org/D100643
2021-04-16 13:47:46 +00:00
Frederik Gossen c2c65585c5 [MLIR] Fix `isValidIndex`
Differential Revision: https://reviews.llvm.org/D100635
2021-04-16 14:58:54 +02:00
Frederik Gossen 3a5a610e27 [MLIR][Shape] Expose `getShapeVec` and add support for extent tensors
Differential Revision: https://reviews.llvm.org/D100636
2021-04-16 13:59:20 +02:00
Nicolas Vasilache b5f3a128bf [mlir][Python][Linalg] Add support for captures in body builder.
When Linalg named ops support was added, captures were omitted
from the body builder. This revision adds support for captures
which allows us to write FillOp in a more idiomatic fashion using
the _linalg_ops_ext mixin support.

This raises an issue in the generation of `_linalg_ops_gen.py` where
```
  @property
  def result(self):
    return self.operation.results[0] if len(self.operation.results) > 1 else None
```.
The condition should be `== 1`.

This will be fixed in a separate commit.

Differential Revision: https://reviews.llvm.org/D100363
2021-04-16 08:47:26 +00:00
Nicolas Vasilache 8cf650c554 [mlir][linalg] Add support for WAW fusion on tensors.
Differential Revision: https://reviews.llvm.org/D100603
2021-04-16 08:22:09 +00:00
Ahmed Taei 0e2f9b61fd Fix tile-and-pad when padding doesn't span all dimension
Without this tile-and-pad will never terminate if pad-fails.

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D97720
2021-04-15 20:17:40 -07:00
Prashant Kumar 102fd1cb8b Add support for numpy arrays to memref conversions.
This offers the ability to pass numpy arrays to the corresponding
memref argument.

Reviewed By: mehdi_amini, nicolasvasilache

Differential Revision: https://reviews.llvm.org/D100077
2021-04-15 23:41:26 +00:00
River Riddle 706c9c5ce0 [mlir] Add support for walking locations similarly to Operations
This allows for walking all nested locations of a given location, and is generally useful when processing locations.

Differential Revision: https://reviews.llvm.org/D100437
2021-04-15 16:09:34 -07:00
River Riddle 4efb7754e0 [mlir][NFC] Add a using directive for llvm::SetVector
Differential Revision: https://reviews.llvm.org/D100436
2021-04-15 16:09:34 -07:00
Aart Bik 916f3e16bd [mlir][vector][avx] add AVX dot product to X86Vector dialect with lowering
In the long run, we want to unify the dot product codegen solutions between
all target architectures, but this intrinsic enables experimenting with AVX
specific implementations in the meantime.

Reviewed By: nicolasvasilache

Differential Revision: https://reviews.llvm.org/D100593
2021-04-15 15:01:39 -07:00
River Riddle b1260109fb [mlir][AsmPrinter] Fix multi-threaded segfault by using explicit null stream per thread
We were using llvm::nulls, but that isn't thread safe so we switch to giving each thread it's own null stream.

Differential Revision: https://reviews.llvm.org/D100578
2021-04-15 12:26:59 -07:00
Alexander Belyaev cf761904a2 [mlir] Add verification for `linalg.tiled_loop` op.
Differential Revision: https://reviews.llvm.org/D100555
2021-04-15 20:50:36 +02:00
Alexander Belyaev 67f60bcc75 [mlir] Expose `updateBoundsForCyclicDistribution` in Linalg/Utils.h.
Differential Revision: https://reviews.llvm.org/D100580
2021-04-15 20:47:37 +02:00
River Riddle 94662ee0c1 [mlir] Add support for adding attribute+type traits/interfaces to tablegen defs
This matches the current support provided to operations, and allows attaching traits, interfaces, and using the DeclareInterfaceMethods utility. This was missed when attribute/type generation was first added.

Differential Revision: https://reviews.llvm.org/D100233
2021-04-15 11:41:51 -07:00
Aart Bik 92b0a9d7d4 [mlir][sparse] remove restriction on vectorization of index type
Rationale:
Now that vector<?xindex> is allowed, the restriction on vectorization
of index types in the sparse compiler can be removed. Also needs
generalization of scatter/gather index types.

Reviewed By: gysit

Differential Revision: https://reviews.llvm.org/D100522
2021-04-15 10:27:04 -07:00
Chia-hung Duan 6b0cef3e02 Refactor the architecture of mlir-reduce
Add iterator for ReductionNode traversal and use range to indicate the
region we would like to keep. Refactor the interaction between
Pass/Tester/ReductionNode.
Now it'll be easier to add new traversal type and OpReducer

Reviewed By: jpienaar, rriddle

Differential Revision: https://reviews.llvm.org/D99713
2021-04-14 13:40:44 -07:00
Mehdi Amini a33b647100 Revert "Refactor the architecture of mlir-reduce"
This reverts commit a32846b1d0.

The build is broken with -DBUILD_SHARED_LIBS=ON:

tools/mlir/lib/Reducer/CMakeFiles/obj.MLIRReduce.dir/Tester.cpp.o: In function `mlir::Tester::isInteresting(mlir::ModuleOp) const':
Tester.cpp:(.text._ZNK4mlir6Tester13isInterestingENS_8ModuleOpE+0xa8): undefined reference to `mlir::OpPrintingFlags::OpPrintingFlags()'
Tester.cpp:(.text._ZNK4mlir6Tester13isInterestingENS_8ModuleOpE+0xc6): undefined reference to `mlir::Operation::print(llvm::raw_ostream&, mlir::OpPrintingFlags)'
2021-04-14 19:25:43 +00:00
Jacques Pienaar a32846b1d0 Refactor the architecture of mlir-reduce
Add iterator for ReductionNode traversal and use range to indicate the region we would like to keep. Refactor the interaction between Pass/Tester/ReductionNode.
Now it'll be easier to add new traversal type and OpReducer

Reviewed By: jpienaar, rriddle

Differential Revision: https://reviews.llvm.org/D99713
2021-04-14 10:16:30 -07:00
Tobias Gysi ce82843f72 [mlir][linalg] update fusion to support linalg index operations.
The patch updates the linalg fusion pass to add the tile offsets to the indices.

Differential Revision: https://reviews.llvm.org/D100456
2021-04-14 15:32:42 +00:00
Hanhan Wang 7c4de2e9b9 [mlir][StandardToSPIRV] Add support for lowering memref<?xi1> to SPIR-V
Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D100452
2021-04-14 07:22:49 -07:00
Tres Popp d80178f7c1 [mlir] Change verification order to prevent null dereference
Differential Revision: https://reviews.llvm.org/D100390
2021-04-14 09:33:17 +02:00
Hanhan Wang d9b03ef2e8 [mlir][StandardToSPIRV] Add support for lowering math.powf to SPIR-V.
Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D100403
2021-04-13 22:36:47 -07:00
Mehdi Amini 597207a3c3 Expose parseXInDimensionList() to the `DialectAsmParser`
This allows custom types and attribute to parse a dimension list that
isn't necessarily terminated with `xtype`, for example something like:

#tf.shape<4x5>

Differential Revision: https://reviews.llvm.org/D100432
2021-04-14 02:07:34 +00:00
Arjun P eff067440e [MLIR] PresburgerSet subtraction: add documentation and assertion saying we don't support divisions yet
Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D100324
2021-04-14 05:56:35 +05:30
Sumesh Udayakumaran f56791ae2e [mlir] Prevent operations with users from being hoisted
This patch collects operations that have users in a for loop and uses
them  when loop invariant operations are detected and hoisted.

Reviewed By: bondhugula, vinayaka-polymage

Differential Revision: https://reviews.llvm.org/D99761
2021-04-13 15:29:17 -07:00
Rob Suderman 7e1fb9a0d2 [mlir][tosa] Add conv2d lowering to linalg.conv2d operator for FP
Handles lowering conv2d to linalg's convolution operator. This implementation
only supports floating point values but handles all strides, dilations, and
padding values.

Differential Revision: https://reviews.llvm.org/D100061
2021-04-13 13:26:02 -07:00
Lei Zhang 5b15fe9334 [mlir][spirv] Only attach struct offset for required storage classes
Per the SPIR-V spec "2.16.2. Validation Rules for Shader Capabilities":

  Composite objects in the StorageBuffer, PhysicalStorageBuffer,
  Uniform, and PushConstant Storage Classes must be explicitly
  laid out.

For other cases we don't need to attach the struct offsets.

Reviewed By: hanchung

Differential Revision: https://reviews.llvm.org/D100386
2021-04-13 15:30:30 -04:00
Eugene Zhulenev 8a316b00d6 [mlir] Convert async dialect passes from function passes to op agnostic passes
Differential Revision: https://reviews.llvm.org/D100401
2021-04-13 11:46:00 -07:00
Emilio Cota 0b63e3222b [mlir] X86Vector: Add AVX Rsqrt
Reviewed By: aartbik

Differential Revision: https://reviews.llvm.org/D99818
2021-04-13 08:43:48 -07:00
Tobias Gysi 8ea5d190ec [mlir][linalg] update tiling to support linalg index operations.
The patch updates the tiling pass to add the tile offsets to the indices returned by the linalg operations.

Differential Revision: https://reviews.llvm.org/D100379
2021-04-13 14:36:01 +00:00
Butygin eb31540066 [mlir] Canonicalize single-iteration ParallelOp
Differential Revision: https://reviews.llvm.org/D100248
2021-04-13 13:42:19 +03:00
Tobias Gysi ef30179eff [mlir][linalg] lower index operations during linalg to loop lowering.
The patch extends the linalg to loop lowering pass to replace all linalg index operations by the induction variables of the generated loop nests.

Differential Revision: https://reviews.llvm.org/D100364
2021-04-13 09:04:09 +00:00
KareemErgawy-TomTom aa6eb2af10 [MLIR][LinAlg] Implement detensoring cost-modelling.
This patch introduces the neccessary infrastructure changes to implement
cost-modelling for detensoring. In particular, it introduces the
following changes:
- An extension to the dialect conversion framework to selectively
convert sub-set of non-entry BB arguments.
- An extension to branch conversion pattern to selectively convert
sub-set of a branche's operands.
- An interface for detensoring cost-modelling.
- 2 simple implementations of 2 different cost models.

This sets the stage to explose cost-modelling for detessoring in an
easier way. We still need to come up with better cost models.

Reviewed By: silvas

Differential Revision: https://reviews.llvm.org/D99945
2021-04-13 09:07:18 +02:00
Eugene Zhulenev a6628e596e [mlir] Async: add automatic reference counting at async.runtime operations level
Depends On D95311

Previous automatic-ref-counting pass worked with high level async operations (e.g. async.execute), however async values reference counting is a runtime implementation detail.

New pass mostly relies on the save liveness analysis to place drop_ref operations, and does better verification of CFG with different liveIn sets in block successors.

This is almost NFC change. No new reference counting ideas, just a cleanup of the previous version.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D95390
2021-04-12 18:54:55 -07:00
Geoffrey Martin-Noble ae33eef505 [MLIR] Add a switch operation to the standard dialect
This is similar to the definition of llvm.switch, providing
unstructured branch-based control flow. It differs from the LLVM
operation in that it accepts any signless integer (not only an i32),
takes no branch weights (the same as the Branch and CondBranch ops),
and has a slightly different syntax for the default case that includes
it in the list of cases with an explicit `default` keyword.

Also included are several canonicalizers.

See https://llvm.discourse.group/t/rfc-add-std-switch-and-scf-switch/3090

Reviewed By: rriddle, bondhugula

Differential Revision: https://reviews.llvm.org/D99925
2021-04-12 18:46:02 -07:00
Lei Zhang 23b8264b52 [mlir][spirv] Fix runtime array stride when emulating bitwidth
The stride should be calculated with the converted array element
type, not the original input type.

Reviewed By: mravishankar

Differential Revision: https://reviews.llvm.org/D100337
2021-04-12 17:13:33 -04:00
Lei Zhang 2eb98d89ac [mlir][spirv] Allow bitwidth emulation on runtime arrays
Runtime arrays are converted from memrefs with unknown
dimensions.

Reviewed By: mravishankar

Differential Revision: https://reviews.llvm.org/D100335
2021-04-12 17:04:18 -04:00
Lei Zhang 0deeaaca39 [mlir] Move memref.subview patterns to MemRef/Transforms/
These patterns have been used as a prerequisite step for lowering
to SPIR-V. But they don't involve SPIR-V dialect ops; they are
pure memref/vector op transformations. Given now we have a dedicated
MemRef dialect, moving them to Memref/Transforms/, which is a more
suitable place to host them, to allow used by others.

This commit just moves code around and renames patterns/passes
accordingly. CMakeLists.txt for existing MemRef libraries are
also improved along the way.

Reviewed By: mravishankar

Differential Revision: https://reviews.llvm.org/D100326
2021-04-12 16:38:22 -04:00
Lei Zhang fd91f81c85 [mlir][spirv] Put debug-only variable in LLVM_DEBUG
This avoids paying the cost when building in release.

Reviewed By: hanchung

Differential Revision: https://reviews.llvm.org/D100325
2021-04-12 15:14:43 -04:00
eopXD 9cc417cbca [mlir][affine] Fix unfolded bounding maps for affine.for
Loop bounds of affine.for didn't perform foldings like affine.load, affine.store.
Bound maps shall be more composed, leaving most affine.apply become dead.

This resolves the bug listed on https://bugs.llvm.org/show_bug.cgi?id=45203

Differential Revision: https://reviews.llvm.org/D99323
2021-04-13 00:12:43 +05:30
Arjun P 7f9e36b209 [MLIR] PresburgerSet emptiness check: remove assertions that there are no symbols
Symbols are now supported in the integer emptiness check. Remove some outdated assertions checking that there are no symbols.

Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D100327
2021-04-12 23:11:06 +05:30
Aart Bik 7714b405a0 [mlir] introduce "encoding" attribute to tensor type
This CL introduces a generic attribute (called "encoding") on tensors.
The attribute currently does not carry any concrete information, but the type
system already correctly determines that tensor<8xi1,123> != tensor<8xi1,321>.
The attribute will be given meaning through an interface in subsequent CLs.

See ongoing discussion on discourse:

[RFC] Introduce a sparse tensor type to core MLIR
https://llvm.discourse.group/t/rfc-introduce-a-sparse-tensor-type-to-core-mlir/2944

A sparse tensor will look something like this:

```
// named alias with all properties we hold dear:
#CSR = {
  // individual named attributes
}

// actual sparse tensor type:
tensor<?x?xf64, #CSR>
```

I see the following rough 5 step plan going forward:

(1) introduce this format attribute in this CL, currently still empty
(2) introduce attribute interface that gives it "meaning", focused on sparse in first phase
(3) rewrite sparse compiler to use new type, remove linalg interface and "glue"
(4) teach passes to deal with new attribute, by rejecting/asserting on non-empty attribute as simplest solution, or doing meaningful rewrite in the longer run
(5) add FE support, document, test, publicize new features, extend "format" meaning to other domains if useful

Reviewed By: stellaraccident, bondhugula

Differential Revision: https://reviews.llvm.org/D99548
2021-04-12 10:37:15 -07:00
Emilio Cota 8508a63b88 [mlir] Rename AVX512 dialect to X86Vector
We will soon be adding non-AVX512 operations to MLIR, such as AVX's rsqrt. In https://reviews.llvm.org/D99818 several possibilities were discussed, namely to (1) add non-AVX512 ops to the AVX512 dialect, (2) add more dialects (e.g. AVX dialect for AVX rsqrt), and (3) expand the scope of the AVX512 to include these SIMD x86 ops, thereby renaming the dialect to something more accurate such as X86Vector.

Consensus was reached on option (3), which this patch implements.

Reviewed By: aartbik, ftynse, nicolasvasilache

Differential Revision: https://reviews.llvm.org/D100119
2021-04-12 19:20:04 +02:00
MaheshRavishankar b0fc712b14 [mlir][Linalg] Disable const -> linalg.generic when fused op is illegal.
Fusing a constant with a linalg.generic operation can result in the
fused operation being illegal since the loop bound computation
fails. Avoid such fusions.

Differential Revision: https://reviews.llvm.org/D100272
2021-04-12 10:15:54 -07:00
Tobias Gysi 93f9922d65 [mlir][linalg] adding operation to access the iteration index of enclosing linalg ops.
The `linalg.index` operation provides access to the iteration indexes of immediately enclosing linalg operations. It takes a dimension `dim` attribute and returns the iteration index in the given dimension. Having `linalg.index` allows us to unify `linalg.generic` and `linalg.indexed_generic` and also enables index access in named operations.

Differential Revision: https://reviews.llvm.org/D100292
2021-04-12 13:37:17 +00:00
Frederik Gossen e413b86a2c [MLIR][Shape] Combine `cstr_eq` only if they share shape operands
Differential Revision: https://reviews.llvm.org/D100198
2021-04-09 16:54:54 +02:00
Frederik Gossen 74d33052dd [MLIR][Shape] Add convenience builder for `shape.assuming_all`
Differential Revision: https://reviews.llvm.org/D100105
2021-04-09 12:17:34 +02:00