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94699 Commits

Author SHA1 Message Date
Argyrios Kyrtzidis 375584c7eb Clean up temporaries created by an asm statement. Fixes rdar://8540491 
llvm-svn: 117961
 2010-11-01 21:51:42 +00:00
Jakob Stoklund Olesen d7a824006e Add kill flag verification. 
At least X86FloatingPoint requires correct kill flags after register allocation,
and targets using register scavenging benefit. Conservative kill flags are not
enough.

llvm-svn: 117960
 2010-11-01 21:51:31 +00:00
Jakob Stoklund Olesen a5d4b4ffa2 Update kill flags while rewriting instructions after splitting. 
llvm-svn: 117959
 2010-11-01 21:51:29 +00:00
Bill Wendling 418bd53008 Move the machine operand MC encoding patterns to the parent classes. 
llvm-svn: 117956
 2010-11-01 21:17:06 +00:00
Bill Wendling 793af5fa07 Use ARM-style comments. 
llvm-svn: 117955
 2010-11-01 21:16:39 +00:00
Douglas Gregor 298087bc25 Harden Sema::MaybeBindTotemporary. 
llvm-svn: 117954
 2010-11-01 21:10:29 +00:00
Owen Anderson 6186c96765 When folding away a (shl (shr)) pair, we need to check that the bits that will BECOME the low 
bits are zero, not that the current low bits are zero.  Fixes <rdar://problem/8606771>.

llvm-svn: 117953
 2010-11-01 21:08:20 +00:00
Chris Lattner 865dd96f22 use our fancy new MnemonicAlias mechanism to remove a bunch of hacks 
from X86AsmParser.cpp

llvm-svn: 117952
 2010-11-01 21:06:34 +00:00
Fariborz Jahanian eb7714c290 Restore patch for PR8453 which was undone in r117829 
(was project bugs).

llvm-svn: 117951
 2010-11-01 20:47:16 +00:00
Bill Wendling c6627eec13 When we look at instructions to convert to setting the 's' flag, we need to look 
at more than those which define CPSR. You can have this situation:

(1)  subs  ...
(2)  sub   r6, r5, r4
(3)  movge ...
(4)  cmp   r6, 0
(5)  movge ...

We cannot convert (2) to "subs" because (3) is using the CPSR set by
(1). There's an analogous situation here:

(1)  sub   r1, r2, r3
(2)  sub   r4, r5, r6
(3)  cmp   r4, ...
(5)  movge ...
(6)  cmp   r1, ...
(7)  movge ...

We cannot convert (1) to "subs" because of the intervening use of CPSR.

llvm-svn: 117950
 2010-11-01 20:41:43 +00:00
Johnny Chen ab9c1dd9ba Replace the two call sites of inspect.getsource(obj) with a utility function 
getsource_if_available(obj) which also handles the exception if it occurs.

llvm-svn: 117949
 2010-11-01 20:35:01 +00:00
Greg Clayton 4b3dc10e65 Fixed globals not showing up for any but the first compile unit due to a 
mismatch: I was using the compile unit user ID (the compile unit offset in
the DWARF) as the compile unit index.

llvm-svn: 117948
 2010-11-01 20:32:12 +00:00
Sean Callanan 57bbc6ecc6 Print notes for expressions as well as errors 
and warnings.

llvm-svn: 117947
 2010-11-01 20:28:09 +00:00
Douglas Gregor 9aaf7f66fc Do not compare invalid source locations 
llvm-svn: 117946
 2010-11-01 20:13:04 +00:00
Jakob Stoklund Olesen ba9a4985a2 Don't assign new registers created during a split to the same stack slot, but 
give them individual stack slots once the are actually spilled.

llvm-svn: 117945
 2010-11-01 19:49:57 +00:00
Jakob Stoklund Olesen 31fffb62d9 Add basic LiveStacks verification. 
When an instruction refers to a spill slot with a LiveStacks entry, check that
the spill slot is live at the instruction.

llvm-svn: 117944
 2010-11-01 19:49:52 +00:00
Argyrios Kyrtzidis ca76629618 Emit error when using a bound member function for something other than calling it. 
Also avoids IRGen crashes due to accepting invalid code.

llvm-svn: 117943
 2010-11-01 18:49:26 +00:00
Douglas Gregor b524d906fe Require that the types of the parameters of a block literal are complete. 
llvm-svn: 117942
 2010-11-01 18:37:59 +00:00
Owen Anderson cd9da22f68 Use ARM-style comment syntax. 
llvm-svn: 117941
 2010-11-01 18:33:37 +00:00
Bob Wilson 44be217af1 NEON does not support truncating vector stores. Radar 8598391. 
llvm-svn: 117940
 2010-11-01 18:31:39 +00:00
Owen Anderson 083ddf7d6a Covert this test to .s form. 
llvm-svn: 117939
 2010-11-01 18:30:39 +00:00
Owen Anderson a7d985738c Convert this test to .s form. 
llvm-svn: 117938
 2010-11-01 18:26:43 +00:00
Owen Anderson e5271a935a Covert this test to .s form. 
llvm-svn: 117937
 2010-11-01 18:13:11 +00:00
Jim Grosbach 7d45c101e5 Add FIXME. 
llvm-svn: 117936
 2010-11-01 18:11:14 +00:00
Owen Anderson 051b7893dd Covert this test to .s form. 
llvm-svn: 117935
 2010-11-01 18:03:16 +00:00
Johnny Chen 7e329d0d2a Add keyboard shortcuts: 
'thread backtrace'     => Control-C b (gud-bt)     "Show stack for the current thread."
'thread backtrace all' => Control-C B (gud-bt-all) "Show stacks for all the threads."

Change the function name of one existing shortcut:

'breakpoint list"      => Control-C l (gud-listb)  "List all breakpoints."

llvm-svn: 117933
 2010-11-01 17:29:38 +00:00
Rafael Espindola 55ebc962ab Fix test. 
llvm-svn: 117932
 2010-11-01 17:10:53 +00:00
Jim Grosbach fddf36d254 Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gates 
codegen using the patterns; the latter gates the assembler recognizing the
instruction.

llvm-svn: 117931
 2010-11-01 17:08:58 +00:00
Rafael Espindola 13ddd6d410 Write the line info to .debug_line. 
llvm-svn: 117930
 2010-11-01 17:07:14 +00:00
Jim Grosbach 0190a649e8 Mark ARM subtarget features that are available for the assembler. 
llvm-svn: 117929
 2010-11-01 16:59:54 +00:00
Devang Patel 86f30f5a1d Simplify. Builtin types' context is always implied. 
llvm-svn: 117928
 2010-11-01 16:52:40 +00:00
Jim Grosbach 99710a871c trailing whitespace 
llvm-svn: 117927
 2010-11-01 16:44:21 +00:00
Johnny Chen 2e1615ea8e Change the README to reflect the new the screen shot file name lldb-gud-window.png. 
llvm-svn: 117926
 2010-11-01 16:39:24 +00:00
Rafael Espindola 72b5488680 Move EmitInstruction to MCObjectStreamer so that ELF and MachO can share it. 
llvm-svn: 117925
 2010-11-01 16:27:31 +00:00
Johnny Chen 6713a9b317 Python API changes: SBValue.IsPtrType() -> SBValue.IsPointerType(). 
SBFrame print representation: idx: 0 -> #0

llvm-svn: 117924
 2010-11-01 16:08:47 +00:00
Jim Grosbach 5b373341fc The T2 extract/pack instructions are only valid in Thumb2 mode. Mark the 
patterns as such

llvm-svn: 117923
 2010-11-01 15:59:52 +00:00
Rafael Espindola 144fb8af58 Add support for .value. 
llvm-svn: 117922
 2010-11-01 15:29:07 +00:00
Anders Carlsson 09814d3f3a Don't update empty field subobjects for bitfields. Fixes PR8519. 
llvm-svn: 117921
 2010-11-01 15:14:51 +00:00
Douglas Gregor f09b6c9c85 Plug a leak in the preprocessing record's handling of inclusion 
directives. We had a std::string in an object that was allocated via a
BumpPtrAllocator.

llvm-svn: 117912
 2010-11-01 15:03:47 +00:00
Rafael Espindola 1614597873 Implement .weakref. 
llvm-svn: 117911
 2010-11-01 14:28:48 +00:00
Douglas Gregor 1cbdd951e8 Disable some timing code 
llvm-svn: 117910
 2010-11-01 13:48:43 +00:00
Zhongxing Xu e1dbeb28da Explicitly handle CXXBindTemporaryExpr, CXXFunctionalCastExpr, 
and ImplicitCastExpr to propagate asLValue AddStmtChoice property.
But do not propagate AlwaysAdd property.

llvm-svn: 117909
 2010-11-01 13:04:58 +00:00
Zhongxing Xu 627a1868d2 Now initializer of C++ record type is visited as block-level expr. 
Let the destination of AggExprVisitor be an explicit MemRegion. 
Reenable the test case.

llvm-svn: 117908
 2010-11-01 09:09:44 +00:00
Zhongxing Xu 0b51d4db8c Make all CXXConstructExpr's block-level expressions. This is required by 
method inlining. Temporarily fail a test case.

llvm-svn: 117907
 2010-11-01 06:46:05 +00:00
Bill Wendling 2623343625 Move instruction encoding bits into the parent class and remove the temporary 
*_Encode classes. These instructions are the only ones which use those classes,
so a subclass isn't necessary.

llvm-svn: 117906
 2010-11-01 06:00:39 +00:00
Bill Wendling 359dd0c6bd More tests to XFAIL. The arm-and-txt-peephole.ll test passes even when the 
peephole optimizer is disabled. That's not good at all.

llvm-svn: 117905
 2010-11-01 05:59:43 +00:00
Bill Wendling 7a23c1fb7d The testcase is now XFAILed. Sorry about the breakage. 
llvm-svn: 117904
 2010-11-01 05:50:55 +00:00
Bill Wendling cd4750cb4d Disable because peephole is disabled. 
llvm-svn: 117903
 2010-11-01 05:48:44 +00:00
Chris Lattner 1acd6b1edc "mov[zs]x (mem), GR16" are not ambiguous: the mem 
must be 8 bits.  Support this memory form.

llvm-svn: 117902
 2010-11-01 05:41:10 +00:00
Chris Lattner dd3b09c234 Implement enough of the missing instalias support to get 
aliases installed and working.  They now work when the
matched pattern and the result instruction have exactly
the same operand list.

This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://8017633 and PR7459.

Note that we do not accept instructions like:
  movzx 0(%rsp), %rsi

GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand.  It could be 8/16/32 bits.

llvm-svn: 117901
 2010-11-01 05:34:34 +00:00