Commit Graph

201945 Commits

Author SHA1 Message Date
Simon Atanasyan e62aa7457f [Mips] Add Elf_Mips_Options::getRegInfoDesc() function to retrieve an ODK_REGINFO descriptor
No functional changes.

llvm-svn: 238176
2015-05-26 06:05:07 +00:00
Simon Atanasyan e09faec16e [Mips] Make the code shorter - use LLVM_ELF_IMPORT_TYPES_ELFT macro
No functional changes.

llvm-svn: 238175
2015-05-26 06:05:01 +00:00
Vince Harron ebf2b2a10b revert files unintentionally checked in
llvm-svn: 238174
2015-05-26 03:10:41 +00:00
Vince Harron 218353d847 Print port number that lldb-server binds to in platform mode
If binding to port 0 is selected, the actual port is printed.

This improves the reliability of platform startup by ensuring that
a free port can be found.

TEST PLAN
./lldb-server platform --listen *:0

Listening for a connection from <port-number>...

Will appear on stdout (with other stuff potentially)

llvm-svn: 238173
2015-05-26 03:08:05 +00:00
Rafael Espindola 64acc7fcc7 Remove most uses of MCSectionData from MCAssembler.
llvm-svn: 238172
2015-05-26 02:17:21 +00:00
Rafael Espindola 5a1e80bc43 Stop using MCSectionData in MCAsmLayout.h.
llvm-svn: 238170
2015-05-26 02:00:36 +00:00
Davide Italiano 683703ea6d [ELF] Add support for -z origin/now options.
Differential Revision:	http://reviews.llvm.org/D9963

llvm-svn: 238169
2015-05-26 01:57:32 +00:00
Rafael Espindola 0a415bf28d Delete dead code.
llvm-svn: 238168
2015-05-26 01:56:56 +00:00
Rafael Espindola ed34d58c09 Move MCSection destruction to MCContext::reset.
Fixes the leaks when running llc.

Also found by an asan bot.

llvm-svn: 238167
2015-05-26 01:52:19 +00:00
David Majnemer 7a3ce0c537 [MS ABI] Implement restrict qualified references
MSVC 2015 supports '__restrict' qualified reference types.

llvm-svn: 238166
2015-05-26 01:30:45 +00:00
Rafael Espindola 61e724a8c5 Stop using MCSectionData in MCMachObjectWriter.h.
llvm-svn: 238165
2015-05-26 01:15:30 +00:00
Rafael Espindola 009e5fa7cb Remove dead forward declaration.
llvm-svn: 238164
2015-05-26 00:55:28 +00:00
Rafael Espindola 079027ea90 Stop using MCSectionData in MCExpr.h.
llvm-svn: 238163
2015-05-26 00:52:18 +00:00
Rafael Espindola 7549f87672 Return a MCSection from MCFragment::getParent().
Another step in merging MCSectionData and MCSection.

llvm-svn: 238162
2015-05-26 00:36:57 +00:00
Rafael Espindola 24d285d31b Call the destructors of the MCSections.
They now contain the fragments. If we don't call the destructors the
fragments leak.

Found by an asan bot.

llvm-svn: 238161
2015-05-26 00:32:28 +00:00
Rafael Espindola 8324c2f8be Store a MCSection in MCFragment.
Part of the work to merge MCSectionData into MCSection.

llvm-svn: 238160
2015-05-25 23:48:22 +00:00
Rafael Espindola a554c05d95 Turn MCSectionData into a field of MCSection.
This also changes MCAssembler to store a vector of MCSections instead of an
iplist of MCSectionData.

llvm-svn: 238159
2015-05-25 23:14:17 +00:00
Rafael Espindola 09266bad7f Move MCSectionData to MCSection.h.
Another step in merging MCSectionData and MCSection.

llvm-svn: 238158
2015-05-25 22:57:48 +00:00
Rafael Espindola 4f09478614 Remove dead code. NFC.
llvm-svn: 238157
2015-05-25 22:07:33 +00:00
Rafael Espindola 08850b3a88 Make a few MCSectionELF& variables const. NFC.
This just reduces the noise from another patch.

llvm-svn: 238156
2015-05-25 21:56:55 +00:00
Rafael Espindola 25ffbe17c9 Insert MCSectionData into the section list directly in getOrCreateSectionData.
Removing the logic from the constructor will make it easier to merge
MCSectionData and MCSection.

llvm-svn: 238155
2015-05-25 20:39:23 +00:00
Craig Topper 042a39274a Use range-based for loops. NFC.
llvm-svn: 238154
2015-05-25 20:01:18 +00:00
Andrey Churbanov 7af7c8df31 fixed missed arch renaming (from C.Bergstrom)
llvm-svn: 238153
2015-05-25 20:01:16 +00:00
Bjorn Steinbrink 236446cd4c Remove conflicting attributes before adding deduced readonly/readnone
Summary:
In case of functions that have a pointer argument and only pass it to
each other, the function attributes pass deduces that the pointer should
get the readnone attribute, but fails to remove a readonly attribute
that may already have been present.

Reviewers: nlewycky

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9995

llvm-svn: 238152
2015-05-25 19:46:38 +00:00
Davide Italiano f071bd0a18 [llvm-readobj/ELF] Teach how to decode DF_1_XXX flags
llvm-readobj -dynamic-table output.
Before:
0x000000006FFFFFFB unknown

After:
0x000000006FFFFFFB FLAGS_1 NOW ORIGIN

Differential Revision:	http://reviews.llvm.org/D9958

llvm-svn: 238151
2015-05-25 19:12:18 +00:00
Rafael Espindola cd62518369 Move HasInstructions to MCSection.
llvm-svn: 238150
2015-05-25 18:34:26 +00:00
Simon Pilgrim 0be4fa761f [X86][AVX2] Vectorized i16 shift operators
Part of D9474, this patch extends AVX2 v16i16 types to 2 x 8i32 vectors and uses i32 shift variable shifts before packing back to i16.

Adds AVX2 tests for v8i16 and v16i16 

llvm-svn: 238149
2015-05-25 17:49:13 +00:00
Tom Stellard 50828163a1 R600/SI: Remove some unnecessary patterns from VINTRP multiclass
DisableEncoding and Constraints can be set using let statements around
the multiclass defs.

llvm-svn: 238148
2015-05-25 16:15:56 +00:00
Tom Stellard ec87f841c6 R600/SI: Fix bug with v_interp_p1_f32 instructions on 16 bank lds chips
The src and dst register cannot be the same on chips with 16 lds banks.

llvm-svn: 238147
2015-05-25 16:15:54 +00:00
Tom Stellard c70cf90d09 R600/SI: Use NAME rather than opName as the key to the MCOpcode tables
This lets us drop a parameter the opName parameter to the VINTRP
multiclass and makes it possible to create multiple VINTRP defs
with the same asm mnemonic.

llvm-svn: 238146
2015-05-25 16:15:50 +00:00
Kit Barton 5944ee2179 This patch adds support for the vector quadword add/sub instructions introduced
in POWER8.

These are the Clang-related changes for http://reviews.llvm.org/D9081

vadduqm
vaddeuqm
vaddcuq
vaddecuq
vsubuqm
vsubeuqm
vsubcuq
vsubecuq
All builtins are added in altivec.h, and guarded with the POWER8_VECTOR and
powerpc64 macros.



http://reviews.llvm.org/D9903

llvm-svn: 238145
2015-05-25 15:52:45 +00:00
Kit Barton 6646033e6e This patch adds support for the vector quadword add/sub instructions introduced
in POWER8:

vadduqm
vaddeuqm
vaddcuq
vaddecuq
vsubuqm
vsubeuqm
vsubcuq
vsubecuq
In addition to adding the instructions themselves, it also adds support for the
v1i128 type for intrinsics (Intrinsics.td, Function.cpp, and
IntrinsicEmitter.cpp).

http://reviews.llvm.org/D9081

llvm-svn: 238144
2015-05-25 15:49:26 +00:00
Rafael Espindola b028cc8098 Move bundle info from MCSectionData to MCSection.
llvm-svn: 238143
2015-05-25 15:04:26 +00:00
Rafael Espindola c1cd944854 Add a isBundleLocked helper to MCELFStreamer.
llvm-svn: 238142
2015-05-25 14:57:35 +00:00
Rafael Espindola b2ac19ed6e Move LayoutOrder to MCSection.
llvm-svn: 238141
2015-05-25 14:25:28 +00:00
Rafael Espindola 0f5b006e3c Use a simple initial value for the ordinal.
The odd value was only used by the ELF writer to check if the section was one
that it had created.

llvm-svn: 238140
2015-05-25 14:18:24 +00:00
Rafael Espindola 6e6820a7e6 Stop forwarding getOrdinal and setOrdinal.
llvm-svn: 238139
2015-05-25 14:12:48 +00:00
Rafael Espindola 3422d77c50 Use default member initializes. NFC.
llvm-svn: 238138
2015-05-25 14:04:31 +00:00
Rafael Espindola 1f02022027 Move Ordinal from MCSectionData to MCSection. NFC.
Part of the work to merge MCSectionData and MCSection.

llvm-svn: 238137
2015-05-25 14:00:56 +00:00
Rafael Espindola e7134b2d78 Simplify boolean conditional return statements.
Patch by Richard <legalize@xmission.com>

llvm-svn: 238134
2015-05-25 13:50:21 +00:00
Benjamin Kramer 68a29562f9 Refactor: Simplify boolean conditional return statements in llvm/lib/DebugInfo/DWARF
Use clang-tidy to simplify boolean conditional return statements. Patch by
Richard Thomson <legalize@xmission.com>!

Differential Revision: http://reviews.llvm.org/D9972

llvm-svn: 238132
2015-05-25 13:28:03 +00:00
Michael Kuperstein f145228676 [X86] When pattern-matching scalar FMA3 intrinsics, don't re-arrange the first and second operands.
The semantics of the scalar FMA intrinsics are that the high vector elements are copied from the first source.
The existing pattern switches src1 and src2 around, to match the "213" order, which ends up tying the original src2 to the dest. Since the actual scalar fma3 instructions copy the high elements from the dest register, the wrong values are copied.

This modifies the pattern to leave src1 and src2 in their original order.

Differential Revision: http://reviews.llvm.org/D9908

llvm-svn: 238131
2015-05-25 12:35:25 +00:00
Elena Demikhovsky 1c1391ba24 Added promotion to EXTRACT_SUBVECTOR operand.
I encountered with this case in one of KNL tests for i1 vectors.
v16i1 = EXTRACT_SUBVECTOR v32i1, x

llvm-svn: 238130
2015-05-25 11:33:13 +00:00
Alexander Musman 6b080fcda5 Bug fix for PR23577 (https://llvm.org/bugs/show_bug.cgi?id=23577#c0).
"1-4" specifiers are returned as numeric constants, not identifiers,
and should be treated as such. Currently pragma handler incorrectly
assumes that they are returned as identifiers.

Patch by Andrey Bokhanko.

Differential Revision: http://reviews.llvm.org/D9856

llvm-svn: 238129
2015-05-25 11:21:20 +00:00
Greg Clayton 654e0ca650 Quiet compiler warnings about virtual and override not being consistent.
llvm-svn: 238128
2015-05-25 02:58:29 +00:00
Greg Clayton 5cf342d7aa Fix compiler warnings regarding size_t not always being 64 bit in the printf.
llvm-svn: 238127
2015-05-25 02:55:21 +00:00
NAKAMURA Takumi 5582a6a4a5 Reformat.
llvm-svn: 238126
2015-05-25 01:43:34 +00:00
NAKAMURA Takumi fb3bd7127a Prune CRLFs.
llvm-svn: 238125
2015-05-25 01:43:23 +00:00
Chandler Carruth 04cc665cef [Unroll] Switch from an eagerly populated SCEV cache to one that is
lazily built.

Also, make it a much more generic SCEV cache, which today exposes only
a reduced GEP model description but could be extended in the future to
do other profitable caching of SCEV information.

llvm-svn: 238124
2015-05-25 01:00:46 +00:00
Duncan P. N. Exon Smith b2b6511a96 AsmPrinter: Make DIEValue::Ty private, NFC
llvm-svn: 238123
2015-05-24 17:03:15 +00:00