Richard Osborne
9a827b30ab
Add XCore intrinsics for initializing / starting / synchronizing threads.
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llvm-svn: 128633
2011-03-31 15:13:13 +00:00
Richard Osborne
6120962d7d
Add XCore intrinsic for setpsc.
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llvm-svn: 127821
2011-03-17 18:42:05 +00:00
Richard Osborne
c871eff3f5
Add XCore intrinsics for setclk, setrdy.
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llvm-svn: 127761
2011-03-16 21:56:00 +00:00
Richard Osborne
d4346f2388
Add checkevent intrinsic to check if any resources owned by the current thread
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can event.
llvm-svn: 127741
2011-03-16 18:34:00 +00:00
Richard Osborne
3a68eb150b
Add XCore intrinsics for getps, setps, setsr and clrsr.
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llvm-svn: 127678
2011-03-15 13:45:47 +00:00
Richard Osborne
42f52e737e
Add XCore intrinsic for eeu instruction.
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llvm-svn: 126384
2011-02-24 13:39:18 +00:00
Richard Osborne
bfa5cc0e08
Add XCore intrinsic for clre instruction.
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llvm-svn: 126322
2011-02-23 18:52:05 +00:00
Richard Osborne
4995b05f56
Add llvm.xcore.waitevent intrinsic. The effect of this intrinsic is to enable
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events on the thread and wait until a resource is ready to event. The vector
of the resource that is ready is returned.
llvm-svn: 126320
2011-02-23 18:35:59 +00:00
Richard Osborne
2c610aa3ed
Add XCore intrinsic for the setv instruction.
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llvm-svn: 126315
2011-02-23 16:46:37 +00:00
Richard Osborne
12377e0947
Fix format for setc instruction.
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llvm-svn: 126314
2011-02-23 15:20:16 +00:00
Richard Osborne
aab96995f6
Add XCore intrinsic for settw instruction.
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llvm-svn: 126313
2011-02-23 14:45:03 +00:00
Richard Osborne
1ae65c7cb8
Add XCore intrinsics for various instructions on ports.
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llvm-svn: 126132
2011-02-21 18:23:30 +00:00
Richard Osborne
d9dde78c27
Add intrinsic for setc instruction on the XCore.
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llvm-svn: 125186
2011-02-09 13:22:12 +00:00
Richard Osborne
a31b9c2f7c
Add XCore intrinsics for resource instructions.
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llvm-svn: 124794
2011-02-03 13:14:25 +00:00
Chris Lattner
2a0a3b43d7
Flag -> Glue, the ongoing saga
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llvm-svn: 122513
2010-12-23 18:28:41 +00:00
Jakob Stoklund Olesen
d7dcbb57fb
Remove Predicate_* calls from MBlaze and XCore
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llvm-svn: 112920
2010-09-03 00:35:16 +00:00
Eric Christopher
2401271217
Remove isTwoAddress from XCore.
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llvm-svn: 106446
2010-06-21 18:51:38 +00:00
Chris Lattner
b7c48433df
fix a type contradition: XCoreISD::RETSP has one argument, not zero.
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llvm-svn: 99760
2010-03-28 08:47:39 +00:00
Chris Lattner
0433699ef0
set SDNPVariadic on nodes throughout the rest of the targets that
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need them.
llvm-svn: 98937
2010-03-19 05:33:51 +00:00
Richard Osborne
00fb2ce233
Don't mark call instruction as a barrier.
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llvm-svn: 96983
2010-02-23 21:08:11 +00:00
Richard Osborne
3a53f4e240
ECALLF, ECALLT shouldn't be marked as barriers.
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llvm-svn: 96964
2010-02-23 18:29:49 +00:00
Richard Osborne
f81db146b4
Mark unconditional branches as barriers. Found using -verify-machineinstrs
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llvm-svn: 96960
2010-02-23 18:13:38 +00:00
Richard Osborne
f578196968
Lower BR_JT on the XCore to a jump into a series of jump instructions.
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llvm-svn: 96942
2010-02-23 13:25:07 +00:00
Dan Gohman
4a618827de
Fix "the the" and similar typos.
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llvm-svn: 95781
2010-02-10 16:03:48 +00:00
Richard Osborne
3bd09434a6
Add XCore support for indirectbr / blockaddress.
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llvm-svn: 89273
2009-11-18 23:20:42 +00:00
Dan Gohman
9fd22f68f2
Set isBarrier = 1 on return instructions, as they are control barriers.
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llvm-svn: 86851
2009-11-11 18:11:07 +00:00
Dan Gohman
453d64c9f5
Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
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bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.
llvm-svn: 85517
2009-10-29 18:10:34 +00:00
Richard Osborne
4e13316bf9
Add some peepholes for signed comparisons using ashr X, X, 32.
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llvm-svn: 83549
2009-10-08 15:38:17 +00:00
Richard Osborne
692f6e7f9d
Remove xs1b predicate since it is no longer needed to differentiate betweem
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xs1a and xs1b.
llvm-svn: 83383
2009-10-06 16:17:57 +00:00
Richard Osborne
d7b887410d
Remove xs1a subtarget. xs1a is a preproduction device used in
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early development boards which is no longer supported in the
XMOS toolchain.
llvm-svn: 83381
2009-10-06 16:01:09 +00:00
Richard Osborne
bbb772ace9
Add extra SEXT pattern.
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llvm-svn: 77920
2009-08-02 22:45:24 +00:00
Richard Osborne
a8edd048c2
Fix pattern for LD16S_3r, add basic tests to check load / store instructions
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are being properly selected.
llvm-svn: 75797
2009-07-15 17:06:59 +00:00
Bill Wendling
09f17a8479
Untabification.
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llvm-svn: 72604
2009-05-30 01:09:53 +00:00
Richard Osborne
4359325ba8
Add pseudo instructions to the XCore for (load|store|load address) of a
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frame index. eliminateFrameIndex will replace these instructions with
(LDWSP|STWSP|LDAWSP) or (LDW|STW|LDAWF) if a frame pointer is in use.
This fixes PR 3324. Previously we used LDWSP, STWSP, LDAWSP before frame
pointer elimination. However since they were marked as implicitly using
SP they could not be rematerialised.
llvm-svn: 62238
2009-01-14 18:26:46 +00:00
Richard Osborne
feece7edab
Add support for ISD::TRAP to the XCore backend
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llvm-svn: 60479
2008-12-03 10:59:16 +00:00
Richard Osborne
d16b37efae
Add XCore intrinsics for getid (returns thread id) and bitrev (reverses
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bits in a word).
llvm-svn: 59296
2008-11-14 10:12:16 +00:00
Richard Osborne
ca08e0645a
Add XCore backend.
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llvm-svn: 58838
2008-11-07 10:59:00 +00:00