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104 Commits

Author SHA1 Message Date
Rafael Espindola 0fc5e89c82 ADD64ri32 sign extends its argument, so we need to use a R_X86_64_32S. 
Fixes PR9934.

We really need to start tblgening the relocation info :-(

llvm-svn: 131669
 2011-05-19 20:32:34 +00:00
Chris Lattner 0ab5e2cded Fix a ton of comment typos found by codespell. Patch by 
Luis Felipe Strano Moraes!

llvm-svn: 129558
 2011-04-15 05:18:47 +00:00
Joerg Sonnenberger fc4789da4a Add support for the VIA PadLock instructions. 
llvm-svn: 128826
 2011-04-04 16:58:13 +00:00
Joerg Sonnenberger cc53d9919f Expand Op0Mask by one bit in preparation for the PadLock prefixes. 
Define most shift masks incrementally to reduce the redundant
hard-coding. Introduce new shift for the VEX flags to replace the
magic constant 32 in various places.

llvm-svn: 128822
 2011-04-04 15:58:30 +00:00
Rafael Espindola e39062199e Implement xgetbv and xsetbv. 
Patch by Jai Menon.

llvm-svn: 126165
 2011-02-22 00:35:18 +00:00
Rafael Espindola 654cc4a81c Make pushq produce signed relocations. 
llvm-svn: 122005
 2010-12-16 22:50:01 +00:00
Daniel Dunbar 0c9d9fdd81 MC: Move target specific fixup info descriptors to TargetAsmBackend instead of 
the MCCodeEmitter, which seems like a better organization.
 - Also, cleaned up some magic constants while in the area.

llvm-svn: 121953
 2010-12-16 03:20:06 +00:00
Rafael Espindola 8a3a7923eb Define generic 1, 2 and 4 byte pc relative relocations. They are common 
and at least the 4 byte one will be needed to implement the .cfi_* directives.

llvm-svn: 120240
 2010-11-28 14:17:56 +00:00
Rafael Espindola 3c7cab1402 Produce a relocation for pcrel absolute values. Based on a patch by David Meyer. 
llvm-svn: 120006
 2010-11-23 07:20:12 +00:00
Chris Lattner 63274cbc5d add fields to the .td files unconditionally, simplifying tblgen a bit. 
Switch the ARM backend to use 'let' instead of 'set' with this change.

llvm-svn: 119120
 2010-11-15 05:19:05 +00:00
Rafael Espindola 800fd3533c Add X86::reloc_global_offset_table and use it to have a single place where 
we check for _GLOBAL_OFFSET_TABLE_.

llvm-svn: 117241
 2010-10-24 17:35:42 +00:00
Rafael Espindola 89f6613e76 Handle _GLOBAL_OFFSET_TABLE_ correctly. 
llvm-svn: 116932
 2010-10-20 16:46:08 +00:00
Jakob Stoklund Olesen aec745326a Remove the x86 MOV{32,64}{rr,rm,mr}_TC instructions. 
The reg-reg copies were no longer being generated since copyPhysReg copies
physical registers only.

The loads and stores are not necessary - The TC constraint is imposed by the
TAILJMP and TCRETURN instructions, there should be no need for constrained loads
and stores.

llvm-svn: 116314
 2010-10-12 17:15:00 +00:00
Chris Lattner 45270db916 Implement support for the bizarre 3DNow! encoding (which is unlike anything 
else in X86), and add support for pavgusb.  This is apparently the
only instruction (other than movsx) that is preventing ffmpeg from building
with clang.

If someone else is interested in banging out the rest of the 3DNow! 
instructions, it should be quite easy now.

llvm-svn: 115466
 2010-10-03 18:08:05 +00:00
Rafael Espindola 70d6e0e0ff Correctly produce R_X86_64_32 or R_X86_64_32S. 
With this patch in

movq    $foo, foo(%rip)
foo:
.long   foo

We produce a R_X86_64_32S for the first relocation and R_X86_64_32 for the
second one.

llvm-svn: 115134
 2010-09-30 03:11:42 +00:00
Nick Lewycky 23ebf4b319 Add parens to fix GCC warning: 
lib/Target/X86/X86MCCodeEmitter.cpp: 190: error: suggest parentheses around '&&' within '||'

llvm-svn: 115064
 2010-09-29 18:56:57 +00:00
Chris Lattner 5da7f9fcfd make the x86 mccode emitter emit the 0x67 and 0x66 prefix bytes in the same 
order as cctools for diffability.

llvm-svn: 115022
 2010-09-29 03:43:43 +00:00
Chris Lattner a4e1c74947 implement support for 32-bit address operands in 64-bit mode, which 
are defined to emit the 0x67 prefix byte.  rdar://8482675

llvm-svn: 115021
 2010-09-29 03:33:25 +00:00
Chris Lattner cea0a8d7ae fix rdar://8444631 - encoder crash on 'enter' 
What a weird instruction.

llvm-svn: 114190
 2010-09-17 18:02:29 +00:00
Bruno Cardoso Lopes 184eaea855 Fix PR7748 without using microsoft extensions 
llvm-svn: 112128
 2010-08-26 01:02:53 +00:00
Chris Lattner f547740d3f fix PR7465, mishandling of lcall and ljmp: intersegment long 
call and jumps.

llvm-svn: 111496
 2010-08-19 01:18:43 +00:00
Argyrios Kyrtzidis d0fcc9a818 Revert r111082. No warnings for this common pattern. 
llvm-svn: 111102
 2010-08-15 10:27:23 +00:00
Argyrios Kyrtzidis 7c09ddf0ae Add ATTRIBUTE_UNUSED to methods that are not supposed to be used. 
llvm-svn: 111082
 2010-08-14 21:35:10 +00:00
Bruno Cardoso Lopes cdbec62510 Add AVX only vzeroall and vzeroupper instructions 
llvm-svn: 109002
 2010-07-21 08:56:24 +00:00
Bruno Cardoso Lopes 3ceaf7a0a2 Add new AVX vmaskmov instructions, and also fix the VEX encoding bits to support it 
llvm-svn: 108983
 2010-07-21 02:46:58 +00:00
Bruno Cardoso Lopes fd8bfcd6e1 AVX 256-bit conversion instructions 
Add the x86 VEX_L form to handle special cases where VEX_L must be set.

llvm-svn: 108274
 2010-07-13 21:07:28 +00:00
Bruno Cardoso Lopes 792e906bef Start the support for AVX instructions with 256-bit %ymm registers. A couple of 
notes:
- The instructions are being added with dummy placeholder patterns using some 256
  specifiers, this is not meant to work now, but since there are some multiclasses
  generic enough to accept them,  when we go for codegen, the stuff will be already
  there.
- Add VEX encoding bits to support YMM
- Add MOVUPS and MOVAPS in the first round
- Use "Y" as suffix for those Instructions: MOVUPSYrr, ...
- All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX
  file.

llvm-svn: 107996
 2010-07-09 18:27:43 +00:00
Bruno Cardoso Lopes 992d25da71 Merge VEX enums with other x86 enum forms. Also fix all checks of which VEX 
fields to use. 

llvm-svn: 107952
 2010-07-09 01:56:45 +00:00
Bruno Cardoso Lopes e6cc0d33bb Factor out x86 segment override prefix encoding, and also use it for VEX 
llvm-svn: 107942
 2010-07-09 00:38:14 +00:00
Chris Lattner 061d70ad2c reject pseudo instructions early in the encoder. 
llvm-svn: 107939
 2010-07-09 00:17:50 +00:00
Bruno Cardoso Lopes b652c1a145 Remove trailing whitespaces from file 
llvm-svn: 107937
 2010-07-09 00:07:19 +00:00
Chris Lattner f469307c77 Change LEA to have 5 operands for its memory operand, just 
like all other instructions, even though a segment is not
allowed.  This resolves a bunch of gross hacks in the 
encoder and makes LEA more consistent with the rest of the
instruction set.

No functionality change.

llvm-svn: 107934
 2010-07-08 23:46:44 +00:00
Chris Lattner ec536276f0 add some long-overdue enums to refer to the parts of the 5-operand 
X86 memory operand.

llvm-svn: 107925
 2010-07-08 22:41:28 +00:00
Chris Lattner 9f034c1e5d Rework segment prefix emission code to handle segments 
in memory operands at the same type as hard coded segments.
This fixes problems where we'd emit the segment override after
the REX prefix on instructions like:
mov %gs:(%rdi), %rax

This fixes rdar://8127102.  I have several cleanup patches coming
next.

llvm-svn: 107917
 2010-07-08 22:28:12 +00:00
Chris Lattner 05ea2a4791 finish up support for callw: PR7195 
llvm-svn: 107826
 2010-07-07 22:35:13 +00:00
Chris Lattner ac5881295c Implement the major chunk of PR7195: support for 'callw' 
in the integrated assembler.  Still some discussion to be
done.

llvm-svn: 107825
 2010-07-07 22:27:31 +00:00
Bruno Cardoso Lopes 13f0260e76 Fix comment from previous patch 
llvm-svn: 107717
 2010-07-06 22:38:32 +00:00
Bruno Cardoso Lopes e2bd058d32 Add AVX vblendvpd, vblendvps and vpblendvb instructions 
Update VEX encoding to support those new instructions

llvm-svn: 107715
 2010-07-06 22:36:24 +00:00
Chris Lattner cb948d3329 indentation 
llvm-svn: 107599
 2010-07-04 22:56:10 +00:00
Bruno Cardoso Lopes c7111fd355 - Add support for the rest of AVX SSE3 instructions 
- Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M
represents a REX equivalent two byte leading opcode

llvm-svn: 107523
 2010-07-02 22:06:54 +00:00
Bruno Cardoso Lopes 05166740eb - Add AVX SSE2 Move doubleword and quadword instructions. 
- Add encode bits for VEX_W
- All 128-bit SSE 1 & SSE2 instructions that are described
  in the .td file now have a AVX encoded form already working.

llvm-svn: 107365
 2010-07-01 01:20:06 +00:00
Bruno Cardoso Lopes 2e2caefff9 - Add AVX form of all SSE2 logical instructions 
- Add VEX encoding bits to x86 MRM0r-MRM7r

llvm-svn: 107238
 2010-06-30 01:58:37 +00:00
Bruno Cardoso Lopes 30689a3a7f Add AVX ld/st XCSR register. 
Add VEX encoding bits for MRMXm x86 form

llvm-svn: 107204
 2010-06-29 20:35:48 +00:00
Bruno Cardoso Lopes 83651094ad Reapply r106896: 
Add several AVX MOV flavors
Support VEX encoding for MRMDestReg

llvm-svn: 106912
 2010-06-25 23:33:42 +00:00
Bruno Cardoso Lopes 4530fed87e revert this now, it's using avx instead of sse :) 
llvm-svn: 106906
 2010-06-25 23:04:29 +00:00
Bruno Cardoso Lopes a34d9b6d84 Add several AVX MOV flavors 
Support VEX encoding for MRMDestReg

llvm-svn: 106896
 2010-06-25 22:27:51 +00:00
Bruno Cardoso Lopes 4398fd7b83 - Add AVX COMI{SS,SD}{rr,rm} and UCOMI{SS,SD}{rr,rm}. 
- Fix a small VEX encoding issue.
- Move compare instructions to their appropriate place.

llvm-svn: 106787
 2010-06-24 20:48:23 +00:00
Bruno Cardoso Lopes 1a890f9dc0 Add AVX MOV{SS,SD}{rr,rm} instructions 
llvm-svn: 106588
 2010-06-22 22:38:56 +00:00
Chris Lattner c60cecd88b rip out dead code. 
llvm-svn: 106365
 2010-06-19 00:34:14 +00:00
Chris Lattner e808a78ac1 fix rdar://7873482 by teaching the instruction encoder to emit 
segment prefixes.  Daniel wrote most of this patch.

llvm-svn: 106364
 2010-06-19 00:34:00 +00:00