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67 Commits

Author SHA1 Message Date
Elena Demikhovsky 0f370936a0 AVX-512: Added all AVX-512 forms of Vector Convert for Float/Double/Int/Long types. 
In this patch I have only encoding. Intrinsics and DAG lowering will be in the next patch.
I temporary removed the old intrinsics test (just to split this patch).
Half types are not covered here.

Differential Revision: http://reviews.llvm.org/D11134

llvm-svn: 242023
 2015-07-13 13:26:20 +00:00
Elena Demikhovsky 431b81e41f AVX-512: Added VPTESTM and VPTESTNM instructions for SKX 
llvm-svn: 235383
 2015-04-21 13:13:46 +00:00
Craig Topper 8b88cc284f Use SmallVector instead of std::vector for uniquing X86 disassembler operand sets. The number of operands is a small fixed size. 
llvm-svn: 234465
 2015-04-09 04:08:48 +00:00
Craig Topper 34136874fd Simplify some printing code by combining new lines onto previous strings. Don't work so hard not to print a comma on the last entry of an array. 
llvm-svn: 234464
 2015-04-09 04:08:46 +00:00
Craig Topper d434e39557 Don't convert enum to strings just to put them in the uniquing map. Use the enum directly. Only convert to a string for printing. 
llvm-svn: 234463
 2015-04-09 04:08:42 +00:00
Elena Demikhovsky 02ffd26023 AVX-512: Added mask and rounding mode for scalar arithmetics 
Added more tests for scalar instructions to destinguish between AVX and AVX-512 forms.

llvm-svn: 230891
 2015-03-01 07:44:04 +00:00
Craig Topper ae8e1b3831 [X86] Disassembler support for move to/from %rax with a 32-bit memory offset is REX.W and AdSize prefix are both present. 
llvm-svn: 225099
 2015-01-03 00:00:20 +00:00
Craig Topper 055845f5cb [X86] Make the instructions that use AdSize16/32/64 co-exist together without using mode predicates. 
This is necessary to allow the disassembler to be able to handle AdSize32 instructions in 64-bit mode when address size prefix is used.

Eventually we should probably also support 'addr32' and 'addr16' in the assembler to override the address size on some of these instructions. But for now we'll just use special operand types that will lookup the current mode size to select the right instruction.

llvm-svn: 225075
 2015-01-02 07:02:25 +00:00
Craig Topper 99bcab7b85 [X86] Fix disassembly of absolute moves to work correctly in 16 and 32-bit modes with all 4 combinations of OpSize and AdSize prefixes being present or not. 
llvm-svn: 225036
 2014-12-31 07:07:31 +00:00
Craig Topper b86338f7b2 [X86] Remove the single AdSize indicator and replace it with separate AdSize16/32/64 flags. 
This removes a hardcoded list of instructions in the CodeEmitter. Eventually I intend to remove the predicates on the affected instructions since in any given mode two of them are valid if we supported addr32/addr16 prefixes in the assembler.

llvm-svn: 224809
 2014-12-24 06:05:22 +00:00
Robert Khasanov eb12639375 [AVX512] Extended avx512_sqrt_packed (sqrt instructions) to VL subset. 
Refactored through AVX512_maskable

llvm-svn: 220806
 2014-10-28 18:15:20 +00:00
Robert Khasanov d5b14f7994 [AVX512] Extended avx512_binop_rm for AVX512VL subsets. 
Added avx512_binop_rm_vl multiclass for VL subset
Added encoding tests

llvm-svn: 219390
 2014-10-09 08:38:48 +00:00
Robert Khasanov 2ea081d4d1 [SKX] avx512_icmp_packed multiclass extension 
Extended avx512_icmp_packed multiclass by masking versions.
Added avx512_icmp_packed_rmb multiclass for embedded broadcast versions.
Added corresponding _vl multiclasses.
Added encoding tests for CPCMP{EQ|GT}* instructions.
Add more fields for X86VectorVTInfo.
Added AVX512VLVectorVTInfo that include X86VectorVTInfo for 512/256/128-bit versions

Differential Revision: http://reviews.llvm.org/D5024

llvm-svn: 216383
 2014-08-25 14:49:34 +00:00
Robert Khasanov 7ca7df0bf9 [SKX] Enabling load/store instructions: encoding 
Instructions: VMOVAPD, VMOVAPS, VMOVDQA8, VMOVDQA16, VMOVDQA32,VMOVDQA64, VMOVDQU8, VMOVDQU16, VMOVDQU32,VMOVDQU64, VMOVUPD, VMOVUPS,

Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com>

llvm-svn: 214719
 2014-08-04 14:35:15 +00:00
Elena Demikhovsky f7c1b16591 AVX-512: Added rrk, rrkz, rmk, rmkz, rmbk, rmbkz versions of AVX512 FP packed instructions, added encoding tests for them. 
By Robert Khazanov.

llvm-svn: 203098
 2014-03-06 08:45:30 +00:00
Craig Topper 0d1fd55c13 Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables. 
llvm-svn: 201641
 2014-02-19 05:34:21 +00:00
Craig Topper 69e245c01d Remove filtering concept from X86 disassembler table generation. It's no longer necessary. 
llvm-svn: 201299
 2014-02-13 07:07:16 +00:00
Craig Topper 2813e3a46e Remove unnecessary include. 
llvm-svn: 201041
 2014-02-09 07:55:19 +00:00
David Woodhouse caaa2850c0 [x86] Fix disassembly of MOV16ao16 et al. 
The addition of IC_OPSIZE_ADSIZE in r198759 wasn't quite complete. It
also turns out to have been unnecessary. The disassembler handles the
AdSize prefix for itself, and doesn't care about the difference between
(e.g.) MOV8ao8 and MOB8ao8_16 definitions. So just let them coexist and
don't worry about it.

llvm-svn: 199654
 2014-01-20 12:02:53 +00:00
Elena Demikhovsky b19c9dc1a1 AVX-512: Embedded Rounding Control - encoding and printing 
Changed intrinsics for vrcp14/vrcp28 vrsqrt14/vrsqrt28 - aligned with GCC.

llvm-svn: 199102
 2014-01-13 12:55:03 +00:00
David Woodhouse 32da3c8f3b [x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand 
It seems there is no separate instruction class for having AdSize *and*
OpSize bits set, which is required in order to disambiguate between all
these instructions. So add that to the disassembler.

Hm, perhaps we do need an AdSize16 bit after all?

llvm-svn: 198759
 2014-01-08 12:58:24 +00:00
Craig Topper 3321c99a06 Remove modifierType/Base from X86 disassembler tables as they are no longer used. Removes ~11.5K from static tables. 
llvm-svn: 198284
 2014-01-01 21:52:57 +00:00
Elena Demikhovsky de3f751baf AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmp 
Printing rounding control.
Enncoding for EVEX_RC (rounding control).

llvm-svn: 198277
 2014-01-01 15:12:34 +00:00
Elena Demikhovsky 371e363833 AVX-512: decoder for AVX-512, made by Alexey Bader. 
llvm-svn: 198013
 2013-12-25 11:40:51 +00:00
Elena Demikhovsky dacddb0bab AVX-512: added VPCONFLICT instruction and intrinsics, 
added EVEX_KZ to tablegen

llvm-svn: 193959
 2013-11-03 13:46:31 +00:00
Craig Topper 9e3e38ae3f Add XOP disassembler support. Fixes PR13933. 
llvm-svn: 191874
 2013-10-03 05:17:48 +00:00
Craig Topper 009de6015f Filter out repeated sections from the X86 disassembler modRMTable. Saves about ~43K from a released build. Unfortunately the disassembler tables are still upwards of 800K. 
llvm-svn: 191652
 2013-09-30 06:23:19 +00:00
Craig Topper ed59dd34fd Various x86 disassembler fixes. 
Add VEX_LIG to scalar FMA4 instructions.
Use VEX_LIG in some of the inheriting checks in disassembler table generator.
Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts.
Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set.
Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases.
Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms.

llvm-svn: 191649
 2013-09-30 02:46:36 +00:00
Elena Demikhovsky 003e7d73b9 Added encoding prefixes for KNL instructions (EVEX). 
Added 512-bit operands printing.
Added instruction formats for KNL instructions.

llvm-svn: 187324
 2013-07-28 08:28:38 +00:00
Chandler Carruth 91d19d8e93 Sort the #include lines for utils/... 
I've tried to find main moudle headers where possible, but the TableGen
stuff may warrant someone else looking at it.

llvm-svn: 169251
 2012-12-04 10:37:14 +00:00
Craig Topper 963305b450 Add a new compression type to ModRM table that detects when the memory modRM byte represent 8 instructions and the reg modRM byte represents up to 64 instructions. Reduces modRM table from 43k entreis to 25k entries. Based on a patch from Manman Ren. 
llvm-svn: 163774
 2012-09-13 05:45:42 +00:00
Craig Topper 8702c5b7c0 Change unsigned to a uint16_t in static disassembler tables to reduce the table size. 
llvm-svn: 163594
 2012-09-11 04:19:21 +00:00
Craig Topper b8aec08819 Add more indirection to the disassembler tables to reduce amount of space used to store the operand types and encodings. Store only the unique combinations in a separate table and store indices in the instruction table. Saves about 32K of static data. 
llvm-svn: 161101
 2012-08-01 07:39:18 +00:00
Craig Topper 9caea12bd8 Use uint8_t to store the InstructionContext table. Saves 768 bytes of static data. 
llvm-svn: 161034
 2012-07-31 06:15:39 +00:00
Craig Topper 6f142746e7 Tidy up. Move for loop index declarations into for statements. Use unsigned instead of uint16_t for loop indices. Use unsigned instead of uint32_t for arguments to raw_ostream.indent. 
llvm-svn: 161033
 2012-07-31 06:02:05 +00:00
Craig Topper b61024cfcc Tidy up function argument formatting. 
llvm-svn: 161032
 2012-07-31 05:42:02 +00:00
Craig Topper 0c4253fe29 Remove trailing whitespace 
llvm-svn: 161030
 2012-07-31 05:27:01 +00:00
Craig Topper 6dedbae429 Use uint8_t instead of enums to store values in X86 disassembler table. Shaves 150k off the size of X86DisassemblerDecoder.o 
llvm-svn: 151995
 2012-03-04 02:16:41 +00:00
Craig Topper 6491c8020e X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by Kay Tiong Khoo. 
llvm-svn: 151510
 2012-02-27 01:54:29 +00:00
Ahmed Charles 636a3d618c Remove dead code. Improve llvm_unreachable text. Simplify some control flow. 
llvm-svn: 150918
 2012-02-19 11:37:01 +00:00
Benjamin Kramer 478e8de8ef Reuse the enum names from X86Desc in the X86Disassembler. 
This requires some gymnastics to make it available for C code. Remove the names
from the disassembler tables, making them relocation free.

llvm-svn: 150303
 2012-02-11 14:50:54 +00:00
Craig Topper a0cd970b81 More tweaks to get the size of the X86 disassembler tables down. 
llvm-svn: 150167
 2012-02-09 08:58:07 +00:00
Craig Topper 487e744f66 Flatten some of the arrays in the X86 disassembler tables to reduce space needed to store pointers on 64-bit hosts and reduce relocations needed at startup. Part of PR11953. 
llvm-svn: 150161
 2012-02-09 07:45:30 +00:00
David Blaikie b48ed1a4cb Remove unreachable code. (replace with llvm_unreachable to help GCC where necessary) 
llvm-svn: 148284
 2012-01-17 04:43:56 +00:00
Craig Topper f01f1b5cb9 More AVX2 instructions and their intrinsics. 
llvm-svn: 143895
 2011-11-06 23:04:08 +00:00
Craig Topper a697852386 Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist. 
llvm-svn: 141642
 2011-10-11 04:34:23 +00:00
Craig Topper 5aebebe18d Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine. 
llvm-svn: 141353
 2011-10-07 05:35:38 +00:00
Craig Topper f18c896337 Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676. 
llvm-svn: 141065
 2011-10-04 06:30:42 +00:00
Craig Topper 56ff34f7c5 Fix typo in r140954. 
llvm-svn: 140962
 2011-10-02 04:54:26 +00:00
Craig Topper 88cb33e0d4 Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702. 
llvm-svn: 140954
 2011-10-01 19:54:56 +00:00