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12 Commits

Author SHA1 Message Date
Andrew Trick 0b1d8d04b9 misched: Better handling of invalid latencies in the machine model 
llvm-svn: 166107
 2012-10-17 17:27:10 +00:00
Andrew Trick 5f35afb0f1 misched: Handle "transient" non-instructions. 
llvm-svn: 165701
 2012-10-11 05:37:06 +00:00
Andrew Trick c334bd4577 misched: fall-back to a target hook for instr bundles. 
llvm-svn: 165606
 2012-10-10 05:43:18 +00:00
Andrew Trick dd79f0fcea misched: Use the TargetSchedModel interface wherever possible. 
Allows the new machine model to be used for NumMicroOps and OutputLatency.

Allows the HazardRecognizer to be disabled along with itineraries.

llvm-svn: 165603
 2012-10-10 05:43:09 +00:00
Andrew Trick 780fae8cd6 misched: Add computeInstrLatency to TargetSchedModel. 
llvm-svn: 165566
 2012-10-09 23:44:32 +00:00
Andrew Trick cfcf5202a1 misched: Allow flags to disable hasInstrSchedModel/hasInstrItineraries for external users of TargetSchedule. 
llvm-svn: 165564
 2012-10-09 23:44:26 +00:00
Andrew Trick 8abcf4df68 Enable -schedmodel, but prefer itineraries until we have more benchmark data. 
llvm-svn: 165188
 2012-10-04 00:24:34 +00:00
Andrew Trick f2b70d9f3a TargetSchedule: cleanup computeOperandLatency logic & diagnostics. 
llvm-svn: 164154
 2012-09-18 18:20:02 +00:00
Andrew Trick 6e6d597b1c TargetSchedModel API. Implement latency lookup, disabled. 
llvm-svn: 164098
 2012-09-18 04:03:34 +00:00
Andrew Trick 8e7f202e32 Revert r164061-r164067. Most of the new subtarget emitter. 
I have to work out the Target/CodeGen header dependencies
before putting this back.

llvm-svn: 164072
 2012-09-17 23:00:42 +00:00
Andrew Trick f403ee7937 TargetSchedModel API. Implement latency lookup, disabled. 
llvm-svn: 164065
 2012-09-17 22:19:08 +00:00
Andrew Trick d2a19da1b8 TargetSchedModel interface. To be implemented... 
llvm-svn: 163934
 2012-09-14 20:26:46 +00:00