Commit Graph

17 Commits

Author SHA1 Message Date
Dylan McKay 8f46486c65 [AVR] Remove the earlyclobber flag from LDDWRdYQ
Before I started maintaining the AVR backend, this instruction
never originally used to have an earlyclobber flag.

Some time afterwards (years ago), I must've added it back in, not realising that it
was left out for a reason.

This pseudo instrction exists solely to work around a long standing bug
in the register allocator.

Before this commit, the LDDWRdYQ pseudo was not actually working around
any bug. With the earlyclobber flag removed again, the LDDWRdYQ pseudo
now correctly works around PR13375 again.

llvm-svn: 326774
2018-03-06 11:20:25 +00:00
Dylan McKay 3f71f1c91e [AVR] Factor out mayLoad in tablegen patterns
Patch by Gergo Erdi.

llvm-svn: 314897
2017-10-04 10:36:07 +00:00
Dylan McKay d00f9c1ef1 [AVR] Elaborate LDWRdPtr into `ld r, X++; ld r+1, X`
Patch by Gergo Erdi.

llvm-svn: 314896
2017-10-04 10:33:36 +00:00
Dylan McKay 4f5002198b [AVR] Use the correct register classes for 16-bit atomic operations
llvm-svn: 311620
2017-08-24 00:14:38 +00:00
Dylan McKay 84dd12d99e [AVR] Rename 'ZREGS' to 'ZREG'
It will only ever contain one register.

llvm-svn: 307620
2017-07-11 04:53:43 +00:00
Dylan McKay eef7a6a32f [AVR] Add a missing clobber declaration to LPMW
llvm-svn: 307056
2017-07-04 02:52:43 +00:00
Dylan McKay 48614d4a2c [AVR] CPIRdK can only work with r16..r31; Authored by Dr. Gergo Erdi
(https://github.com/avr-rust/rust/issues/50)

llvm-svn: 304283
2017-05-31 06:10:59 +00:00
Dylan McKay 74fc1ce0c2 [AVR] Remove SREG from CPI's Uses; authored by Florian Zeitz
Summary: CPI does not read the status register, but only writes it.

Reviewers: dylanmckay

Reviewed By: dylanmckay

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D33223

llvm-svn: 304116
2017-05-29 00:10:14 +00:00
Serge Pavlov d526b13e61 Add extra operand to CALLSEQ_START to keep frame part set up previously
Using arguments with attribute inalloca creates problems for verification
of machine representation. This attribute instructs the backend that the
argument is prepared in stack prior to  CALLSEQ_START..CALLSEQ_END
sequence (see http://llvm.org/docs/InAlloca.htm for details). Frame size
stored in CALLSEQ_START in this case does not count the size of this
argument. However CALLSEQ_END still keeps total frame size, as caller can
be responsible for cleanup of entire frame. So CALLSEQ_START and
CALLSEQ_END keep different frame size and the difference is treated by
MachineVerifier as stack error. Currently there is no way to distinguish
this case from actual errors.

This patch adds additional argument to CALLSEQ_START and its
target-specific counterparts to keep size of stack that is set up prior to
the call frame sequence. This argument allows MachineVerifier to calculate
actual frame size associated with frame setup instruction and correctly
process the case of inalloca arguments.

The changes made by the patch are:
- Frame setup instructions get the second mandatory argument. It
  affects all targets that use frame pseudo instructions and touched many
  files although the changes are uniform.
- Access to frame properties are implemented using special instructions
  rather than calls getOperand(N).getImm(). For X86 and ARM such
  replacement was made previously.
- Changes that reflect appearance of additional argument of frame setup
  instruction. These involve proper instruction initialization and
  methods that access instruction arguments.
- MachineVerifier retrieves frame size using method, which reports sum of
  frame parts initialized inside frame instruction pair and outside it.

The patch implements approach proposed by Quentin Colombet in
https://bugs.llvm.org/show_bug.cgi?id=27481#c1.
It fixes 9 tests failed with machine verifier enabled and listed
in PR27481.

Differential Revision: https://reviews.llvm.org/D32394

llvm-svn: 302527
2017-05-09 13:35:13 +00:00
Dylan McKay 59e7fe3da8 [AVR] Implement non-constant bit rotations
This lets us do bit rotations of variable amount.

llvm-svn: 301794
2017-05-01 09:48:55 +00:00
Dylan McKay 2e8718bcbb [AVR] Fix a bug so that we now emit R_AVR_16 fixups with the correct offset
Before this, the LDS/STS instructions would have their opcodes
overwritten while linking.

llvm-svn: 301782
2017-04-30 23:33:52 +00:00
Craig Topper 957a94cc03 Fix spelling compliment->complement. Mostly refering to 2s complement. NFC
llvm-svn: 299970
2017-04-11 18:47:58 +00:00
Dylan McKay 18ae0f68f8 [AVR] Use a more appropriate integer type for wide IN/OUT instructions
We could previously select an integer which would hit an assertion error
in pseudo expansion.

The new type will also generate the appropriate fixups if needed, which
wasn't done beforehand.

llvm-svn: 289192
2016-12-09 07:49:14 +00:00
Dylan McKay 8cec7eb6dd [AVR] Allow loading from stack slots where src and dest registers are identical
Fixes PR 31256

llvm-svn: 288897
2016-12-07 11:08:56 +00:00
Dylan McKay 0fe1e63837 [AVR] Merge most recent changes to AVRInstrInfo.td
This adds two new things:

- Operand types per fixup
- Atomic pseudo operations

llvm-svn: 282588
2016-09-28 13:44:02 +00:00
Dylan McKay 6d8078f993 [AVR] Add a majority of the backend code
Summary: This adds the majority of the AVR backend.

Reviewers: hfinkel, dsanders, vkalintiris, arsenm

Subscribers: dylanmckay

Differential Revision: http://reviews.llvm.org/D17906

llvm-svn: 268722
2016-05-06 10:12:31 +00:00
Dylan McKay bada46c111 [AVR] Add instruction definitions
Summary: Add the AVR instruction tablegen definitions.

Reviewers: stoklund, hfinkel, dsanders, arsenm, vkalintiris

Subscribers: dylanmckay, agnat, rjordans, llvm-commits

Differential Revision: http://reviews.llvm.org/D15703

llvm-svn: 260363
2016-02-10 08:55:23 +00:00