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2592 Commits

Author SHA1 Message Date
Dan Gohman 204dece054 Use tabs more consistently in assembler pseudo-ops. 
llvm-svn: 40594
 2007-07-30 15:08:02 +00:00
Christopher Lamb 5fecb80efa Change the x86 backend to use extract_subreg for truncation operations. Passes DejaGnu, SingleSource and MultiSource. 
llvm-svn: 40578
 2007-07-29 01:24:57 +00:00
Christopher Lamb ac3a364c51 Add register info needed to use subreg sets on X86. 
llvm-svn: 40572
 2007-07-28 19:03:30 +00:00
Duncan Sands ce38853cc6 Trampoline codegen support for X86-32. 
llvm-svn: 40566
 2007-07-27 20:02:49 +00:00
Dan Gohman 4788552deb Re-apply 40504, but with a fix for the segfault it caused in oggenc: 
Make the alignedload and alignedstore patterns always require 16-byte
alignment. This way when they are used in the "Fs" instructions, in which
a vector instruction is used for a scalar purpose, they can still require
the full vector alignment. And add a regression test for this.

llvm-svn: 40555
 2007-07-27 17:16:43 +00:00
Evan Cheng 931de40afa Reverting 40504 for now. It's breaking oggenc. 
llvm-svn: 40547
 2007-07-27 01:37:47 +00:00
Evan Cheng d204d08b97 Make sure epilogue esp adjustment is placed before any terminator and pop instructions. 
llvm-svn: 40538
 2007-07-26 17:45:41 +00:00
Evan Cheng 936d17aa1b Don't pollute the meaning of isUnpredicatedTerminator. 
llvm-svn: 40537
 2007-07-26 17:32:14 +00:00
Evan Cheng ca6e041903 Minor bug. 
llvm-svn: 40535
 2007-07-26 17:02:45 +00:00
Dan Gohman c9edd977ea In the .loc directive, print the fields as "debug" fields, so they 
don't get decorated as if for immediate fields for instructions.

llvm-svn: 40529
 2007-07-26 15:24:15 +00:00
Dan Gohman cecd4b3793 Fix a whitespace difference between CMPSSrr and CMPSDrr. 
llvm-svn: 40528
 2007-07-26 15:11:50 +00:00
Evan Cheng ce5185b181 Same goes for constantpool, etc. 
llvm-svn: 40517
 2007-07-26 07:35:15 +00:00
Dan Gohman 8455bd3fae Remove X86ISD::LOAD_PACK and X86ISD::LOAD_UA and associated code from the 
x86 target, replacing them with the new alignment attributes on memory
references.

llvm-svn: 40504
 2007-07-26 00:31:09 +00:00
Evan Cheng 630c1f75b8 Mac OS X x86-64 lower 4G address is not available. 
llvm-svn: 40502
 2007-07-25 23:41:36 +00:00
Evan Cheng 952aa6988b Mac OS X should use 0x90 to fill in gaps to satisfy function alignment requirements. 
llvm-svn: 40501
 2007-07-25 23:36:05 +00:00
Evan Cheng 5c6a31e9a0 Functions with LinkOnce and weak linkage still need to be aligned. Doh. 
llvm-svn: 40499
 2007-07-25 22:28:16 +00:00
Dan Gohman cf0a5349de Don't ignore the return value of AsmPrinter::doInitialization and 
AsmPrinter::doFinalization.

llvm-svn: 40487
 2007-07-25 19:33:14 +00:00
Anton Korobeynikov 64b64ae591 Minor cleanup: 
- Split EH and debug infiormation
 - Make DwarfWriter more verbose in some cases

llvm-svn: 40481
 2007-07-25 00:06:28 +00:00
Dan Gohman f0bb12848f Add const to CanBeFoldedBy, CheckAndMask, and CheckOrMask. 
llvm-svn: 40480
 2007-07-24 23:00:27 +00:00
Dan Gohman f906c7286f Use movaps to load a v4f32 build_vector of all-constant values into a 
register instead of loading each element individually.

llvm-svn: 40478
 2007-07-24 22:55:08 +00:00
Anton Korobeynikov 0c46451d2b Heal EH handling stuff by emitting correct offsets to callee-saved registers. 
Pretty hackish, but code itself is dirty mess, so we won't make anything worse. :)

llvm-svn: 40472
 2007-07-24 21:07:39 +00:00
Dan Gohman b6a8ae20c7 Fix some uses of dyn_cast to be uses of cast. 
llvm-svn: 40443
 2007-07-23 20:24:29 +00:00
Dan Gohman 17f68f95d8 Delete the svn:executable property on these files, which aren't executable. 
llvm-svn: 40441
 2007-07-23 19:26:08 +00:00
Bill Wendling 3d88e9940a Add missing SSE builtins: 
__builtin_ia32_cvtss2si64
    __builtin_ia32_cvttss2si64
    __builtin_ia32_cvtsi642ss
    __builtin_ia32_cvtsd2si64
    __builtin_ia32_cvttsd2si64
    __builtin_ia32_cvtsi642sd

llvm-svn: 40411
 2007-07-23 03:07:27 +00:00
Evan Cheng ac1591be42 No more noResults. 
llvm-svn: 40132
 2007-07-21 00:34:19 +00:00
Evan Cheng 9d5df0a5f6 Added -print-emitted-asm to print out JIT generated asm to cerr. 
llvm-svn: 40123
 2007-07-20 21:56:13 +00:00
Evan Cheng 8fefeffb37 Because we promote SSE logical ops and loads to v2i64, we often end up generate 
code that cross integer / floating point domains (e.g. generate pxor / pand for
logical ops on floating point value, movdqa to load / store floating point SSE
values). Given that, it's better to use movaps instead of movdqa and movups
instead of movdqu. They have the same latency but the "aps" variants are one
byte shorter.
If the domain crossing problem is a real performance issue, then we will have to
fix it with dynamic programming based isel.

llvm-svn: 40076
 2007-07-20 00:27:43 +00:00
Evan Cheng 64738536b3 Fix custom lowering of SSE FXOR. 
llvm-svn: 40071
 2007-07-19 23:36:01 +00:00
Evan Cheng 7ca3555bfa Fix patterns so we isel the xorps, etc. for floating pt logical SSE ops. DAG combiner may fold away the (bit_convert (load)). 
llvm-svn: 40070
 2007-07-19 23:34:10 +00:00
Evan Cheng 94b5a80b93 Change instruction description to split OperandList into OutOperandList and 
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033
 2007-07-19 01:14:50 +00:00
Evan Cheng 7b5b06805a Only adjust esp around calls in presence of alloca. 
llvm-svn: 40028
 2007-07-19 00:42:05 +00:00
Evan Cheng 8941071ae1 Use MOV instead of LEA to restore ESP if callee-saved frame size is 0; if previous instruction updates esp, fold it in. 
llvm-svn: 40018
 2007-07-18 21:26:06 +00:00
Dan Gohman 776962a97a Implement initial memory alignment awareness for SSE instructions. Vector loads 
and stores that have a specified alignment of less than 16 bytes now use
instructions that support misaligned memory references.

llvm-svn: 40015
 2007-07-18 20:23:34 +00:00
Evan Cheng f314055706 New entry. 
llvm-svn: 39998
 2007-07-18 08:21:49 +00:00
Evan Cheng 97b5dc63d7 Fold prologue esp update when possible. 
llvm-svn: 39984
 2007-07-17 21:26:42 +00:00
Evan Cheng b2bb4b4040 Make sure not to break eh_return. 
llvm-svn: 39978
 2007-07-17 18:40:47 +00:00
Evan Cheng 27ba94bf3b Update. 
llvm-svn: 39977
 2007-07-17 18:39:45 +00:00
Evan Cheng 67e2e22e97 Missed the case where alloca is used but the stack size (not including callee-saved portion) is zero. Thanks Dan. 
llvm-svn: 39974
 2007-07-17 18:03:34 +00:00
Evan Cheng 9ae2eb43d8 Use push / pop for prologues and epilogues. 
llvm-svn: 39967
 2007-07-17 07:59:08 +00:00
Anton Korobeynikov 383a324735 Long live the exception handling! 
This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.

In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.

After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be 
thought as 'finished': I expect many small and not so small glitches
everywhere.

llvm-svn: 39855
 2007-07-14 14:06:15 +00:00
Chris Lattner bdc69595d9 another missed SSE optimization 
llvm-svn: 39772
 2007-07-12 06:31:38 +00:00
Dale Johannesen 68471d263f Fix fp_constant_op failure. 
llvm-svn: 38514
 2007-07-10 21:53:30 +00:00
Dale Johannesen 23f631d87c fix 80 columnn violations, increasing the world's 
pedantic satisfaction level.

llvm-svn: 38512
 2007-07-10 20:53:41 +00:00
Chris Lattner f51bd666d9 add a note 
llvm-svn: 38507
 2007-07-10 20:03:50 +00:00
Dan Gohman 57111e7a60 Define non-intrinsic instructions for vector min, max, sqrt, rsqrt, and rcp, 
in addition to the intrinsic forms. Add spill-folding entries for these new
instructions, and for the scalar min and max instrinsic instructions which
were missing. And add some preliminary ISelLowering code for using the new
non-intrinsic vector sqrt instruction, and fneg and fabs.

llvm-svn: 38478
 2007-07-10 00:05:58 +00:00
Chris Lattner 517290ae52 The various "getModuleMatchQuality" implementations should return 
zero if they see a target triple they don't understand.

llvm-svn: 38463
 2007-07-09 17:25:29 +00:00
Evan Cheng d771e05121 isUnpredicatedTerminator should treat conditional branches as unpredicated terminator. 
llvm-svn: 37960
 2007-07-06 23:22:03 +00:00
Rafael Espindola b567e3ffb0 Add the byval attribute 
llvm-svn: 37940
 2007-07-06 10:57:03 +00:00
Anton Korobeynikov de9c825859 Proper flag __alloca call 
llvm-svn: 37923
 2007-07-05 20:36:08 +00:00
Gabor Greif e16561cd5d Here is the bulk of the sanitizing. 
Almost all occurrences of "bytecode" in the sources have been eliminated.

llvm-svn: 37913
 2007-07-05 17:07:56 +00:00