Commit Graph

405003 Commits

Author SHA1 Message Date
Adrian Prantl 6e78cfb28a typo 2021-11-16 09:09:55 -08:00
Kazu Hirata ee0133dc6d [llvm] Use range-for loops (NFC) 2021-11-16 09:01:56 -08:00
William S. Moses 30d87d4a5d [MLIR][LLVM] Permit integer types in switch other than i32
LLVM switchop currently only permits i32. Both LLVM IR and MLIR Standard switch permit other integer types leading to an illegal state when lowering an i8 switch from MLIR standard

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D113955
2021-11-16 12:00:37 -05:00
Philip Reames ed6b69a38f Add a hasPoisonGeneratingFlags proxy wrapper to Instruction [NFC]
This just cuts down on casts to Operator.
2021-11-16 08:48:16 -08:00
Nilay Vaish 7f287390d7 [libc++] Add introsort to avoid O(n^2) behavior
This commit adds a benchmark that tests std::sort on an adversarial inputs,
and uses introsort in std::sort to avoid O(n^2) behavior on adversarial
inputs.

Inputs where partitions are unbalanced even after 2 log(n) pivots have
been selected, the algorithm switches to heap sort to avoid the
possibility of spending O(n^2) time on sorting the input.
Benchmark results show that the intro sort implementation does
significantly better.

Benchmarking results before this change. Time represents the sorting
time required per element:

----------------------------------------------------------------------------------------------------------
Benchmark                                                                Time             CPU   Iterations
----------------------------------------------------------------------------------------------------------
BM_Sort_uint32_QuickSortAdversary_1                                   3.75 ns         3.74 ns    187432960
BM_Sort_uint32_QuickSortAdversary_4                                   3.05 ns         3.05 ns    231211008
BM_Sort_uint32_QuickSortAdversary_16                                  2.45 ns         2.45 ns    288096256
BM_Sort_uint32_QuickSortAdversary_64                                  32.8 ns         32.8 ns     21495808
BM_Sort_uint32_QuickSortAdversary_256                                  132 ns          132 ns      5505024
BM_Sort_uint32_QuickSortAdversary_1024                                 498 ns          497 ns      1572864
BM_Sort_uint32_QuickSortAdversary_16384                               3846 ns         3845 ns       262144
BM_Sort_uint32_QuickSortAdversary_262144                             61431 ns        61400 ns       262144
BM_Sort_uint64_QuickSortAdversary_1                                   3.93 ns         3.92 ns    181141504
BM_Sort_uint64_QuickSortAdversary_4                                   3.10 ns         3.09 ns    222560256
BM_Sort_uint64_QuickSortAdversary_16                                  2.50 ns         2.50 ns    283639808
BM_Sort_uint64_QuickSortAdversary_64                                  33.2 ns         33.2 ns     21757952
BM_Sort_uint64_QuickSortAdversary_256                                  132 ns          132 ns      5505024
BM_Sort_uint64_QuickSortAdversary_1024                                 478 ns          477 ns      1572864
BM_Sort_uint64_QuickSortAdversary_16384                               3932 ns         3930 ns       262144
BM_Sort_uint64_QuickSortAdversary_262144                             61646 ns        61615 ns       262144

Benchmarking results after this change:

----------------------------------------------------------------------------------------------------------
Benchmark                                                                Time             CPU   Iterations
----------------------------------------------------------------------------------------------------------
BM_Sort_uint32_QuickSortAdversary_1                                   6.31 ns         6.30 ns    107741184
BM_Sort_uint32_QuickSortAdversary_4                                   4.51 ns         4.50 ns    158859264
BM_Sort_uint32_QuickSortAdversary_16                                  3.00 ns         3.00 ns    223608832
BM_Sort_uint32_QuickSortAdversary_64                                  44.8 ns         44.8 ns     15990784
BM_Sort_uint32_QuickSortAdversary_256                                 69.0 ns         68.9 ns      9961472
BM_Sort_uint32_QuickSortAdversary_1024                                 118 ns          118 ns      6029312
BM_Sort_uint32_QuickSortAdversary_16384                                175 ns          175 ns      4194304
BM_Sort_uint32_QuickSortAdversary_262144                               210 ns          210 ns      3407872
BM_Sort_uint64_QuickSortAdversary_1                                   6.75 ns         6.73 ns    103809024
BM_Sort_uint64_QuickSortAdversary_4                                   4.53 ns         4.53 ns    160432128
BM_Sort_uint64_QuickSortAdversary_16                                  2.98 ns         2.97 ns    234356736
BM_Sort_uint64_QuickSortAdversary_64                                  44.3 ns         44.3 ns     15990784
BM_Sort_uint64_QuickSortAdversary_256                                 69.2 ns         69.2 ns     10223616
BM_Sort_uint64_QuickSortAdversary_1024                                 119 ns          119 ns      6029312
BM_Sort_uint64_QuickSortAdversary_16384                                173 ns          173 ns      4194304
BM_Sort_uint64_QuickSortAdversary_262144                               212 ns          212 ns      3407872

Differential Revision: https://reviews.llvm.org/D113413
2021-11-16 11:38:46 -05:00
Louis Dionne 4eda928660 [libc++] Add missed comment in https://reviews.llvm.org/D113910 2021-11-16 11:36:06 -05:00
Mark de Wever bfc253c000 [libc++][nfc] Improve standard conformance.
The return type of the deleted functions doesn't match the synopsis in
the standard.

Reviewed By: #libc, ldionne

Differential Revision: https://reviews.llvm.org/D114000
2021-11-16 17:30:35 +01:00
David Spickett 5beec6fb04 [libcxxabi/runtimes] Set LLVM_HOST_TRIPLE in runtimes build
This allows tests to tell if they're running natively.

Those tests are libcxxabi/test/native/arm-linux-eabi.
Which were running on Linaro's bots but became unsupported
when we switched to the runtimes build.

Reviewed By: #libc_abi, phosek

Differential Revision: https://reviews.llvm.org/D113663
2021-11-16 16:30:17 +00:00
Mark de Wever 3ddede8bfa [libc++][doc] Update format implementation status. 2021-11-16 17:29:40 +01:00
Nilay Vaish d17d89f4eb [libc++] Remove not needed call to __is_long()
The string is known to be long since __grow_by unconditionally calls
__set_long_cap().

Differential Revision: https://reviews.llvm.org/D113910
2021-11-16 11:26:13 -05:00
David Sherwood 4607459022 [AArch64] Fix TypeSize->uint64_t implicit conversion in AArch64ISelLowering::hasAndNot
For now I've just changed the code to only return true from
AArch64ISelLowering::hasAndNot if the vector is fixed-length.
Once we have the right patterns or DAG combines to use bic/bif
we can also enable this for SVE.

Test added here:

  CodeGen/AArch64/vselect-constants.ll

Differential Revision: https://reviews.llvm.org/D113994
2021-11-16 16:25:16 +00:00
Matheus Izvekov 35f798d05d
[libcxx] CI: only build native target for bootstrapping-build
Signed-off-by: Matheus Izvekov <mizvekov@gmail.com>

Reviewed By: #libc, ldionne

Differential Revision: https://reviews.llvm.org/D113950
2021-11-16 17:22:30 +01:00
Quinn Pham d4b28a0fe6 [NFC][clang] Inclusive language: replace master with main in convert_arm_neon.py
[NFC] As part of using inclusive language within the llvm project and to
match the renamed master branch, this patch replaces master with main in
`convert_arm_neon.py`.

Reviewed By: kristof.beyls

Differential Revision: https://reviews.llvm.org/D113942
2021-11-16 10:11:06 -06:00
Dmitry Vyukov d0c138ec8a tsan: disable bench_threads.cpp on aarch64
The new test started failing on bots with:

CHECK failed: tsan_rtl.cpp:327 "((addr + size)) <= ((TraceMemEnd()))"
   (0xf06200e03010, 0xf06200000000) (tid=4073872)

https://lab.llvm.org/buildbot#builders/179/builds/1761

This is a latent bug in aarch64 virtual address space layout,
there is not enough address space to fit traces for all threads.
But since the trace space is going away with the new tsan runtime
(D112603), disable the test.

Reviewed By: melver

Differential Revision: https://reviews.llvm.org/D113990
2021-11-16 16:53:04 +01:00
Dmitry Vyukov c7081b5b4c tsan: fix crash during thread exit
Use of gethostent provokes caching of some resources inside of libc.
They are freed in __libc_thread_freeres very late in thread lifetime,
after our ThreadFinish. __libc_thread_freeres calls free which
previously crashed in malloc hooks.
Fix it by setting ignore_interceptors for finished threads,
which in turn prevents malloc hooks.

Reviewed By: melver

Differential Revision: https://reviews.llvm.org/D113989
2021-11-16 16:43:09 +01:00
Andrzej Warzynski 50acc6d0f7 [flang][fir] Add missing `HasParent` in `fir_DTEntryOp`
Differential Revision: https://reviews.llvm.org/D113674
2021-11-16 15:40:55 +00:00
Florian Hahn be56ece918
[llvm-reduce] Move code to check chunk to function, to enable reuse (NFC).
This patch moves the logic to clone and check a new chunk into a new
function, to allow re-use in a follow-up patch that implements parallel
reductions.

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D113856
2021-11-16 15:39:13 +00:00
Christian Kühnel 75a078455f [NFC] disabling clang-tidy check readability-identifier-naming in Protocol.h
The file follows the LSP syntax, so we're intentially deviating
from the LLVM coding standard.

Differential Revision: https://reviews.llvm.org/D113889
2021-11-16 15:25:43 +00:00
Ahsan Saghir 4c8b8e0154 [PowerPC] Allow MMA built-ins to accept non-void pointers and arrays
Calls to MMA builtins that take pointer to void
do not accept other pointers/arrays whereas normal
functions with the same parameter do. This patch
allows MMA built-ins to accept non-void pointers
and arrays.

Reviewed By: nemanjai

Differential Revision: https://reviews.llvm.org/D113306
2021-11-16 09:14:41 -06:00
Christian Kühnel 274f12a44c [NFC][clangd] fix llvm-namespace-comment finding
Fixing the clang-tidy finding.

Differential Revision: https://reviews.llvm.org/D113895
2021-11-16 15:10:32 +00:00
Mark de Wever 0e50216f22 [libc++][format][nfc] Remove dead code.
This was an early part of the prototype. This has never been shipped
enabled and the final version of this code looks completely different.
2021-11-16 16:02:26 +01:00
Dmitry Vyukov c971f989ee tsan: de-hardcode number of unused bits in trace events
Precisely specifying the unused parts of the bitfield is critical for
performance. If we don't specify them, compiler will generate code to load
the old value and shuffle it to extract the unused bits to apply to the new
value. If we specify the unused part and store 0 in there, all that
unnecessary code goes away (store of the 0 const is combined with other
constant parts).

I don't see a good way to ensure we cover all of u64 bits with fields.
So at least introduce named kUnusedBits consts and check that bits
sum up to 64.

Depends on D113978.

Reviewed By: melver

Differential Revision: https://reviews.llvm.org/D113979
2021-11-16 16:00:14 +01:00
Dmitry Vyukov fa24d58279 tsan: use smaller trace parts for Go
In the old runtime we used to use different number of trace parts
for C++ and Go to reduce trace memory consumption for Go.
But now it's easier and better to use smaller parts because
we already use minimal possible number of parts for C++ (3).

Reviewed By: melver

Differential Revision: https://reviews.llvm.org/D113978
2021-11-16 15:59:33 +01:00
Mark de Wever 59a98dc208 [libc++][doc] Fix copy pasted comment. 2021-11-16 15:56:59 +01:00
Mark de Wever f0bb6c760c [libc++][doc] Add a todo.
As suggested in D113831.
2021-11-16 15:56:29 +01:00
LLVM GN Syncbot e993c6e8f8 [gn build] Port 5baa4ee30b 2021-11-16 14:52:00 +00:00
Mark de Wever 5baa4ee30b [libc++][NFC] Move format_to_n_result.
Places `format_to_n_result` to its own file. While working on D112361 it
turns out the type will be used outside the format header.

Reviewed By: #libc, Quuxplusone, Mordante

Differential Revision: https://reviews.llvm.org/D113831
2021-11-16 15:51:49 +01:00
Nicolas Vasilache b377807a76 [mlir][LLVM] Fix folding of LLVM::ExtractValueOp
Limit the backtracking along def-use chains when a prefix is encountered as it would generate incorrect foldings.

Differential Revision: https://reviews.llvm.org/D113975
2021-11-16 14:49:05 +00:00
Matt Devereau 83727f2771 [AArch64][SVE] Remove arm-registered-target requirement on bfloat tests
Changes in https://reviews.llvm.org/D113489 caused buildbot failures
2021-11-16 14:38:21 +00:00
Jon Chesterfield 30b29db7c7 [amdgpu] Don't crash on empty global ctor/dtor
Global ctor/dtor can be an empty array, which is a Constant not a
ConstantArray. The cast<ConstantArray> therefore asserts / crashes.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D113800
2021-11-16 14:36:08 +00:00
Sanjay Patel 8fce94f916 [InstCombine] canonicalize icmp with trunc op into mask and cmp, part 2
If C is a high-bit mask:
(trunc X) u< C --> (X & C) != C (are any masked-high-bits clear?)

If C is low-bit mask:
(trunc X) u> C --> (X & ~C) != 0 (are any masked-high-bits set?)

If C is not-of-power-of-2 (one clear bit):
(trunc X) u> C --> (X & (C+1)) == C+1 (are all masked-high-bits set?)

This extends the fold added with:
acabad9ff6 (https://alive2.llvm.org/ce/z/aFr7qV)

Using decomposeBitTestICmp() to generalize this is a planned follow-up, but that requires removing an inverse fold.

Here are Alive2 generalizations for these folds:
https://alive2.llvm.org/ce/z/u-ZpC_ (ult, the previous patch)
https://alive2.llvm.org/ce/z/YsuAu2 (ult, this patch)
https://alive2.llvm.org/ce/z/ekktQP (ugt, low bitmask)
https://alive2.llvm.org/ce/z/pJY9wR (ugt, one clear bit)

Differential Revision: https://reviews.llvm.org/D112634
2021-11-16 09:27:30 -05:00
Alexey Bataev 900cc1a226 [SLP]Improve cost of the gather nodes.
No need to count the final shuffle cost for the constants, gathering of
the constants is just a constant vector + extra inserts, if required.

Differential Revision: https://reviews.llvm.org/D113770
2021-11-16 06:25:07 -08:00
Jake Egan 2f43a656f3 [AIX] XFAIL lto-comp-dir.ll for lack of .file directive support
This test explicitly checks for .file directives, which is not currently supported on AIX. This patch sets this test to XFAIL on AIX for now.

Reviewed By: shchenz

Differential Revision: https://reviews.llvm.org/D113640
2021-11-16 09:15:00 -05:00
Alexey Bataev cdf8a53c1d [SLP]Fix windows build, NFC.
Need to put `IndexIdx` var to the list of captures.
2021-11-16 06:09:51 -08:00
Greg McGary 3a1b3c9afe [lld-macho][nfc] rename parsed-section types & variables
This is an NFC diff that prepares for pruning & relocating `__eh_frame`.

Along the way, I made the following changes to ...
* clarify usage of `section` vs. `subsection`
* remove `map` & `vec` from type names
* disambiguate class `Section` from template parameter `SectionHeader`.

Differential Revision: https://reviews.llvm.org/D113241
2021-11-16 07:06:41 -07:00
Jean Perier 2e65c8e8db [flang] Allow write after non advancing read in IO runtime
1. To avoid overwriting the part of the record read in the non advancing read,
the furtherPositionInRecord field must be set to the max of the
furtherPositionInRecord and the positionInRecord at the beginning of the
IO write.

2. To allow any further read to succeed after the write, the unit
beganReadingRecord_ must be set to false when resetting the recordLength
during the write, otherwise, recordLength will not be computed in further
read and an assert is hit (at unit.cpp(398)).

The added unit test exercises both of these scenarios.

Differential Revision: https://reviews.llvm.org/D113740
2021-11-16 14:53:39 +01:00
Zbigniew Sarbinowski 422cf2b506 [SystemZ][z/OS] Fix warnings from unsigned int to long in 32-bit mode
This patch fixes the warnings which shows up when libcxx library started to be compiled in 32-bit mode on z/OS.
More specifically, the assignment from unsigned int to time_t aka long was flags as follows:
 ```
libcxx/include/c++/v1/__support/ibm/nanosleep.h:31:11: warning: implicit conversion changes signedness: 'unsigned int' to 'time_t' (aka 'long') [-Wsign-conversion]
  __sec = sleep(static_cast<unsigned int>(__sec));
        ~ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
libcxx/include/c++/v1/__support/ibm/nanosleep.h:36:36: warning: implicit conversion changes signedness: 'unsigned int' to 'long' [-Wsign-conversion]
      __rem->tv_nsec = __micro_sec * 1000;
                     ~ ~~~~~~~~~~~~^~~~~~
libcxx/include/c++/v1/__support/ibm/nanosleep.h:47:36: warning: implicit conversion changes signedness: 'unsigned int' to 'long' [-Wsign-conversion]
      __rem->tv_nsec = __micro_sec * 1000;
                     ~ ~~~~~~~~~~~~^~~~~~
3 warnings generated.
```

Here is a small test case illustrating the issue:

```
typedef long    time_t ;
unsigned int sleep(unsigned int );
int main() {
  time_t sec = 0;
#ifdef FIX
  sec = static_cast<time_t>(sleep(static_cast<unsigned int>(sec)));
#else
  sec = sleep(static_cast<unsigned int>(sec));
#endif
}
```
clang++ -c -Wsign-conversion -m32 t.C
```
t.C:8:9: warning: implicit conversion changes signedness: 'unsigned int' to 'time_t' (aka 'long') [-Wsign-conversion]
  sec = sleep(static_cast<unsigned int>(sec));
      ~ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Reviewed By: ldionne, #libc, Quuxplusone, Mordante

Differential Revision: https://reviews.llvm.org/D112837
2021-11-16 13:51:35 +00:00
Andrzej Warzynski 6c3d7fd4c5 [flang][CodeGen] Transform `fir.boxchar_len` to a sequence of LLVM MLIR
This patch extends the `FIRToLLVMLowering` pass in Flang by adding a
hook to transform `fir.boxchar_len` to a sequence of LLVM MLIR
instructions.

This is part of the upstreaming effort from the `fir-dev` branch in [1].

[1] https://github.com/flang-compiler/f18-llvm-project

Differential Revision: https://reviews.llvm.org/D113763

Originally written by:
Co-authored-by: Eric Schweitz <eschweitz@nvidia.com>
2021-11-16 13:49:23 +00:00
Alexey Bataev aa9bbb64be [SLP]Adjust GEP indices types when trying to build entries.
Need to adjust the types of GEPs indices when building the tree
entries/operands. Otherwise some of the nodes might differ and
vectorizer is unable to correctly find them and count their cost.

Differential Revision: https://reviews.llvm.org/D113792
2021-11-16 05:44:33 -08:00
Alexey Bataev 51c0b6843a [SLP][NFC]Add more tests for shuffles that can be optimized after SLP,
NFC.
2021-11-16 05:42:18 -08:00
Valentin Clement 3124618704
[fir] Add fir.gentypedesc conversion
Add conversion pattern for the GenTypeDescOp.
Convert to a global constant with an addressof.

This patch is part of the upstreaming effort from fir-dev branch.

Reviewed By: kiranchandramohan

Differential Revision: https://reviews.llvm.org/D113766

Co-authored-by: Eric Schweitz <eschweitz@nvidia.com>
Co-authored-by: Jean Perier <jperier@nvidia.com>
2021-11-16 14:41:00 +01:00
Joseph Huber 374cd0fb61 [OpenMP] Fix initializer not working on AMDGPU
The RAII class used for debugging RTL entry used a shared variable to
keep track of the current depth. This used a global initializer, which
isn't supported on AMDGPU. This patch removes the initializer and
instead sets it to zero when the state is initialized in the runtime.

Reviewed By: jdoerfert, JonChesterfield

Differential Revision: https://reviews.llvm.org/D113963
2021-11-16 08:17:15 -05:00
Christian Kühnel d2da1a2f40 [NFC][clangd] cleaning up unused "using"
Cleaning up unused "using" declarations.
This patch was generated from automatically applyning clang-tidy fixes.

Differential Revision: https://reviews.llvm.org/D113891
2021-11-16 13:09:49 +00:00
Florian Hahn 97b9b6f565
[llvm-reduce] Add new BitWriter dependency after 28d95a2610. 2021-11-16 12:48:21 +00:00
Sander.DeSmalen@arm.com 305816ff1e [IndVarSimplify] Reduce nondeterministic behaviour in visitIVCast.
rGf39978b84f1d3a1da6c32db48f64c8daae64b3ad led to and/or exposed
an issue with IndVarSimplification for a loop where a i32 phi node is
no longer replaced by a widened (i64) phi node, because the SCEVs of a
sign-extend no longer folded the same way. I'm unsure how to properly
explain this because it's all rather complicated, but in short: SCEVs
don't fold as nicely as they used to and this caused a difference.

While investigating this, I found that IndVarSimplify can actually
optimise the case in the way we want to if it chooses the widened IV to
be 'signed' (the i32 IV is both sign and zero-extended). Oddly enough,
there is some level of indeterminism in the way the algorithm works,
it just picks the sign of the 'first' zext/sext user, where the order of
the users-iterator is not guaranteed to be the same on each invocation
of the pass (e.g. shown by first running loop-rotate, which puts the
users in a different order).

While I think the fix is valid in the sense that consistently picking
_any_ order is better than having an nondeterministic order, I can
use a bit of advice from people more familiar in this area of the
code-base.

For example, I'm not sure if this fix is hiding another issue where the
IndVarSimplify pass could actually draw the same conclusions (i.e. that
it only needs an i64 phi node) if it does a bit more work, regardless
of whether it chooses the induction variable to be signed or unsigned.

I'm also not sure if choosing signed is better than unsigned, or whether
that just happens to be beneficial only in this individual case.

Any feedback would be much appreciated!

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D112573
2021-11-16 12:41:04 +00:00
Florian Hahn 28d95a2610
[llvm-reduce] Allow writing temporary files as bitcode.
Textual LLVM IR files are much bigger and take longer to write to disk.
To avoid the extra cost incurred by serializing to text, this patch adds
an option to save temporary files as bitcode instead.

Reviewed By: aeubanks

Differential Revision: https://reviews.llvm.org/D113858
2021-11-16 12:39:42 +00:00
Diana Picus f1dfc0275c [fir] Add fir.cmpc conversion
This patch adds the codegen for fir.cmpc. The real and imaginary parts
are extracted and compared separately. For the .EQ. predicate the
results are AND'd, for the .NE. predicate the results are OR'd, and for
other predicates we keep only the result on the real parts.

This patch is part of the upstreaming effort from fir-dev.

Differential Revision: https://reviews.llvm.org/D113976

Co-authored-by: Eric Schweitz <eschweitz@nvidia.com>
Co-authored-by: Jean Perier <jperier@nvidia.com>
2021-11-16 12:26:27 +00:00
Fabian Wolff 738e7f1231 Fix false positive in `bugprone-throw-keyword-missing` check
Fixes PR#52400. The tests for bugprone-throw-keyword-missing actually
already contain exceptions as class members, but not as members with
initializers, which was probably just an oversight.
2021-11-16 07:09:17 -05:00
Pavel Labath 098c01c132 [lldb] Refactor Platform::ResolveExecutable
Module resolution is probably the most complex piece of lldb [citation
needed], with numerous levels of abstraction, each one implementing
various retry and fallback strategies.

It is also a very repetitive, with only small differences between
"host", "remote-and-connected" and "remote-but-not-(yet)-connected"
scenarios.

The goal of this patch (first in series) is to reduce the number of
abstractions, and deduplicate the code.

One of the reasons for this complexity is the tension between the desire
to offload the process of module resolution to the remote platform
instance (that's how most other platform methods work), and the desire
to keep it local to the outer platform class (its easier to subclass the
outer class, and it generally makes more sense).

This patch resolves that conflict in favour of doing everything in the
outer class. The gdb-remote (our only remote platform) implementation of
ResolveExecutable was not doing anything gdb-specific, and was rather
similar to the other implementations of that method (any divergence is
most likely the result of fixes not being applied everywhere rather than
intentional).

It does this by excising the remote platform out of the resolution
codepath. The gdb-remote implementation of ResolveExecutable is moved to
Platform::ResolveRemoteExecutable, and the (only) call site is
redirected to that. On its own, this does not achieve (much), but it
creates new opportunities for layer peeling and code sharing, since all
of the code now lives closer together.

Differential Revision: https://reviews.llvm.org/D113487
2021-11-16 12:52:51 +01:00
Butygin 6c48f6aafe [mlir][spirv] add AtomicFAddEXTOp
Differential Revision: https://reviews.llvm.org/D113764
2021-11-16 14:24:22 +03:00