Commit Graph

1333 Commits

Author SHA1 Message Date
Nadav Rotem 40cda80af8 No need to go through int64 and APInt when generating a new constant.
llvm-svn: 176615
2013-03-07 06:34:49 +00:00
Eli Bendersky b1caf3c30e Remove duplicate line and move another closer to its actual use
llvm-svn: 176391
2013-03-01 23:32:40 +00:00
Eli Bendersky 33ebf836bc A small refactoring + adding comments.
SelectionDAGIsel::LowerArguments needs a function, not a basic block. So it
makes sense to pass it the function instead of extracting a basic-block from
the function and then tossing it. This is also more self-documenting (functions
have arguments, BBs don't).

In addition, added comments to a couple of Select* methods.

llvm-svn: 176305
2013-02-28 23:09:18 +00:00
Eric Christopher 10d35e9065 Remove unnecessary cast to void.
llvm-svn: 176222
2013-02-27 23:49:45 +00:00
Nadav Rotem c29095fb50 Silence the unused variable warning.
llvm-svn: 176218
2013-02-27 22:52:54 +00:00
Nadav Rotem 00b75dd3c4 The FastISEL should be fast. But when we record statistics we use atomic operations to increment the counters.
This patch disables the counters on non-debug builds. This reduces the runtime of SelectionDAGISel::SelectCodeCommon by ~5%.

llvm-svn: 176214
2013-02-27 21:59:43 +00:00
Chad Rosier 0587597fb8 Fix wording.
llvm-svn: 176055
2013-02-25 22:20:00 +00:00
Chad Rosier a92ef4ba5b [fast-isel] Add X86FastIsel::FastLowerArguments to handle functions with 6 or
fewer scalar integer (i32 or i64) arguments. It completely eliminates the need
for SDISel for trivial functions.

Also, add the new llc -fast-isel-abort-args option, which is similar to
-fast-isel-abort option, but for formal argument lowering.

llvm-svn: 176052
2013-02-25 21:59:35 +00:00
Chad Rosier 3489bcc9ab [ms-inline asm] Remove a redundant call to the setHasMSInlineAsm function.
llvm-svn: 175456
2013-02-18 20:13:59 +00:00
NAKAMURA Takumi 68426c79db [ms-inline asm] Fix undefined behavior to reset hasMSInlineAsm in advance of SelectAllBasicBlocks().
llvm-svn: 175422
2013-02-18 07:06:48 +00:00
Chad Rosier 925c9b499e [ms-inline asm] Do not omit the frame pointer if we have ms-inline assembly.
If the frame pointer is omitted, and any stack changes occur in the inline
assembly, e.g.: "pusha", then any C local variable or C argument references
will be incorrect.  

I pass no judgement on anyone who would do such a thing. ;)
rdar://13218191

llvm-svn: 175334
2013-02-16 01:25:28 +00:00
Bill Wendling aef9c37c65 Use the 'target-features' and 'target-cpu' attributes to reset the subtarget features.
If two functions require different features (e.g., `-mno-sse' vs. `-msse') then
we want to honor that, especially during LTO. We can do that by resetting the
subtarget's features depending upon the 'target-feature' attribute.

llvm-svn: 175314
2013-02-15 22:31:27 +00:00
Evan Cheng 615620c9e8 Currently, codegen may spent some time in SDISel passes even if an entire
function is successfully handled by fast-isel. That's because function
arguments are *always* handled by SDISel. Introduce FastLowerArguments to
allow each target to provide hook to handle formal argument lowering.

As a proof-of-concept, add ARMFastIsel::FastLowerArguments to handle
functions with 4 or fewer scalar integer (i8, i16, or i32) arguments. It
completely eliminates the need for SDISel for trivial functions.

rdar://13163905

llvm-svn: 174855
2013-02-11 01:27:15 +00:00
Chandler Carruth d3e73556d6 Move TargetTransformInfo to live under the Analysis library. This no
longer would violate any dependency layering and it is in fact an
analysis. =]

llvm-svn: 171686
2013-01-07 03:08:10 +00:00
Chandler Carruth 42e9611f15 Funnel the actual TargetTransformInfo pass from the SelectionDAGISel
pass into the SelectionDAG itself rather than snooping on the
implementation of that pass as exposed by the TargetMachine. This
removes the last direct client of the ScalarTargetTransformInfo class
outside of the TTI pass implementation.

llvm-svn: 171625
2013-01-05 12:32:17 +00:00
Chandler Carruth 9fb823bbd4 Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.

There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.

The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.

I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).

I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.

llvm-svn: 171366
2013-01-02 11:36:10 +00:00
Jakob Stoklund Olesen 2705333253 Use MachineInstrBuilder for PHI nodes in SelectionDAGISel.
llvm-svn: 170716
2012-12-20 18:46:29 +00:00
Chad Rosier df42cf39ab Fall back to the selection dag isel to select tail calls.
This shouldn't affect codegen for -O0 compiles as tail call markers are not
emitted in unoptimized compiles.  Testing with the external/internal nightly
test suite reveals no change in compile time performance.  Testing with -O1,
-O2 and -O3 with fast-isel enabled did not cause any compile-time or
execution-time failures.  All tests were performed on my x86 machine.
I'll monitor our arm testers to ensure no regressions occur there.

In an upcoming clang patch I will be marking the objc_autoreleaseReturnValue
and objc_retainAutoreleaseReturnValue as tail calls unconditionally.  While
it's theoretically true that this is just an optimization, it's an
optimization that we very much want to happen even at -O0, or else ARC
applications become substantially harder to debug.

Part of rdar://12553082

llvm-svn: 169796
2012-12-11 00:18:02 +00:00
Jakub Staszak bac8ae6506 Use dyn_cast instead of isa and cast. No functionality change.
llvm-svn: 169196
2012-12-04 00:50:06 +00:00
Chandler Carruth ed0881b2a6 Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

llvm-svn: 169131
2012-12-03 16:50:05 +00:00
Andrew Trick 108c88c5b7 misched: Allow subtargets to enable misched and dependent options.
This allows me to begin enabling (or backing out) misched by default
for one subtarget at a time. To run misched we typically want to:
- Disable SelectionDAG scheduling (use the source order scheduler)
- Enable more aggressive coalescing (until we decide to always run the coalescer this way)
- Enable MachineScheduler pass itself.

Disabling PostRA sched may follow for some subtargets.

llvm-svn: 167826
2012-11-13 08:47:29 +00:00
Jakob Stoklund Olesen 57e310613c Freeze the reserved registers as soon as isel is complete.
Also provide an MRI::getReservedRegs() function to access the frozen
register set, and isReserved() and isAllocatable() methods to test
individual registers.

The various implementations of TRI::getReservedRegs() are quite
complicated, and many passes need to look at the reserved register set.
This patch makes it possible for these passes to use the cached copy in
MRI, avoiding a lot of malloc traffic and repeated calculations.

llvm-svn: 165982
2012-10-15 21:33:06 +00:00
Craig Topper 04b4e83cf7 Fix bad comment. No functional change.
llvm-svn: 164000
2012-09-16 16:48:25 +00:00
Nadav Rotem 7c277da364 Add a new optimization pass: Stack Coloring, that merges disjoint static allocations (allocas). Allocas are known to be
disjoint if they are marked by disjoint lifetime markers (@llvm.lifetime.XXX intrinsics).

llvm-svn: 163299
2012-09-06 09:17:37 +00:00
Manman Ren cf10446ffa BranchProb: modify the definition of an edge in BranchProbabilityInfo to handle
the case of multiple edges from one block to another.

A simple example is a switch statement with multiple values to the same
destination. The definition of an edge is modified from a pair of blocks to
a pair of PredBlock and an index into the successors.

Also set the weight correctly when building SelectionDAG from LLVM IR,
especially when converting a Switch.
IntegersSubsetMapping is updated to calculate the weight for each cluster.

llvm-svn: 162572
2012-08-24 18:14:27 +00:00
Craig Topper a538d831e6 Add a getName function to MachineFunction. Use it in places that previously did getFunction()->getName(). Remove includes of Function.h that are no longer needed.
llvm-svn: 162347
2012-08-22 06:07:19 +00:00
Bob Wilson 3e6fa462f3 Fall back to selection DAG isel for calls to builtin functions.
Fast isel doesn't currently have support for translating builtin function
calls to target instructions.  For embedded environments where the library
functions are not available, this is a matter of correctness and not
just optimization.  Most of this patch is just arranging to make the
TargetLibraryInfo available in fast isel.  <rdar://problem/12008746>

llvm-svn: 161232
2012-08-03 04:06:28 +00:00
Jim Grosbach 1af8c8060c Provide function name in 'Cannot select' fatal error.
When dumping the DAG for a fatal 'Cannot select' back-end error, also
provide the name of the function the construct is in. Useful when dealing
with large testcases, as the next step is to llvm-extract the function
in question to get a small(er) testcase.

llvm-svn: 160152
2012-07-13 00:29:09 +00:00
Bill Wendling e38859dc8e Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp and
include/llvm/Analysis/DebugInfo.h to include/llvm/DebugInfo.h.

The reasoning is because the DebugInfo module is simply an interface to the
debug info MDNodes and has nothing to do with analysis.

llvm-svn: 159312
2012-06-28 00:05:13 +00:00
Jakub Staszak cec09b2594 Add some constantness. No functionality change.
llvm-svn: 155859
2012-04-30 23:41:30 +00:00
Jakob Stoklund Olesen d114da6004 Fix PR12599.
The X86 target is editing the selection DAG while isel is selecting
nodes following a topological ordering. When the DAG hacking triggers
CSE, nodes can be deleted and bad things happen.

llvm-svn: 155257
2012-04-20 23:36:09 +00:00
Jakob Stoklund Olesen e3a891cf08 Make ISelPosition a local variable.
Now that multiple DAGUpdateListeners can be active at the same time,
ISelPosition can become a local variable in DoInstructionSelection.

We simply register an ISelUpdater with CurDAG while ISelPosition exists.

llvm-svn: 155249
2012-04-20 22:08:50 +00:00
Jakob Stoklund Olesen beb9469d5c Register DAGUpdateListeners with SelectionDAG.
Instead of passing listener pointers to RAUW, let SelectionDAG itself
keep a linked list of interested listeners.

This makes it possible to have multiple listeners active at once, like
RAUWUpdateListener was already doing. It also makes it possible to
register listeners up the call stack without controlling all RAUW calls
below.

DAGUpdateListener uses an RAII pattern to add itself to the SelectionDAG
list of active listeners.

llvm-svn: 155248
2012-04-20 22:08:46 +00:00
Rafael Espindola ba0a6cabb8 Always compute all the bits in ComputeMaskedBits.
This allows us to keep passing reduced masks to SimplifyDemandedBits, but
know about all the bits if SimplifyDemandedBits fails. This allows instcombine
to simplify cases like the one in the included testcase.

llvm-svn: 154011
2012-04-04 12:51:34 +00:00
Andrew Trick 60cf03e772 misched preparation: clarify ScheduleDAG and ScheduleDAGInstrs roles.
ScheduleDAG is responsible for the DAG: SUnits and SDeps. It provides target hooks for latency computation.

ScheduleDAGInstrs extends ScheduleDAG and defines the current scheduling region in terms of MachineInstr iterators. It has access to the target's scheduling itinerary data. ScheduleDAGInstrs provides the logic for building the ScheduleDAG for the sequence of MachineInstrs in the current region. Target's can implement highly custom schedulers by extending this class.

ScheduleDAGPostRATDList provides the driver and diagnostics for current postRA scheduling. It maintains a current Sequence of scheduled machine instructions and logic for splicing them into the block. During scheduling, it uses the ScheduleHazardRecognizer provided by the target.

Specific changes:
- Removed driver code from ScheduleDAG. clearDAG is the only interface needed.

- Added enterRegion/exitRegion hooks to ScheduleDAGInstrs to delimit the scope of each scheduling region and associated DAG. They should be used to setup and cleanup any region-specific state in addition to the DAG itself. This is necessary because we reuse the same ScheduleDAG object for the entire function. The target may extend these hooks to do things at regions boundaries, like bundle terminators. The hooks are called even if we decide not to schedule the region. So all instructions in a block are "covered" by these calls.

- Added ScheduleDAGInstrs::begin()/end() public API.

- Moved Sequence into the driver layer, which is specific to the scheduling algorithm.

llvm-svn: 152208
2012-03-07 05:21:52 +00:00
Andrew Trick 5297d8df99 whitespace
llvm-svn: 152175
2012-03-07 00:18:15 +00:00
Lang Hames 29d6ed6416 Rename getExceptionAddressRegister() to getExceptionPointerRegister() for consistency with setExceptionPointerRegister(...).
llvm-svn: 150460
2012-02-14 04:45:49 +00:00
Bill Wendling 0aef16afd5 [unwind removal] Remove all of the code for the dead 'unwind' instruction. There
were no 'unwind' instructions being generated before this, so this is in effect
a no-op.

llvm-svn: 149906
2012-02-06 21:44:22 +00:00
Andrew Trick d06df96a7c VLIW specific scheduler framework that utilizes deterministic finite automaton (DFA).
This new scheduler plugs into the existing selection DAG scheduling framework. It is a top-down critical path scheduler that tracks register pressure and uses a DFA for pipeline modeling.

Patch by Sergei Larin!

llvm-svn: 149547
2012-02-01 22:13:57 +00:00
Bill Wendling a4237652d2 Remove the eh.exception and eh.selector intrinsics. Also remove a hack to copy
over the catch information. The catch information is now tacked to the invoke
instruction.

llvm-svn: 149326
2012-01-31 01:46:13 +00:00
David Blaikie 46a9f016c5 More dead code removal (using -Wunreachable-code)
llvm-svn: 148578
2012-01-20 21:51:11 +00:00
Jakob Stoklund Olesen 9349351d72 Add a RegisterMaskSDNode class.
This SelectionDAG node will be attached to call nodes by LowerCall(),
and eventually becomes a MO_RegisterMask MachineOperand on the
MachineInstr representing the call instruction.

LowerCall() will attach a register mask that depends on the calling
convention.

llvm-svn: 148436
2012-01-18 23:52:12 +00:00
Evan Cheng 09cc429cb1 Allow targets to select source order pre-RA scheduler.
llvm-svn: 148033
2012-01-12 18:27:52 +00:00
Chad Rosier 73a3fab480 Add comment.
llvm-svn: 147696
2012-01-06 23:45:47 +00:00
David Blaikie a379b18173 Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch
llvm-svn: 146960
2011-12-20 02:50:00 +00:00
Joerg Sonnenberger d6cb7649d8 Allow inlining of functions with returns_twice calls, if they have the
attribute themselve.

llvm-svn: 146851
2011-12-18 20:35:43 +00:00
Devang Patel 7bbc1e56f5 Update DebugLoc while merging nodes at -O0.
Patch by Kyriakos Georgiou!

llvm-svn: 146670
2011-12-15 18:21:18 +00:00
Chad Rosier 2f8347e0b6 [fast-isel] Guard "exhastive" fast-isel output with -fast-isel-verbose2.
llvm-svn: 146453
2011-12-13 00:05:11 +00:00
Owen Anderson bb15fec2b8 Enhance both TargetLibraryInfo and SelectionDAGBuilder so that the latter can use the former to prevent the formation of libm SDNode's when -fno-builtin is passed.
llvm-svn: 146193
2011-12-08 22:15:21 +00:00
Chad Rosier 0464869922 Add rather verbose stats for fast-isel failures.
llvm-svn: 146186
2011-12-08 21:37:10 +00:00
Evan Cheng 7f8e563a69 Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.

llvm-svn: 146026
2011-12-07 07:15:52 +00:00
Evan Cheng 2a81dd4a3c First chunk of MachineInstr bundle support.
1. Added opcode BUNDLE
2. Taught MachineInstr class to deal with bundled MIs
3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs
4. Taught MachineBasicBlock methods about bundled MIs

llvm-svn: 145975
2011-12-06 22:12:01 +00:00
Nick Lewycky 50f02cb21b Move global variables in TargetMachine into new TargetOptions class. As an API
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.

One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.

llvm-svn: 145714
2011-12-02 22:16:29 +00:00
Chad Rosier cfd0d10e72 Fix the stats collection for fast-isel. The failed count was only accounting
for a single miss and not all predecessor instructions that get selected by
the selection DAG instruction selector.  This is still not exact (e.g., over
states misses when folded/dead instructions are present), but it is a step in
the right direction.

llvm-svn: 144832
2011-11-16 21:02:08 +00:00
Benjamin Kramer 1f97a5a671 Remove all remaining uses of Value::getNameStr().
llvm-svn: 144648
2011-11-15 16:27:03 +00:00
Eli Friedman 9d448e4a42 Don't try to form pre/post-indexed loads/stores until after LegalizeDAG runs. Fixes PR11029.
llvm-svn: 144438
2011-11-12 00:35:34 +00:00
Dan Gohman d78fc160cc Delete the Latency scheduling preference.
llvm-svn: 142815
2011-10-24 17:56:48 +00:00
Bill Wendling 63a4ea1859 Correct over-zealous removal of hack.
Some code want to check that *any* call within a function has the 'returns
twice' attribute, not just that the current function has one.

llvm-svn: 142221
2011-10-17 18:43:40 +00:00
Bill Wendling 2a83a71c2a Now that we have the ReturnsTwice function attribute, this method is
obsolete. Check the attribute instead.
<rdar://problem/8031714>

llvm-svn: 142212
2011-10-17 18:22:52 +00:00
Bill Wendling 267f323d28 Modify the mapping from landing pad to call sites to accept more than one call
site.

llvm-svn: 141226
2011-10-05 22:24:35 +00:00
Bill Wendling e61c62533e Small refactoring. Cache the FunctionInfo->MBB into a local variable.
llvm-svn: 141221
2011-10-05 22:16:11 +00:00
Andrew Trick 924123acb3 Lower ARM adds/subs to add/sub after adding optional CPSR operand.
This is still a hack until we can teach tblgen to generate the
optional CPSR operand rather than an implicit CPSR def. But the
strangeness is now limited to the selection DAG. ADD/SUB MI's no
longer have implicit CPSR defs, nor do we allow flag setting variants
of these opcodes in machine code. There are several corner cases to
consider, and getting one wrong would previously lead to nasty
miscompilation. It's not the first time I've debugged one, so this
time I added enough verification to ensure it won't happen again.

llvm-svn: 140228
2011-09-21 02:20:46 +00:00
Andrew Trick 52363bdbeb Restore hasPostISelHook tblgen flag.
No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.

llvm-svn: 140160
2011-09-20 18:22:31 +00:00
Andrew Trick 8586e62d91 ARM isel bug fix for adds/subs operands.
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile

llvm-svn: 140134
2011-09-20 03:17:40 +00:00
Andrew Trick 53df4b6dfa whitespace
llvm-svn: 140133
2011-09-20 03:06:13 +00:00
Evan Cheng e6fba77971 Follow up to r138791.
Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.

llvm-svn: 138810
2011-08-30 19:09:48 +00:00
Bill Wendling 4eb0433672 A landingpad instruction is neither folded nor dead.
llvm-svn: 138387
2011-08-23 21:33:05 +00:00
Duncan Sands a41634e307 Silence a bunch (but not all) "variable written but not read" warnings
when building with assertions disabled.

llvm-svn: 137460
2011-08-12 14:54:45 +00:00
Chris Lattner 96710b4308 fix PR10605 / rdar://9930964 by adding a pretty scary missed check.
It's somewhat surprising anything works without this.  Before we would
compile the testcase into:

test:                                   # @test
	movl	$4, 8(%rdi)
	movl	8(%rdi), %eax
	orl	%esi, %eax
	cmpl	$32, %edx
	movl	%eax, -4(%rsp)          # 4-byte Spill
	je	.LBB0_2

now we produce:

test:                                   # @test
	movl	8(%rdi), %eax
	movl	$4, 8(%rdi)
	orl	%esi, %eax
	cmpl	$32, %edx
	movl	%eax, -4(%rsp)          # 4-byte Spill
	je	.LBB0_2
llvm-svn: 137303
2011-08-11 06:26:54 +00:00
Devang Patel 9ab3cac694 Revert r135423.
llvm-svn: 135454
2011-07-19 00:28:24 +00:00
Devang Patel 4dc76f2438 During bottom up fast-isel, instructions emitted to materalize registers are at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases.
[take 2]

llvm-svn: 135423
2011-07-18 20:55:23 +00:00
Devang Patel 0eada03216 Revert r133953 for now.
llvm-svn: 134116
2011-06-29 23:50:13 +00:00
Evan Cheng 6cc775f905 - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.

llvm-svn: 134021
2011-06-28 19:10:37 +00:00
Devang Patel 4dc034df1d During bottom up fast-isel, instructions emitted to materalize registers are at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases.
llvm-svn: 133953
2011-06-27 22:32:04 +00:00
Jakub Staszak 12a43bdde5 Introduce MachineBranchProbabilityInfo class, which has similar API to
BranchProbabilityInfo (expect setEdgeWeight which is not available here).
Branch Weights are kept in MachineBasicBlocks. To turn off this analysis
set -use-mbpi=false.

llvm-svn: 133184
2011-06-16 20:22:37 +00:00
Devang Patel 84b64a3e92 Remove unused statistical counter.
llvm-svn: 132087
2011-05-25 21:55:40 +00:00
Devang Patel 7992883811 Preserve debug info during iSel by keeping DanglingDebugInfoMap live until end of function.
Patch by Micah Villmow

llvm-svn: 131908
2011-05-23 17:44:13 +00:00
Cameron Zwarich 2af60abad8 Fix PR9955 by only attaching load memory operands to load instructions and
similarly for stores. Now "make check" passes with the MachineVerifier forced
on with the VerifyCoalescing option!

llvm-svn: 131705
2011-05-19 23:44:34 +00:00
Eli Friedman e9692808b7 Make fast-isel miss counting in -stats and -fast-isel-verbose take terminators into account; since there are many fewer isel misses with recent changes, misses caused by terminators are more significant.
llvm-svn: 131502
2011-05-17 23:02:10 +00:00
Dan Gohman d282f46c6b Delete unused variables.
llvm-svn: 131430
2011-05-16 22:19:54 +00:00
Jim Grosbach e85c0dde7a Track how many insns fast-isel successfully selects as well as how many it
misses.

llvm-svn: 131426
2011-05-16 21:51:07 +00:00
Rafael Espindola 2050af838d Don't do tail calls in a function that call setjmp. The stack might be
corrupted when setjmp returns again.

llvm-svn: 131399
2011-05-16 03:05:33 +00:00
Eli Friedman 7a78f66145 Use array_lengthof. No functional change.
llvm-svn: 131008
2011-05-06 19:50:10 +00:00
Eli Friedman fd8c6adffb Small syntax cleanup; we don't need to #define constants in C++. No functionality change intended.
llvm-svn: 130926
2011-05-05 16:25:23 +00:00
Chris Lattner 6d277517d1 Recommit the fix for rdar://9289512 with a couple tweaks to
fix bugs exposed by the gcc dejagnu testsuite:
1. The load may actually be used by a dead instruction, which
   would cause an assert.
2. The load may not be used by the current chain of instructions,
   and we could move it past a side-effecting instruction. Change
   how we process uses to define the problem away.

llvm-svn: 130018
2011-04-22 21:59:37 +00:00
Daniel Dunbar 6309828206 Revert r1296656, "Fix rdar://9289512 - not folding load into compare at -O0...",
which broke a couple GCC test suite tests at -O0.

llvm-svn: 129914
2011-04-21 16:14:46 +00:00
Eli Friedman bcd09b3a7f SelectBasicBlock is rather slow even when it doesn't do anything; skip the
unnecessary work where possible.

llvm-svn: 129763
2011-04-19 17:01:08 +00:00
Chris Lattner 4832660b4d fix an oversight which caused us to compile the testcase (and other
less trivial things) into a dummy lea.  Before we generated:

_test:                                  ## @test
	movq	_G@GOTPCREL(%rip), %rax
	leaq	(%rax), %rax
	ret

now we produce:

_test:                                  ## @test
	movq	_G@GOTPCREL(%rip), %rax
	ret

This is part of rdar://9289558

llvm-svn: 129662
2011-04-17 17:12:08 +00:00
Chris Lattner 045c43855c Fix rdar://9289512 - not folding load into compare at -O0
The basic issue here is that bottom-up isel is matching the branch
and compare, and was failing to fold the load into the branch/compare
combo.  Fixing this (by allowing folding into any instruction of a
sequence that is selected) allows us to produce things like:


cmpb    $0, 52(%rax)
je      LBB4_2

instead of:

movb    52(%rax), %cl
cmpb    $0, %cl
je      LBB4_2

This makes the generated -O0 code run a bit faster, but also speeds up
compile time by putting less pressure on the register allocator and 
generating less code.

This was one of the biggest classes of missing load folding.  Implementing
this shrinks 176.gcc's c-decl.s (as a random example) by about 4% in (verbose-asm)
line count.

llvm-svn: 129656
2011-04-17 06:35:44 +00:00
Chris Lattner d70ff0d807 split a complex predicate out to a helper function. Simplify two for loops,
which don't need to check for falling off the end of a block *and* end of phi
nodes, since terminators are never phis.

llvm-svn: 129655
2011-04-17 06:03:19 +00:00
Andrew Trick b1fd328581 Added block number and name to isel debug output.
I'm tired of doing this manually for each checkout.
If anyone knows a better way debug isel for non-trivial tests feel
free to revert and let me know how to do it.

llvm-svn: 128132
2011-03-23 01:38:28 +00:00
Jim Grosbach 621818ab1a trailing whitespace.
llvm-svn: 126733
2011-03-01 01:39:05 +00:00
Jim Grosbach 1d479dbc55 Generalize the register matching code in DAGISel a bit.
llvm-svn: 126731
2011-03-01 01:37:19 +00:00
Cameron Zwarich a62fc89a04 Merge information about the number of zero, one, and sign bits of live-out
registers at phis. This enables us to eliminate a lot of pointless zexts during
the DAGCombine phase. This fixes <rdar://problem/8760114>.

llvm-svn: 126380
2011-02-24 10:00:25 +00:00
Cameron Zwarich 97eb52da7b Add a mechanism for invalidating the LiveOutInfo of a PHI, and use it whenever
a block is visited before all of its predecessors.

llvm-svn: 126378
2011-02-24 10:00:16 +00:00
Cameron Zwarich 988faf91bd Track blocks visited in reverse postorder.
llvm-svn: 126377
2011-02-24 10:00:13 +00:00
Cameron Zwarich 6470647383 Refactor the LiveOutInfo interface into a few methods on FunctionLoweringInfo
and make the actual map private.

llvm-svn: 126376
2011-02-24 10:00:08 +00:00
Cameron Zwarich b670d512e9 Have isel visit blocks in reverse postorder rather than an undefined order. This
allows for the information propagated across basic blocks to be merged at phis.

llvm-svn: 126375
2011-02-24 10:00:04 +00:00
Cameron Zwarich f8b22b3483 Roll out r126169 and r126170 in an attempt to fix the selfhost bot.
llvm-svn: 126185
2011-02-22 03:24:52 +00:00
Cameron Zwarich 800f85baf9 Merge information about the number of zero, one, and sign bits of live-out registers
at phis. This enables us to eliminate a lot of pointless zexts during the DAGCombine
phase. This fixes <rdar://problem/8760114>.

llvm-svn: 126170
2011-02-22 00:46:27 +00:00
Cameron Zwarich f248f945c8 Have isel visit blocks in reverse postorder rather than an undefined order. This
allows for the information propagated across basic blocks to be merged at phis.

llvm-svn: 126169
2011-02-22 00:46:22 +00:00
Devang Patel f3292b2196 Revert r124611 - "Keep track of incoming argument's location while emitting LiveIns."
In other words, do not keep track of argument's location.  The debugger (gdb) is not prepared to see line table entries for arguments. For the debugger, "second" line table entry marks beginning of function body.
This requires some coordination with debugger to get this working. 
 - The debugger needs to be aware of prolog_end attribute attached with line table entries.
 - The compiler needs to accurately mark prolog_end in line table entries (at -O0 and at -O1+)

llvm-svn: 126155
2011-02-21 23:21:26 +00:00
Devang Patel 56cc5fdf09 Keep track of incoming argument's location while emitting LiveIns.
llvm-svn: 124611
2011-01-31 21:38:14 +00:00
Chris Lattner 2d186574a6 reapply my fix for PR8961 with a tweak to properly handle
multi-instruction sequences like calls.  Many thanks to Jakob for
finding a testcase.

llvm-svn: 123559
2011-01-16 02:27:38 +00:00
Dan Gohman abac063b7a Delete an assignment to ThisBB which isn't needed, and tidy up some
comments.

llvm-svn: 123479
2011-01-14 22:26:16 +00:00
Chris Lattner 3be81e9bd7 Set the insertion point correctly for instructions generated by load folding:
they should go *before* the new instruction not after it. 

llvm-svn: 123420
2011-01-14 01:33:40 +00:00
Jakob Stoklund Olesen 793d7b7626 Use an IndexedMap for LiveOutRegInfo to hide its dependence on TargetRegisterInfo::FirstVirtualRegister.
llvm-svn: 123096
2011-01-08 23:10:50 +00:00
Evan Cheng 6eb516dbea Do not model all INLINEASM instructions as having unmodelled side effects.
Instead encode llvm IR level property "HasSideEffects" in an operand (shared
with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check
the operand when the instruction is an INLINEASM.

This allows memory instructions to be moved around INLINEASM instructions.

llvm-svn: 123044
2011-01-07 23:50:32 +00:00
Evan Cheng ac730dd2d1 Avoid zero extend bit test operands to pointer type if all the masks fit in
the original type of the switch statement key.
rdar://8781238

llvm-svn: 122935
2011-01-06 01:02:44 +00:00
Eric Christopher c673b21a87 80-cols.
llvm-svn: 122909
2011-01-05 21:45:56 +00:00
Andrew Trick 10ffc2b6c2 Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.

Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.

Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.

Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.

ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.

ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.

llvm-svn: 122541
2010-12-24 05:03:26 +00:00
Andrew Trick c416ba612b whitespace
llvm-svn: 122539
2010-12-24 04:28:06 +00:00
Chris Lattner 11a33811b6 flags -> glue for selectiondag
llvm-svn: 122509
2010-12-23 17:24:32 +00:00
Chris Lattner f647e95b9a sdisel flag -> glue.
llvm-svn: 122507
2010-12-23 17:13:18 +00:00
Chris Lattner 3e5fbd74ed rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for
something that just glues two nodes together, even if it is
sometimes used for flags.

llvm-svn: 122310
2010-12-21 02:38:05 +00:00
Chris Lattner 17f906be96 improve "cannot yet select" errors a trivial amount: now
they are just as useless, but at least a bit more gramatical

llvm-svn: 122305
2010-12-21 02:07:03 +00:00
Chris Lattner 77a8a71414 fix PR8642: if a critical edge has a PHI value that can trap,
isel is *required* to split the edge.  PHI values get evaluated
on the edge, not in their predecessor block.

llvm-svn: 122170
2010-12-19 04:58:57 +00:00
Bill Wendling 54df187f25 Check for _setjmp too, because it's also used.
llvm-svn: 119875
2010-11-20 00:03:09 +00:00
Duncan Sands 1462777017 Simplify uses of MVT and EVT. An MVT can be compared directly
with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.

llvm-svn: 118169
2010-11-03 12:17:33 +00:00
Nick Lewycky 90b2ac2696 For statistics that are only used in functions declared in !NDEBUG, wrap the
declarations in !NDEBUG to avoid -Wunused-variable warnings. Patch by
Matt Beaumont-Gay!

llvm-svn: 117345
2010-10-26 00:51:57 +00:00
Devang Patel 43c3f4b63c Simplify.
Do not count use of sdisel for single call instruction.

llvm-svn: 117316
2010-10-25 21:31:46 +00:00
Devang Patel 3bc6d198fb Add counters to count basic blocks and machine basic blocks with out of order line number info.
Add counters to count how many basic blocks are entirely selected by fastisel.

llvm-svn: 117310
2010-10-25 20:55:43 +00:00
Chandler Carruth 82058c05f8 Move the remaining attribute macros to systematic names based on the attribute
name and prefixed with 'LLVM_'.

llvm-svn: 117203
2010-10-23 08:40:19 +00:00
Owen Anderson 6c18d1aac0 Get rid of static constructors for pass registration. Instead, every pass exposes an initializeMyPassFunction(), which
must be called in the pass's constructor.  This function uses static dependency declarations to recursively initialize
the pass's dependencies.

Clients that only create passes through the createFooPass() APIs will require no changes.  Clients that want to use the
CommandLine options for passes will need to manually call the appropriate initialization functions in PassInitialization.h
before parsing commandline arguments.

I have tested this with all standard configurations of clang and llvm-gcc on Darwin.  It is possible that there are problems
with the static dependencies that will only be visible with non-standard options.  If you encounter any crash in pass
registration/creation, please send the testcase to me directly.

llvm-svn: 116820
2010-10-19 17:21:58 +00:00
Jakob Stoklund Olesen 665aa6efcc When isel is emitting instructions for an x86 target without CMOV, the CFG is
edited during emission.

If the basic block ends in a switch that gets lowered to a jump table, any
phis at the default edge were getting updated wrong. The jump table data
structure keeps a pointer to the header blocks that wasn't getting updated
after the MBB is split.

This bug was exposed on 32-bit Linux when disabling critical edge splitting in
codegen prepare.

The fix is to uipdate stale MBB pointers whenever a block is split during
emission.

llvm-svn: 115191
2010-09-30 19:44:31 +00:00
Oscar Fuentes 57214f533a Fix VS 2010 build.
Patch by Nathan Jeffords!

llvm-svn: 114661
2010-09-23 16:59:36 +00:00
Chris Lattner a9e57e0eff Rework passing parent pointers into complexpatterns, I forgot
that complex patterns are matched after the entire pattern has
a structural match, therefore the NodeStack isn't in a useful
state when the actual call to the matcher happens.

llvm-svn: 114489
2010-09-21 22:00:25 +00:00
Devang Patel 99ff76212a If only user of a vreg is an copy instruction to export copy of vreg out of current basic block then insert DBG_VALUE so that debug value of the variable is also transfered to new vreg.
Testcase is in r114476.
This fixes radar 8412415.

llvm-svn: 114478
2010-09-21 20:56:33 +00:00
Chris Lattner 0bb8b19865 correct this logic.
llvm-svn: 114474
2010-09-21 20:46:40 +00:00
Chris Lattner dd83548fea just like they can opt into getting the root of the pattern being
matched, allow ComplexPatterns to opt into getting the parent node
of the operand being matched.

llvm-svn: 114472
2010-09-21 20:37:12 +00:00
Chris Lattner eeba0c73e5 implement rdar://6653118 - fastisel should fold loads where possible.
Since mem2reg isn't run at -O0, we get a ton of reloads from the stack,
for example, before, this code:

int foo(int x, int y, int z) {
  return x+y+z;
}

used to compile into:

_foo:                                   ## @foo
	subq	$12, %rsp
	movl	%edi, 8(%rsp)
	movl	%esi, 4(%rsp)
	movl	%edx, (%rsp)
	movl	8(%rsp), %edx
	movl	4(%rsp), %esi
	addl	%edx, %esi
	movl	(%rsp), %edx
	addl	%esi, %edx
	movl	%edx, %eax
	addq	$12, %rsp
	ret

Now we produce:

_foo:                                   ## @foo
	subq	$12, %rsp
	movl	%edi, 8(%rsp)
	movl	%esi, 4(%rsp)
	movl	%edx, (%rsp)
	movl	8(%rsp), %edx
	addl	4(%rsp), %edx    ## Folded load
	addl	(%rsp), %edx     ## Folded load
	movl	%edx, %eax
	addq	$12, %rsp
	ret

Fewer instructions and less register use = faster compiles.

llvm-svn: 113102
2010-09-05 02:18:34 +00:00
Chris Lattner f6418b804e zap dead code.
llvm-svn: 112155
2010-08-26 02:57:35 +00:00
Owen Anderson a7aed18624 Reapply r110396, with fixes to appease the Linux buildbot gods.
llvm-svn: 110460
2010-08-06 18:33:48 +00:00
Owen Anderson bda59bd247 Revert r110396 to fix buildbots.
llvm-svn: 110410
2010-08-06 00:23:35 +00:00
Owen Anderson 755aceb5d0 Don't use PassInfo* as a type identifier for passes. Instead, use the address of the static
ID member as the sole unique type identifier.  Clean up APIs related to this change.

llvm-svn: 110396
2010-08-05 23:42:04 +00:00
Evan Cheng 37b740c4bf Add an ILP scheduler. This is a register pressure aware scheduler that's
appropriate for targets without detailed instruction iterineries.
The scheduler schedules for increased instruction level parallelism in
low register pressure situation; it schedules to reduce register pressure
when the register pressure becomes high.

On x86_64, this is a win for all tests in CFP2000. It also sped up 256.bzip2
by 16%.

llvm-svn: 109300
2010-07-24 00:39:05 +00:00
Gabor Greif dde79d8f1a mass elimination of reliance on automatic iterator dereferencing
llvm-svn: 109103
2010-07-22 13:36:47 +00:00
Dan Gohman 103c4ebea5 Use the source-order scheduler instead of the "fast" scheduler at -O0,
because it's more likely to keep debug line information in its original
order.

llvm-svn: 108496
2010-07-16 02:01:19 +00:00
Dan Gohman d7b5ce3312 Reapply bottom-up fast-isel, with several fixes for x86-32:
- Check getBytesToPopOnReturn().
 - Eschew ST0 and ST1 for return values.
 - Fix the PIC base register initialization so that it doesn't ever
   fail to end up the top of the entry block.

llvm-svn: 108039
2010-07-10 09:00:22 +00:00
Bill Wendling f831d86311 Clarify what mysterious check means.
llvm-svn: 108005
2010-07-09 19:44:12 +00:00
Bob Wilson 6586e9b203 --- Reverse-merging r107947 into '.':
U    utils/TableGen/FastISelEmitter.cpp
--- Reverse-merging r107943 into '.':
U    test/CodeGen/X86/fast-isel.ll
U    test/CodeGen/X86/fast-isel-loads.ll
U    include/llvm/Target/TargetLowering.h
U    include/llvm/Support/PassNameParser.h
U    include/llvm/CodeGen/FunctionLoweringInfo.h
U    include/llvm/CodeGen/CallingConvLower.h
U    include/llvm/CodeGen/FastISel.h
U    include/llvm/CodeGen/SelectionDAGISel.h
U    lib/CodeGen/LLVMTargetMachine.cpp
U    lib/CodeGen/CallingConvLower.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
U    lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
U    lib/CodeGen/SelectionDAG/FastISel.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
U    lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
U    lib/CodeGen/SelectionDAG/InstrEmitter.cpp
U    lib/CodeGen/SelectionDAG/TargetLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.h
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86FastISel.cpp
U    lib/Target/X86/X86ISelLowering.h

llvm-svn: 107987
2010-07-09 16:37:18 +00:00
Dan Gohman 0b5aa1cdd3 Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emitting
a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL.

llvm-svn: 107943
2010-07-09 00:39:23 +00:00
Bill Wendling a992445ff2 Extension of r107506. Make sure that we don't mark a function as having a call
if the inline ASM doesn't need a stack frame.

llvm-svn: 107922
2010-07-08 22:38:02 +00:00
Dan Gohman e75704369d Revert 107840 107839 107813 107804 107800 107797 107791.
Debug info intrinsics win for now.

llvm-svn: 107850
2010-07-08 01:00:56 +00:00
Dan Gohman 1adc499dda Fix -fast-isel-abort to check the right instruction.
llvm-svn: 107839
2010-07-07 23:47:25 +00:00
Dan Gohman e7ccc51cc1 Implement bottom-up fast-isel. This has the advantage of not requiring
a separate DCE pass over MachineInstrs.

llvm-svn: 107804
2010-07-07 19:20:32 +00:00
Dan Gohman b792f844ad Update the insert position after scheduling, which may change the
position when emitting multiple blocks when executing a custom
inserter.

llvm-svn: 107797
2010-07-07 18:22:13 +00:00
Dan Gohman ffe64b1ee5 Give FunctionLoweringInfo an MBB member, avoiding the need to pass it
around everywhere, and also give it an InsertPt member, to enable isel
to operate at an arbitrary position within a block, rather than just
appending to a block.

llvm-svn: 107791
2010-07-07 16:47:08 +00:00
Dan Gohman 87fb4e8fcd Simplify FastISel's constructor by giving it a FunctionLoweringInfo
instance, rather than pointers to all of FunctionLoweringInfo's
members.

This eliminates an NDEBUG ABI sensitivity.

llvm-svn: 107789
2010-07-07 16:29:44 +00:00
Dan Gohman e784616fbb Move FunctionLoweringInfo.h out into include/llvm/CodeGen. This will
allow target-specific fast-isel code to make use of it directly.

llvm-svn: 107787
2010-07-07 16:01:37 +00:00
Dan Gohman ee0cb70381 CanLowerReturn doesn't need a SelectionDAG; it just needs an LLVMContext.
SelectBasicBlock doesn't needs its BasicBlock argument.

llvm-svn: 107712
2010-07-06 22:19:37 +00:00
Bill Wendling f844642350 Proper indentation.
llvm-svn: 107581
2010-07-04 08:58:43 +00:00
Dale Johannesen 4d887f7ca7 Propagate the AlignStack bit in InlineAsm's to the
PrologEpilog code, and use it to determine whether
the asm forces stack alignment or not.  gcc consistently
does not do this for GCC-style asms; Apple gcc inconsistently
sometimes does it for asm blocks.  There is no
convenient place to put a bit in either the SDNode or
the MachineInstr form, so I've added an extra operand
to each; unlovely, but it does allow for expansion for
more bits, should we need it.  PR 5125.  Some
existing testcases are affected.
The operand lists of the SDNode and MachineInstr forms
are indexed with awesome mnemonics, like "2"; I may
fix this someday, but not now.  I'm not making it any
worse.  If anyone is inspired I think you can find all
the right places from this patch.

llvm-svn: 107506
2010-07-02 20:16:09 +00:00
Dan Gohman 93f5920914 Rename CreateReg to CreateRegs, and MakeReg to CreateReg.
llvm-svn: 107451
2010-07-02 00:10:16 +00:00
Dan Gohman d2965c10a1 Temporarily disable on-demand fast-isel.
llvm-svn: 107393
2010-07-01 12:15:30 +00:00
Dan Gohman 42b7ee15f5 Use FuncInfo's isExportedInst accessor method instead of
doing the work manually.

llvm-svn: 107384
2010-07-01 03:57:05 +00:00
Dan Gohman 85e02e9340 Rename CreateRegForValue to CreateReg, and change its argument
from a Value to a Type, because it doesn't actually care about
the Value.

llvm-svn: 107383
2010-07-01 03:55:39 +00:00
Dan Gohman 722f5fc567 Enable on-demand fast-isel.
llvm-svn: 107377
2010-07-01 02:58:57 +00:00
Dan Gohman 600f62b3ba Reapply r106634, now that the bug it exposed is fixed.
llvm-svn: 106746
2010-06-24 14:30:44 +00:00
Daniel Dunbar 4df321b7ad Revert r106263, "Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,"... it was causing both 'file' (with clang) and 176.gcc (with llvm-gcc) to be miscompiled.
llvm-svn: 106634
2010-06-23 17:09:26 +00:00
Dan Gohman 7edb39cc6b Minor code simplifications.
llvm-svn: 106286
2010-06-18 16:00:29 +00:00
Dan Gohman 6e681a5fbe Give NamedRegionTimer an Enabled flag, allowing all its clients to
switch from this:

  if (TimePassesIsEnabled) {
    NamedRegionTimer T(Name, GroupName);
    do_something();
  } else {
    do_something(); // duplicate the code, this time without a timer!
  }

to this:

  {
    NamedRegionTimer T(Name, GroupName, TimePassesIsEnabled);
    do_something();
  }

llvm-svn: 106285
2010-06-18 15:56:31 +00:00
Dan Gohman b92156d5e4 Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,
which is faster, simpler, and less surprising.

llvm-svn: 106263
2010-06-18 01:05:21 +00:00
Dan Gohman d16aa541af SelectionDAG shouldn't have a FunctionLoweringInfo member. RegsForValue
shouldn't have a TargetLoweringInfo member. And FunctionLoweringInfo::set
doesn't needs its EnableFastISel argument.

llvm-svn: 105101
2010-05-29 17:03:36 +00:00
Bill Wendling ddee3cb163 Add FIXME comment to remove this.
llvm-svn: 104749
2010-05-26 21:53:50 +00:00
Bill Wendling 27311269cb Add "setjmp_syscall", "savectx", "qsetjmp", "vfork", "getcontext" to the list of
usual suspects that could "return twice".

llvm-svn: 104737
2010-05-26 20:39:00 +00:00
Devang Patel 1b08572a66 Update debug info when live-in reg is copied into a vreg.
llvm-svn: 104732
2010-05-26 20:18:50 +00:00
Bill Wendling 0c3bfd3fb0 Move the check for "calls setjmp" to SelectionDAGISel so that it can be used by
more than just the stack slot coloring algorithm.

llvm-svn: 104722
2010-05-26 19:46:12 +00:00
Eric Christopher e805ea9e39 Temporarily revert r104655 as it's breaking the bots.
llvm-svn: 104664
2010-05-26 01:59:55 +00:00
Bill Wendling c5222d6c38 Dale and Evan suggested putting the "check for setjmp" much earlier in the
machine code generation. That's a good idea, so I made it so.

llvm-svn: 104655
2010-05-26 00:32:40 +00:00
Evan Cheng bdd062dae0 Add a hybrid bottom up scheduler that reduce register usage while avoiding
pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot
of long latency instructions so a strict register pressure reduction
scheduler does not work well.
Early experiments show this speeds up some NEON loops by over 30%.

llvm-svn: 104216
2010-05-20 06:13:19 +00:00
Evan Cheng 738e920edf Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace.
llvm-svn: 104147
2010-05-19 20:19:50 +00:00
Bill Wendling 02d3368831 - Set the "HasCalls" flag after instruction selection is finished.
- Change the logic DisableFramePointerElim() to check for the
  -disable-non-leaf-fp-elim before -disable-fp-elim.

llvm-svn: 103990
2010-05-17 23:09:50 +00:00
Bill Wendling 95f6ebcb37 Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe what
the variable actually tracks.

N.B., several back-ends are using "HasCalls" as being synonymous for something
that adjusts the stack. This isn't 100% correct and should be looked into.

llvm-svn: 103802
2010-05-14 21:14:32 +00:00
Evan Cheng 55869af998 Instruction selection optimizations may have moved the def of a function argument out of the entry block. rdar://7937489
llvm-svn: 102993
2010-05-04 00:58:39 +00:00
Dan Gohman ec74444d3e Remove the code for special-casing byval for fast-isel. SelectionDAG
handles argument lowering anyway, so there's no need for special
casing here.

llvm-svn: 102828
2010-05-01 02:44:23 +00:00
Dan Gohman 096619eb52 Fix whitespace.
llvm-svn: 102817
2010-05-01 00:33:28 +00:00
Dan Gohman 5d059718c9 Reorgnaize more switch code lowering to clean up some tricky
code, and to eliminate the need for the SelectionDAGBuilder
state to be live during CodeGenAndEmitDAG calls.

Call SDB->clear() before CodeGenAndEmitDAG calls instead of
before it, and move the CurDAG->clear() out of SelectionDAGBuilder,
which doesn't own the DAG, and into CodeGenAndEmitDAG.

llvm-svn: 102814
2010-05-01 00:25:44 +00:00
Dan Gohman 25c1653700 Get rid of the EdgeMapping map. Instead, just check for BasicBlock
changes before doing phi lowering for switches.

llvm-svn: 102809
2010-05-01 00:01:06 +00:00
Dan Gohman 09452cecd8 Remove this debug output. The MachineFunction will be printed once all of
instruction selection is done; it's confusing to see parts of it printed,
while other parts are omitted, along the way.

llvm-svn: 102771
2010-04-30 21:21:21 +00:00
Evan Cheng 923679f929 Re-enable 102565 with fixes.
llvm-svn: 102602
2010-04-29 06:33:38 +00:00
Evan Cheng d65a1e782b Temporarily disable my changes to unbreak the build.
llvm-svn: 102590
2010-04-29 03:34:19 +00:00
Evan Cheng 70a0145d7c Avoid emitting a dbg_value machineinstr that's not going to be inserted into entry block.
llvm-svn: 102581
2010-04-29 01:23:55 +00:00
Evan Cheng f4336ebb2a Check Reg against zero.
llvm-svn: 102573
2010-04-29 00:59:34 +00:00
Evan Cheng 6e822459ed Replace r102368 with code that's less fragile. This creates DBG_VALUE instructions for function arguments early and insert them after instruction selection is done.
llvm-svn: 102554
2010-04-28 23:08:54 +00:00
Dan Gohman 6e9a8fcc28 Move FastISel's HandlePHINodesInSuccessorBlocks call down into FastISel
itself too.

llvm-svn: 102176
2010-04-23 15:29:50 +00:00
Dan Gohman 5b43aa0ddd Sink SelectionDAGBuilder's HandlePHINodesInSuccessorBlocks down
into SelectionDAGBuilder itself.

llvm-svn: 102128
2010-04-22 20:55:53 +00:00
Dan Gohman c594eab10f Move HandlePHINodesInSuccessorBlocks functions out of SelectionDAGISel
and into SelectionDAGBuilder and FastISel.

llvm-svn: 102123
2010-04-22 20:46:50 +00:00
Dan Gohman fd81254190 Move PHINodesToUpdate out of SelectionDAGBuilder and into
FunctionLoweringInfo, as it isn't SelectionDAG-specific. This isn't
completely natural, as PHI node state is not per-function but rather
per-basic-block, however there's currently no other convenient
per-basic-block state to group it with.

llvm-svn: 102109
2010-04-22 19:55:20 +00:00
Dan Gohman 57c732b032 Add more const qualifiers on TargetMachine and friends.
llvm-svn: 101977
2010-04-21 01:34:56 +00:00
Dan Gohman 950fe784be Sink the CopyToExportRegsIfNeeded calls out of SelectionDAGISel
into SelectionDAGBuilder. This avoids a separate pass over the
instructions, and has the side effect of providing debug location
information to the copy.

llvm-svn: 101906
2010-04-20 15:03:56 +00:00
Dan Gohman f41ad478ca Don't send PHI nodes down to SelectionDAGBuilder of FastISel, since
they end up doing nothing.

llvm-svn: 101904
2010-04-20 15:00:41 +00:00
Dan Gohman eadc04badc Remove this debug output; it isn't that useful, and it's incomplete
in the case where a basic block is split.

llvm-svn: 101850
2010-04-20 00:56:44 +00:00
Dan Gohman e450d7444d Sink DebugLoc handling out of SelectionDAGISel into FastISel and
SelectionDAGBuilder, where it doesn't have to be as complicated.

llvm-svn: 101848
2010-04-20 00:48:35 +00:00
Dan Gohman 3df671a81c Remove MachineFunction's DefaultDebugLoc member, and make DwarfDebug.cpp
responsible for figuring out what that's supposed to be on its own.

llvm-svn: 101844
2010-04-20 00:37:27 +00:00
Dan Gohman ca35aa1122 Reapply the removal of SelectionDAGISel's BB, with a fix for the case
where multiple blocks are emitted; functions which do this need to return
the new BB so that their callers can stay current.

llvm-svn: 101843
2010-04-20 00:29:35 +00:00
Dan Gohman be2e727a38 Revert 101825, which is causing trouble.
llvm-svn: 101832
2010-04-19 23:34:15 +00:00
Dan Gohman 8cccc542f6 Eliminate SelectionDAGISel's "current block" member. Just pass it as
an argument to things that need it.

llvm-svn: 101825
2010-04-19 22:51:14 +00:00
Dan Gohman 7c0303a059 Eliminate the CurMBB member from SelectionDAGBuilder. For places that
need it, just pass around the parent block of the current instruction
explicitly.

llvm-svn: 101822
2010-04-19 22:41:47 +00:00
Dan Gohman 1e95790fd4 Give SelectionDAG a TargetMachine too, rather than having it
fetch one from the MachineFunction.

llvm-svn: 101807
2010-04-19 19:22:07 +00:00
Dan Gohman c334960f16 Code that needs a TargetMachine should have access to one directly, rather
than just getting one through a TargetLowering.

llvm-svn: 101802
2010-04-19 19:05:59 +00:00
Dan Gohman 21cea8ac2e Use const qualifiers with TargetLowering. This eliminates several
const_casts, and it reinforces the design of the Target classes being
immutable.

SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.

And PIC16's AsmPrinter no longer uses TargetLowering.

llvm-svn: 101635
2010-04-17 15:26:15 +00:00
Evan Cheng f1bd5fcdb4 More work to allow dag combiner to promote 16-bit ops to 32-bit.
llvm-svn: 101621
2010-04-17 06:13:15 +00:00
Dan Gohman 3a7ee8eead Avoid creating virtual registers for unused values.
llvm-svn: 101480
2010-04-16 17:15:02 +00:00
Dan Gohman 4572a9f479 Fix a comment.
llvm-svn: 101477
2010-04-16 16:52:37 +00:00
Dan Gohman 5563473062 Refine further the scope where the global DebugLoc value is active.
llvm-svn: 101443
2010-04-16 05:06:56 +00:00
Dan Gohman b29cda9b3c Fix a bunch of namespace polution.
llvm-svn: 101376
2010-04-15 17:08:50 +00:00
Dan Gohman 913c998703 Add more const qualifiers for LLVM IR pointers in CodeGen.
llvm-svn: 101342
2010-04-15 04:33:49 +00:00
Dan Gohman bcaf681cde Add const qualifiers to CodeGen's use of LLVM IR constructs.
llvm-svn: 101334
2010-04-15 01:51:59 +00:00
Dan Gohman a3918ecdf5 Delete unused arguments.
llvm-svn: 101275
2010-04-14 20:05:00 +00:00
Dan Gohman 7deb447781 Factor out EH landing pad code into a separate function, and constify
a bunch of stuff to support it.

llvm-svn: 101273
2010-04-14 19:53:31 +00:00
Dan Gohman c2c08d19b8 Reset the debug location even if the instruction was a terminator.
llvm-svn: 101272
2010-04-14 19:30:02 +00:00
Dan Gohman 3215eae4a3 Delete an unused function.
llvm-svn: 101263
2010-04-14 17:22:02 +00:00
Dan Gohman 094fc7b09e Clear the FunctionLoweringInfo object before doing other things that
don't need it.

llvm-svn: 101262
2010-04-14 17:13:16 +00:00
Dan Gohman ad0b3ea3cc Move this assert out of SelectionDAGISel into FunctionLoweringInfo, and
drop the redundant #ifndef NDEBUG.

llvm-svn: 101261
2010-04-14 17:11:23 +00:00
Dan Gohman 0f405c8d73 Add a comment.
llvm-svn: 101260
2010-04-14 17:09:37 +00:00
Dan Gohman 2ca8fb229c Move the code for initialing the entry block livein set out of
SelectionDAGISel.

llvm-svn: 101258
2010-04-14 17:05:00 +00:00
Dan Gohman 4bfb437ec9 Reorgnaize this code to be more tidy and readable.
llvm-svn: 101256
2010-04-14 17:02:07 +00:00
Dan Gohman 1939b5f130 Trim #includes.
llvm-svn: 101255
2010-04-14 16:54:39 +00:00
Dan Gohman 2b79ee8bc8 Move the code for emitting livein copies out of SelectionDAGISel.
llvm-svn: 101254
2010-04-14 16:51:49 +00:00
Dan Gohman 69e8e322d9 Sink landing-pad marking code out of
SelectionDAGISel::runOnMachineFunction into FunctionLowering.

llvm-svn: 101252
2010-04-14 16:32:56 +00:00
Chris Lattner 94ef52824b minor tidying.
llvm-svn: 100725
2010-04-07 23:50:38 +00:00
Chris Lattner 2104b8d36e rename llvm::llvm_report_error -> llvm::report_fatal_error
llvm-svn: 100709
2010-04-07 22:58:41 +00:00
Chris Lattner 3b9f02a2aa Three changes:
1. Introduce some enums and accessors in the InlineAsm class
   that eliminate a ton of magic numbers when handling inline
   asm SDNode.
2. Add a new MDNodeSDNode selection dag node type that holds
   a MDNode (shocking!)
3. Add a new argument to ISD::INLINEASM nodes that hold !srcloc
   metadata, propagating it to the instruction emitter, which
   drops it.

No functionality change.

llvm-svn: 100605
2010-04-07 05:20:54 +00:00
Chris Lattner 6361414c88 remove some redundant MMI arguments.
llvm-svn: 100417
2010-04-05 06:10:13 +00:00
Chris Lattner 305f2efb63 unthread MMI from FastISel
llvm-svn: 100416
2010-04-05 06:05:26 +00:00
Chris Lattner f5d0636850 trim some spurious references to DwarfWriter. SDIsel really doesn't
need it anymore, so don't addRequire it.

llvm-svn: 100400
2010-04-05 04:09:20 +00:00
Chris Lattner ab5dc34351 selection dag doesn't need DwarfWriter, remove some tendrils.
llvm-svn: 100382
2010-04-05 02:23:33 +00:00
Chris Lattner 7cfa70e9b3 fastisel doesn't need DwarfWriter, remove some tendricles.
llvm-svn: 100381
2010-04-05 02:19:28 +00:00
Chris Lattner bd009d6d6d stop using DebugLoc::getUnknownLoc()
llvm-svn: 100215
2010-04-02 20:17:23 +00:00
Chris Lattner 915c5f9862 Switch the code generator (except the JIT) onto the new DebugLoc
representation.  This eliminates the 'DILocation' MDNodes for 
file/line/col tuples from -O0 -g codegen.

This remove the old DebugLoc class, making it a typedef for DebugLoc,
I'll rename NewDebugLoc next.

I didn't update the JIT to use the new apis, so it will continue to
work, but be as slow as before.  Someone should eventually do this
or, better yet, rip out the JIT debug info stuff and build the JIT
on top of MC.

llvm-svn: 100209
2010-04-02 19:42:39 +00:00
Chris Lattner 3131ae86d8 use the optimized debug info apis in sdisel.
llvm-svn: 99986
2010-03-31 04:24:50 +00:00
Chris Lattner 03719af41d add a statistic for the # times isel has to backtrack.
llvm-svn: 99774
2010-03-28 19:46:56 +00:00
Chris Lattner 6642118e83 finally remove the immAllOnesV_bc/immAllZerosV_bc patterns
and those derived from them.  These are obnoxious because
they were written as: PatLeaf<(bitconvert).  Not having an
argument was foiling adding better type checking for operand
count matching up with what was required (in this case,
bitconvert always requires an operand!)

llvm-svn: 99759
2010-03-28 08:43:23 +00:00
Chris Lattner 89ad2f1d60 comply with the wishes of a fixme.
llvm-svn: 99742
2010-03-28 05:55:17 +00:00
Chris Lattner 4d8786b5cc now that (parallel) is gone and a variety of bugs in targets
are cleaned up, we can remove an old fixme.

llvm-svn: 99741
2010-03-28 05:54:03 +00:00
Chris Lattner 49e2773dd8 add an optimized form of OPC_EmitMergeInputChains for the 1, 0 and
1, 1 cases which are by-far the most frequent.  This shrinks the X86
isel table from 77014 -> 74657 bytes.

llvm-svn: 99740
2010-03-28 05:50:16 +00:00
Chris Lattner e01f7e33ac don't add nodes to the now-dead nodes list multiple times, this
can cause a crash on crazy situations in msp430 when morph-node-to
is disabled.

llvm-svn: 99739
2010-03-28 05:28:31 +00:00
Chris Lattner 7aed1fb69d don't add flag nodes with chain results to the NowDeadNodes
list multiple times when MorphNodeTo can't be applied.

llvm-svn: 99735
2010-03-28 04:54:33 +00:00
Chris Lattner decc73d4bc improve -debug-only=isel comments for cases when we don't enter a
scope due to obviously false predicate.

llvm-svn: 99723
2010-03-27 18:54:50 +00:00
Chris Lattner 552dddc51c Change tblgen to emit FOOISD opcode names as two
bytes instead of one byte.  This is important because
we're running up to too many opcodes to fit in a byte
and it is aggrevated by FIRST_TARGET_MEMORY_OPCODE
making the numbering sparse.  This just bites the
bullet and bloats out the table.  In practice, this
increases the size of the x86 isel table from 74.5K
to 76K.  I think we'll cope :)

This fixes rdar://7791648

llvm-svn: 99494
2010-03-25 06:33:05 +00:00
Devang Patel a3e9c9ca7b Emit dwarf variable info communicated by code generator through DBG_VALUE machine instructions.
This is a work in progress.

llvm-svn: 98556
2010-03-15 18:33:46 +00:00
Chris Lattner f71cb6c439 fix ShrinkDemandedOps to not leave dead nodes around,
fixing PR6607

llvm-svn: 98512
2010-03-14 19:46:02 +00:00
Chris Lattner 468decdda2 rewrite ShrinkDemandedOps to be faster and indent less,
no functionality change.

llvm-svn: 98511
2010-03-14 19:43:04 +00:00
Chris Lattner f1ed59a418 make -view-isel-dags print after the 'ShrinkDemandedOps' pass.
llvm-svn: 98509
2010-03-14 19:27:55 +00:00
Chris Lattner 9efbbcbe45 fix AsmPrinter::GetBlockAddressSymbol to always return a unique
label instead of trying to form one based on the BB name (which
causes collisions if the name is empty).  This fixes PR6608

llvm-svn: 98495
2010-03-14 17:53:23 +00:00
Chris Lattner ee2fbbc978 change the LabelSDNode to be EHLabelSDNode and make it hold
an MCSymbol.  Make the EH_LABEL MachineInstr hold its label
with an MCSymbol instead of ID.  Fix a bug in MMI.cpp which
would return labels named "Label4" instead of "label4".

llvm-svn: 98463
2010-03-14 02:33:54 +00:00
Dan Gohman 52cc041ee5 Attempt to make this debug output meaningful, both in the case of
multibyte opcodes and in the case of multiple scopes.

llvm-svn: 98036
2010-03-09 02:15:05 +00:00
Dan Gohman f6fb1e0d93 Print the correct index in the "match failed at index" message.
llvm-svn: 98013
2010-03-09 00:07:36 +00:00
Jakob Stoklund Olesen b0503beff1 Avoid creating bad PHI instructions when BR is being const-folded.
llvm-svn: 97836
2010-03-05 21:49:10 +00:00