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19 Commits

Author SHA1 Message Date
Igor Breger 70583606b1 [X86][AVX-512] Allow EVEX encoded instruction selection when available for mul v8i32. 
Differential Revision: https://reviews.llvm.org/D32679

llvm-svn: 302127
 2017-05-04 07:34:58 +00:00
Igor Breger 131008fbcb Change AVX512 braodcastsd/ss patterns interaction with spilling . New implementation take a scalar register and generate a vector without COPY_TO_REGCLASS (turn it into a VR128 register ) .The issue is that during register allocation we may spill a scalar value using 128-bit loads and stores, wasting cache bandwidth. 
Differential Revision: http://reviews.llvm.org/D19579

llvm-svn: 268190
 2016-05-01 08:40:00 +00:00
Igor Breger 1360f4db47 AVX512: Fix predicate of AVX pcmpeqw/b , pcmpgtb/w/d instructions . AVX512 version of this instructions return result in kmask register, so AVX patterns should not be disabled. 
Differential Revision: http://reviews.llvm.org/D17517

llvm-svn: 261619
 2016-02-23 08:55:33 +00:00
Igor Breger 0aeda37464 AVX512: VPBROADCASTB/W/D/Q from GPR intrinsics implementation. 
Differential Revision: http://reviews.llvm.org/D16813

llvm-svn: 260024
 2016-02-07 08:30:50 +00:00
Elena Demikhovsky 86528270b9 AVX-512: Fixed a bug in FMA instruction selection on KNL 
The FMA instruction was selected from AVX2 set instead of AVX-512

Differential Revision: http://reviews.llvm.org/D16884

llvm-svn: 259792
 2016-02-04 15:11:11 +00:00
Igor Breger b1bd47ca1a AVX512: Fix vpmovzxbw predicate for AVX1/2 instructions. 
Differential Revision: http://reviews.llvm.org/D16595

llvm-svn: 258915
 2016-01-27 08:57:46 +00:00
Igor Breger 7b46b4e798 AVX512BW: Enable packed word shift for 512bit vector. Enable lowering scalar immidiate shift v64i8 .Fix predicate for AVX1/2 shifts. 
Differential Revision: http://reviews.llvm.org/D15713

llvm-svn: 256324
 2015-12-23 08:06:50 +00:00
Igor Breger 1f78296869 AVX512: Implemented encoding, intrinsics and DAG lowering for VMOVDDUP instructions. 
Differential Revision: http://reviews.llvm.org/D14702

llvm-svn: 253548
 2015-11-19 08:26:56 +00:00
Igor Breger 24cab0fa06 AVX512: Implemented encoding and intrinsics for VMOVSHDUP/VMOVSLDUP instructions. 
Differential Revision: http://reviews.llvm.org/D14322

llvm-svn: 253185
 2015-11-16 07:22:00 +00:00
Igor Breger 3ff8ef9eb7 Revert r253160. 
It broke layering violation. Reproducible with BUILD_SHARED_LIBS=ON.

llvm-svn: 253163
 2015-11-15 12:19:11 +00:00
Igor Breger aa40ddd3ba AVX512: Implemented encoding and intrinsics for VMOVSHDUP/VMOVSLDUP instructions. 
Differential Revision: http://reviews.llvm.org/D14322

llvm-svn: 253160
 2015-11-15 07:23:13 +00:00
Igor Breger b6b27af46a AVX512 : Implemented encoding and DAG lowering for VMOVHPS/PD and VMOVLPS/PD instructions. 
Differential Revision: http://reviews.llvm.org/D14492

llvm-svn: 252592
 2015-11-10 07:09:07 +00:00
Igor Breger 21296d230a AVX512: Implemented encoding and intrinsics for VPBROADCASTB/W/D/Q instructions. 
Differential Revision: http://reviews.llvm.org/D13884

llvm-svn: 250819
 2015-10-20 11:56:42 +00:00
Igor Breger defab3c1ef AVX512: vpextrb/w/d/q and vpinsrb/w/d/q implementation. 
This instructions doesn't have intrincis.
Added tests for lowering and encoding.

Differential Revision: http://reviews.llvm.org/D12317

llvm-svn: 249688
 2015-10-08 12:55:01 +00:00
Asaf Badouh d2c3599c5f [X86][AVX512VLBW] add support in byte shift and SAD 
add byte shift left/right
add SAD - compute sum of absolute differences

Differential Revision: http://reviews.llvm.org/D12479

llvm-svn: 246654
 2015-09-02 14:21:54 +00:00
Igor Breger a6297c701e AVX512: Implemented encoding and intrinsics for vshufps/d. 
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D11709

llvm-svn: 246640
 2015-09-02 10:50:58 +00:00
Igor Breger 2ae0fe3ac3 AVX512: Implemented encoding and intrinsics for vpalignr 
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D12270

llvm-svn: 246428
 2015-08-31 11:14:02 +00:00
Igor Breger 87e6397fb1 AVX : Fix ISA disabling in case AVX512VL , some instructions should be disabled only if AVX512BW and AVX512VL present. 
Tests added.

Differential Revision: http://reviews.llvm.org/D11414

llvm-svn: 242987
 2015-07-23 07:11:14 +00:00
Igor Breger 096e8b0995 AVX : Fix ISA disabling in case AVX512VL , some instructions should be disabled only if AVX512BW present. 
Tests added.

Differential Revision: http://reviews.llvm.org/D11122

llvm-svn: 242270
 2015-07-15 07:08:10 +00:00