Commit Graph

126 Commits

Author SHA1 Message Date
Petar Jovanovic d4349f3bf6 [mips] Add support for Virtualization ASE
This includes

  Instructions: tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr, hypcall
                mfgc0, mtgc0, mfhgc0, mthgc0, dmfgc0, dmtgc0,

  Assembler directives: .set virt, .set novirt, .module virt, .module novirt

  Attribute: virt

  .MIPS.abiflags: VZ (0x100)

Patch by Vladimir Stefanovic.

Differential Revision: https://reviews.llvm.org/D44905

llvm-svn: 331024
2018-04-27 09:12:08 +00:00
Simon Dardis 7bc8ad5849 [mips] Spectre variant two mitigation for MIPSR2
This patch provides mitigation for CVE-2017-5715, Spectre variant two,
which affects the P5600 and P6600. It implements the LLVM part of
-mindirect-jump=hazard. It is _not_ enabled by default for the P5600.

The migitation strategy suggested by MIPS for these processors is to use
hazard barrier instructions. 'jalr.hb' and 'jr.hb' are hazard
barrier variants of the 'jalr' and 'jr' instructions respectively.

These instructions impede the execution of instruction stream until
architecturally defined hazards (changes to the instruction stream,
privileged registers which may affect execution) are cleared. These
instructions in MIPS' designs are not speculated past.

These instructions are used with the attribute +use-indirect-jump-hazard
when branching indirectly and for indirect function calls.

These instructions are defined by the MIPS32R2 ISA, so this mitigation
method is not compatible with processors which implement an earlier
revision of the MIPS ISA.

Performance benchmarking of this option with -fpic and lld using
-z hazardplt shows a difference of overall 10%~ time increase
for the LLVM testsuite. Certain benchmarks such as methcall show a
substantially larger increase in time due to their nature.

Reviewers: atanasyan, zoran.jovanovic

Differential Revision: https://reviews.llvm.org/D43486

llvm-svn: 325653
2018-02-21 00:06:53 +00:00
Simon Dardis 730fdb73a1 [mips] Correct c.cond.fmt instruction definition.
Permit explicit $fcc<X> operand in c.cond.fmt instruction.

Add c.cond.fmt to the MIPS to microMIPS instruction mapping table.

Check that $fcc1 - $fcc7 are unusable for MIPS-I to MIPS-III for
c.cond.fmt, bc1t, bc1f.

Reviewers: seanbruno, zoran.jovanovic, vkalintiris

Differential Revision: https://reviews.llvm.org/D24510

llvm-svn: 292117
2017-01-16 13:55:58 +00:00
Simon Dardis ba92b034bf Revert "[mips] Fix c.<cc>.<fmt> instruction definition."
This reverts commit r281022. Mips buildbot broke, due to unhandled register
class FCC.

llvm-svn: 281033
2016-09-09 11:06:01 +00:00
Simon Dardis 8efa979029 [mips] Fix c.<cc>.<fmt> instruction definition.
As part of this effort, remove MipsFCmp nodes and use tablegen
patterns rather than custom lowering through C++.

Unexpectedly, this improves codesize for microMIPS as previous floating
point setcc expansions would materialize 0 and 1 into GPRs before using
the relevant mov[tf].[sd] instruction. Now $zero is used directly.

Reviewers: dsanders, vkalintiris, zoran.jovanovic

Differential Review: https://reviews.llvm.org/D23118

llvm-svn: 281022
2016-09-09 09:22:52 +00:00
Hrvoje Varga dbe4d96b4f [mips][microMIPS] Implement DBITSWAP, DLSA and LWUPC and add tests for AUI instructions
Differential Revision: https://reviews.llvm.org/D16452

llvm-svn: 280909
2016-09-08 07:41:43 +00:00
Daniel Sanders e8efff373a [mips] MIPS32R6 compact branch support
Summary:
MIPSR6 introduces a class of branches called compact branches. Unlike the
traditional MIPS branches which have a delay slot, compact branches do not
have a delay slot. The instruction following the compact branch is only
executed if the branch is not taken and must not be a branch.

It works by generating compact branches for MIPS32R6 when the delay slot
filler cannot fill a delay slot. Then, inspecting the generated code for
forbidden slot hazards (a compact branch with an adjacent branch or other
CTI) and inserting nops to clear this hazard.

Patch by Simon Dardis.

Reviewers: vkalintiris, dsanders

Subscribers: MatzeB, dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D16353

llvm-svn: 263444
2016-03-14 16:24:05 +00:00
Zoran Jovanovic 8eb8c9861d [mips] Add support for branch-likely pseudo-instructions
Differential Revision: http://reviews.llvm.org/D10537

llvm-svn: 247697
2015-09-15 15:06:26 +00:00
Vasileios Kalintiris 974d409259 [mips] Added support for the ERETNC instruction.
Summary: This required adding the instruction predicate HasMips32r5.

Patch by Scott Egerton.

Reviewers: dsanders, vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11136

llvm-svn: 242666
2015-07-20 12:28:56 +00:00
Kai Nacke 3adf9b8d80 [mips] Add new format for dmtc2/dmfc2 for Octeon CPUs.
Octeon CPUs use dmtc2 rt,imm16 and dmfcp2 rt,imm16 for the crypto coprocessor.
E.g. dmtc2 rt,0x4057 starts calculation of sha-1.

I had to introduce a new deconding namespace to avoid a decoding conflict.

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D10083

llvm-svn: 238439
2015-05-28 16:23:16 +00:00
Zoran Jovanovic b59a541926 [mips][microMIPSr6] Implement mips32 to microMIPSr6 mapping support
Differential Revision: http://reviews.llvm.org/D8661

llvm-svn: 235505
2015-04-22 13:27:34 +00:00
Kai Nacke 63072f81b3 [mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132
This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132.
It also includes patterns for instruction selection and test cases.

Reviewed by D. Sanders

llvm-svn: 226573
2015-01-20 16:10:51 +00:00
Daniel Sanders b4484d62ad [mips] Add synci instruction.
Patch by Amaury Pouly

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6421

llvm-svn: 222899
2014-11-27 17:28:10 +00:00
Jozef Kolek dc62fc4a8f [mips][microMIPS] Implement SDBBP and RDHWR instructions.
Differential Revision: http://reviews.llvm.org/D5240

llvm-svn: 222347
2014-11-19 11:25:50 +00:00
Daniel Sanders f28bf76d88 Revert: r215698 - Current implementation of c.cond.fmt instructions only accept default cc0 register...
It causes a number of regressions when -fintegrated-as is enabled. This happens
because there are codegen-only instructions that incorrectly uses the first
operand as the encoding for the $fcc register. The regressions do not occur when
-via-file-asm is also given.

llvm-svn: 215847
2014-08-17 19:47:47 +00:00
Vladimir Medic 8d380fa37a Current implementation of c.cond.fmt instructions only accept default cc0 register. This patch enables the instruction to accept other fcc registers. The aliases with default fcc0 registers are also defined.
llvm-svn: 215698
2014-08-15 09:29:30 +00:00
Daniel Sanders e6198bf886 [mips] Added support for assembling sdbbp.
Summary:
This instruction is re-encoded in MIPS32r6/MIPS64r6 without changing the
restrictions. We hadn't implemented it for earlier ISA's so it has been added to those too.

Differential Revision: http://reviews.llvm.org/D4265

llvm-svn: 211590
2014-06-24 13:00:32 +00:00
Daniel Sanders c171f65a87 [mips] Add cache and pref instructions
Summary:
cache and pref were added in MIPS-III, and MIPS32 but were re-encoded in
MIPS32r6/MIPS64r6 to use a 9-bit offset rather than the 16-bit offset
available to earlier cores.

Resolved the decoding conflict between pref and lwc3.

Depends on D4115

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D4116

llvm-svn: 210900
2014-06-13 13:15:59 +00:00
Matheus Almeida 595fcab2d0 [mips] Implement jr.hb and jalr.hb (Jump Register and Jump and Link Register with Hazard Barrier).
Summary: These instructions are available in ISAs >= mips32/mips64. For mips32r6/mips64r6, jr.hb has a new encoding format.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D4019

llvm-svn: 210654
2014-06-11 15:05:56 +00:00
Daniel Sanders 8dcb116a3e [mips] Implement tlbp, tlbr, tlbwi, and tlbwr
Reviewers: vmedic, dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3571

llvm-svn: 208301
2014-05-08 11:51:18 +00:00
Daniel Sanders 3dc2c016a6 [mips] Split Instruction.Predicates into smaller lists and re-join them with !listconcat
Summary:
The overall idea is to chop the Predicates list into subsets that are
usually overridden independently. This allows subclasses to partially
override the predicates of their superclasses without having to re-add all
the existing predicates.

This patch starts the process by moving HasStdEnc into a new
EncodingPredicates list and almost everything else into
AdditionalPredicates.

It has revealed a couple likely bugs where 'let Predicates' has removed
the HasStdEnc predicate.

No functional change (confirmed by diffing tablegen-erated files).

Depends on D3549, D3506

Reviewers: vmedic

Differential Revision: http://reviews.llvm.org/D3550

llvm-svn: 208184
2014-05-07 10:27:09 +00:00
Kai Nacke 6da86e8529 [mips] Add Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu.
This patch adds the Octeon cnMips instructions seqi/snei and v3mulu/vmm0/vmulu.
It is only for the assembler. Test case is included.

Reviewed by: Daniel.Sanders@imgtec.com

llvm-svn: 205631
2014-04-04 16:21:59 +00:00
Daniel Sanders 442f1a12f1 [mips] Implement ehb, ssnop, and pause in assembler
Summary: Add negative tests for pause

Reviewers: matheusalmeida

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3246

llvm-svn: 205537
2014-04-03 13:21:51 +00:00
Kai Nacke 13673ac704 [mips] Add more Octeon cnMips instructions
Adds the instructions ext/ext32/cins/cins32.
It also changes pop/dpop to accept the two operand version and
adds a simple pattern to generate baddu.
Tests for the two operand versions (including baddu/dmul/dpop/pop)
and the code generation pattern for baddu are included.

Reviewed by: Daniel.Sanders@imgtec.com

llvm-svn: 205449
2014-04-02 18:40:43 +00:00
Kai Nacke af47f60f83 [mips] Add Octeon cnMips instructions mtmX and mtpX
Adds the Octeon cnMips instructions "load multiplier register MPLx" and "load product register Px".
Includes tests.

Reviews by: Daniel.Sanders@imgtec.com

llvm-svn: 205343
2014-04-01 18:35:26 +00:00
Kai Nacke 93fe5e810d [MIPS] Add cpu octeon and some instructions
The Octeon cpu from Cavium Networks is mips64r2 based and has an extended
instruction set. In order to utilize this with LLVM, a new cpu feature "octeon"
and a subtarget feature "cnmips" is added. A small set of new instructions
(baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and
dpop instructions with option -mcpu=octeon or -mattr=+cnmips.

llvm-svn: 204337
2014-03-20 11:51:58 +00:00
Zoran Jovanovic 87d13e5ec1 Implementation of microMIPS 16-bit instructions MOVE and JALR.
Differential Revision: http://llvm-reviews.chandlerc.com/D3112

llvm-svn: 204325
2014-03-20 10:18:24 +00:00
Zoran Jovanovic 8876be39c7 Support for microMIPS FPU instructions 2.
llvm-svn: 198009
2013-12-25 10:09:27 +00:00
Zoran Jovanovic ce02486d16 Support for microMIPS FPU instructions 1.
llvm-svn: 197815
2013-12-20 15:44:08 +00:00
Zoran Jovanovic 8e918c3c4d Support for microMIPS control instructions.
llvm-svn: 197696
2013-12-19 16:25:00 +00:00
Zoran Jovanovic ccb70caa13 Support for microMIPS trap instruction with immediate operands.
llvm-svn: 194569
2013-11-13 13:15:03 +00:00
Zoran Jovanovic c18b6d1083 Support for microMIPS trap instructions 1.
llvm-svn: 194205
2013-11-07 14:35:24 +00:00
Zoran Jovanovic 8a80aa76c8 Support for microMIPS branch instructions.
llvm-svn: 193992
2013-11-04 14:53:22 +00:00
Zoran Jovanovic 507e084a18 Support for microMIPS jump instructions
llvm-svn: 193623
2013-10-29 16:38:59 +00:00
Zoran Jovanovic fc26cfcde7 Fixed bug when generating Load Upper Immediate microMIPS instruction.
llvm-svn: 190746
2013-09-14 07:35:41 +00:00
Zoran Jovanovic ab85278137 Support for misc microMIPS instructions.
llvm-svn: 190744
2013-09-14 06:49:25 +00:00
Akira Hatanaka 2c544d8ed5 [mips] Make "b" (unconditional branch) a pseudo. "b" is an assembly idiom, which is
equivalent to "beq $zero, $zero, offset".

llvm-svn: 190220
2013-09-06 23:40:15 +00:00
Vladimir Medic 457ba56b05 This patch adds support for microMIPS Move to/from HI/LO instructions. Test cases are included in patch.
llvm-svn: 190152
2013-09-06 12:53:21 +00:00
Vladimir Medic e0fbb44a48 This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch.
llvm-svn: 190148
2013-09-06 12:41:17 +00:00
Vladimir Medic 8277c1874a This patch implements trap instructions for mips. The test cases are added.
llvm-svn: 189213
2013-08-26 10:02:40 +00:00
Vladimir Medic 939877ee14 This patch implements ei and di instructions for mips. Test cases are added.
llvm-svn: 188176
2013-08-12 13:07:23 +00:00
Vladimir Medic d3dade29f5 Moving definition of MnemonicContainsDot field from class Instruction to class AsmParser as suggested.
llvm-svn: 187569
2013-08-01 09:25:27 +00:00
Akira Hatanaka 8f69d7f0c0 [mips] Delete instruction format for "bal".
llvm-svn: 187443
2013-07-30 20:42:19 +00:00
Akira Hatanaka 8bce21c154 [mips] Fix FP conditional move instructions to have explicit FP condition code
register operands.

llvm-svn: 187242
2013-07-26 20:51:20 +00:00
Akira Hatanaka 1fb1b8b811 [mips] Fix FP branch instructions to have explicit FP condition code register
operands.

llvm-svn: 187238
2013-07-26 20:13:47 +00:00
Vladimir Medic 29410f9c91 Implement eret and deret(return from exception) instructions for Mips. Test examples are given.
llvm-svn: 186507
2013-07-17 14:05:19 +00:00
Vladimir Medic 64828a1f73 This patch represents Mips utilization of r186388 code that alows asm matcher to emit mnemonics contain '.' characters. This makes asm parser code simpler and more efficient.
llvm-svn: 186397
2013-07-16 10:07:14 +00:00
Vladimir Medic bcf1ca08e0 Add support for Mips break and syscall insructions. The corresponding test cases are added.
llvm-svn: 186151
2013-07-12 09:25:35 +00:00
Vladimir Medic 524ad0e46e Reverting commit r185999 due to buildboot failure.
llvm-svn: 186000
2013-07-10 12:26:26 +00:00
Vladimir Medic e84de1e101 Add support for Mips break and syscall insructions. The corresponding test cases are added.
llvm-svn: 185999
2013-07-10 10:18:10 +00:00