055192ccd3
[mips] Enable spilling and reloading of the dsp register set.
...
The dsp register class is an alias of the gpr register class, so
we have to define instructions for spilling and reloading.
Reviewers: atanasyan
Differential Revision: https://reviews.llvm.org/D38038
llvm-svn: 314798
2017-10-03 13:45:49 +00:00
e9abe8816c
[mips][microMIPS][DSP] Implement BALIGN, BITREV, BPOSGE32, CMP*, CMPGDU*, CMPGU* and CMPU* instructions
...
Differential Revision: http://reviews.llvm.org/D16182
llvm-svn: 269752
2016-05-17 09:32:58 +00:00
6f09cdfd48
[mips][microMIPS] Implement APPEND, BPOSGE32C, MODSUB, MULSA.W.PH and MULSAQ_S.W.PH instructions
...
Differential Revision: http://reviews.llvm.org/D14117
llvm-svn: 269408
2016-05-13 11:32:53 +00:00
f8bb23e509
[mips] Range check uimm16 and fix several bugs this revealed.
...
Summary:
The bugs were:
* teq and similar take 4-bit unsigned immediates on microMIPS.
* teqi and similar have side-effects like teq do.
* shll_s.w and shra_r.w take 5-bit unsigned immediates.
* The various DSP ext* instructions take a 5-bit immediate.
* repl.qh takes an 8-bit unsigned immediate.
* repl.ph takes a 10-bit unsigned immediate.
* rddsp/wrdsp take a 10-bit unsigned immediate.
* teqi and similar take signed 16-bit immediates (10-bit for microMIPS).
* Out-of-range immediate macros for or/xor take a simm32/simm64 depending
on architecture. I'll fix the simm64 case properly when I reach simm32.
lui is a bit more lenient than GAS and accepts signed immediates in addition
to unsigned. This is because MipsMCExpr can produce signed values when
constant folding and it currently lacks a way of knowing it should fold to
an unsigned value.
Reviewers: vkalintiris
Subscribers: dsanders, llvm-commits
Differential Revision: http://reviews.llvm.org/D15446
llvm-svn: 259360
2016-02-01 15:13:31 +00:00
252cca555f
[mips][microMIPS][DSP] Implement PACKRL.PH, PICK.PH, PICK.QB, SHILO, SHILOV and WRDSP instructions
...
Differential Revision: http://reviews.llvm.org/D14429
llvm-svn: 255991
2015-12-18 08:59:37 +00:00
672b0f5582
[mips][microMIPS] Implement PREPEND, RADDU.W.QB, RDDSP, REPL.PH, REPL.QB, REPLV.PH, REPLV.QB and MTHLIP instructions
...
Differential Revision: http://reviews.llvm.org/D14527
llvm-svn: 254496
2015-12-02 09:31:24 +00:00
c03957f049
[mips][microMIPS] Implement LBUX, LHX, LWX, MAQ_S[A].W.PHL, MAQ_S[A].W.PHR, MFHI, MFLO, MTHI and MTLO instructions
...
Differential Revision: http://reviews.llvm.org/D14436
llvm-svn: 254297
2015-11-30 12:58:39 +00:00
56f3b0e410
[mips][microMIPS] Implement PRECR.QB.PH, PRECR_SRA[_R].PH.W, PRECRQ.PH.W, PRECRQ.QB.PH, PRECRQU_S.QB.PH and PRECRQ_RS.PH.W instructions
...
Differential Revision: http://reviews.llvm.org/D14605
llvm-svn: 254291
2015-11-30 08:37:38 +00:00
b65518c15c
[mips][microMIPS] Implement MUL[_S].PH, MULEQ_S.W.PHL, MULEQ_S.W.PHR, MULEU_S.PH.QBL, MULEU_S.PH.QBR, MULQ_RS.PH, MULQ_RS.W, MULQ_S.PH and MULQ_S.W instructions
...
Differential Revision: http://reviews.llvm.org/D14280
llvm-svn: 253651
2015-11-20 07:14:52 +00:00
78409019d9
[mips][microMIPS] Implement DPS.W.PH, DPSQ_S.W.PH, DPSQ_SA.L.W, DPSQX_S.W.PH, DPSQX_SA.W.PH, DPSU.H.QBL, DPSU.H.QBR and DPSX.W.PH instructions
...
Differential Revision: http://reviews.llvm.org/D14058
llvm-svn: 253443
2015-11-18 07:41:35 +00:00
72a7f9c1f5
[mips][microMIPS] Implement EXTP, EXTPDP, EXTPDPV, EXTPV, EXTR[_RS].W, EXTR_S.H, EXTRV[_RS].W and EXTRV_S.H instructions
...
Differential Revision: http://reviews.llvm.org/D14174
llvm-svn: 253332
2015-11-17 12:54:15 +00:00
246b21f66a
[mips][microMIPS] Implement SUBQ[_S].PH, SUBQ_S.W, SUBQH[_R].PH, SUBQH[_R].W, SUBU[_S].PH, SUBU[_S].QB and SUBUH[_R].QB instructions
...
Differential Revision: http://reviews.llvm.org/D14114
llvm-svn: 253329
2015-11-17 10:11:22 +00:00
3e0588d033
[mips][microMIPS] Implement PRECEQ.W.PHL, PRECEQ.W.PHR, PRECEQU.PH.QBL, PRECEQU.PH.QBLA, PRECEQU.PH.QBR, PRECEQU.PH.QBRA, PRECEU.PH.QBL, PRECEU.PH.QBLA, PRECEU.PH.QBR and PRECEU.PH.QBRA instructions
...
Differential Revision: http://reviews.llvm.org/D14279
llvm-svn: 253326
2015-11-17 09:43:29 +00:00
32fb5c40d2
[mips][microMIPS] Implement SHRA[_R].PH, SHRAV[_R].PH, SHRAV[_R].QB, SHRAV_R.W, SHRA_R.W, SHRL.PH, SHRL.QB, SHRLV.PH and SHRLV.QB instructions
...
Differential Revision: http://reviews.llvm.org/D14010
llvm-svn: 253041
2015-11-13 13:14:25 +00:00
2cf61020b8
[mips][microMIPS] Implement SHLL.PH, SHLL_S.PH, SHLL.QB, SHLLV.PH, SHLLV_S.PH, SHLLV.QB, SHLLV_S.W, SHLL_S.W, SHRA.QB and SHRA_R.QB instructions
...
Differential Revision: http://reviews.llvm.org/D13929
llvm-svn: 251098
2015-10-23 06:39:29 +00:00
5292083584
[mips][microMIPS] Implement ADDQ.PH, ADDQ_S.W, ADDQH.PH, ADDQH.W, ADDSC, ADDU.PH, ADDU_S.QB, ADDWC and ADDUH.QB instructions
...
Differential Revision: http://reviews.llvm.org/D13130
llvm-svn: 250685
2015-10-19 07:16:26 +00:00
d0a7d6e4ee
[mips][microMIPS] Implement ABSQ.QB, ABSQ_S.PH, ABSQ_S.W, ABSQ_S.QB, INSV, MADD, MADDU, MSUB, MSUBU, MULT and MULTU instructions
...
Differential Revision: http://reviews.llvm.org/D13721
llvm-svn: 250683
2015-10-19 06:34:44 +00:00
54b1eb4c73
[mips][microMIPS] Implement DPA.W.PH, DPAQ_S.W.PH, DPAQ_SA.L.W, DPAQX_S.W.PH, DPAQX_SA.W.PH, DPAU.H.QBL, DPAU.H.QBR and DPAX.W.PH instructions
...
Differential Revision: http://reviews.llvm.org/D13376
llvm-svn: 250382
2015-10-15 08:59:45 +00:00
2e386d3d07
[mips][micromips] Initial support for micrmomips DSP instructions and addu.qb implementation
...
Differential Revision: http://reviews.llvm.org/D12798
llvm-svn: 250058
2015-10-12 16:07:25 +00:00
Simon Dardis