Commit Graph

288664 Commits

Author SHA1 Message Date
Alexey Bataev 354df2eeab [OPENMP] Analyze the type of the mapped entity instead of its base.
If the mapped entity is a data member, we erroneously checked the type
of its base rather than the type of the mapped entity itself.

llvm-svn: 331385
2018-05-02 18:44:10 +00:00
Martin Storsjo d0b5034b8a [COFF, ARM64] Hook up a few remaining relocations
Differential Revision: https://reviews.llvm.org/D46355

llvm-svn: 331384
2018-05-02 18:24:37 +00:00
Farhana Aleen 07e612340f [AMDGPU] A trivial fix for a buildbot failure caused by "commit 224a839fcbbead221f872cd32a1dd0c308d37299".
Author: FarhanaAleen
llvm-svn: 331383
2018-05-02 18:16:39 +00:00
Petr Hosek 716d9949f6 [sanitizer] Fix Fuchsia ReadBinaryName not to crash when uninitialized
If the sanitizer runtime is loaded in a binary that doesn't really
support it, then __sanitizer_startup_hook will never have been
called to initialize StoredArgv. This case can't be supported, but
its failure mode shouldn't be to crash in sanitizer_common internals.

Patch By: mcgrathr

Differential Revision: https://reviews.llvm.org/D46344

llvm-svn: 331382
2018-05-02 18:08:47 +00:00
Daniel Sanders 8d0d1aa229 [reassociate] Fix excessive revisits when processing long chains of reassociatable instructions.
Summary:
Some of our internal testing detected a major compile time regression which I've
tracked down to:
    r278938 - Revert "Reassociate: Reprocess RedoInsts after each inst".
It appears that processing long chains of reassociatable instructions causes
non-linear (potentially exponential) growth in the number of times an
instruction is revisited. For example, the included test revisits instructions
220 times in a 20-instruction test.

It appears that r278938 reversed the order instructions were visited and that
this is preventing scheduled revisits from being cancelled as a result of
visiting the instructions naturally during normal processing. However, simply
reversing the order also harmed the generated code. Upon closer inspection, it
was discovered that revisits occurred in the opposite order to the first pass
(Thanks to escha for spotting that).

This patch makes the revisit order consistent with the first pass which allows
more revisits to be cancelled. This does appear to have a small impact on the
generated code in few cases but it significantly reduces compile-time.

After this patch, our internal test that was most affected by the regression
dropped from ~2 million revisits to ~4k resulting in Reassociate having 0.46%
of the runtime it had before (99.54% improvement).

Here's the summaries reported by lnt for the LLVM test-suite with --benchmarking-only:
| metric         | geomean before patch | geomean after patch | delta   |
| -----          | -----                | -----               | -----   |
| compile time   | 0.1956               | 0.1261              | -35.54% |
| execution time | 0.3240               | 0.3237              | -       |
| code size      | 7365.4459            | 7365.6079           | -       |

The results have a few wins and losses on compile-time, mostly in the +/- 2.5% range. There was one outlier though:
| Performance Regressions - compile_time | Δ | Previous | Current |
| MultiSource/Benchmarks/ASC_Sequoia/CrystalMk/CrystalMk | 9.82% | 2.0473 | 2.2483 |

Reviewers: javed.absar, dberlin

Reviewed By: dberlin

Subscribers: kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D45734

llvm-svn: 331381
2018-05-02 17:59:16 +00:00
Simon Pilgrim 819f218f07 [X86] Cleanup WriteFShuffle/WriteFVarShuffle (+256 variants) scheduler classes with more common default values
llvm-svn: 331380
2018-05-02 17:58:50 +00:00
Volodymyr Sapsai dea80d5174 Emit an error when mixing <stdatomic.h> and <atomic>
Atomics in C and C++ are incompatible at the moment and mixing the
headers can result in confusing error messages.

Emit an error explicitly telling about the incompatibility. Introduce
the macro `__ALLOW_STDC_ATOMICS_IN_CXX__` that allows to choose in C++
between C atomics and C++ atomics.

rdar://problem/27435938

Reviewers: rsmith, EricWF, mclow.lists

Reviewed By: mclow.lists

Subscribers: jkorous-apple, christof, bumblebritches57, JonChesterfield, smeenai, cfe-commits

Differential Revision: https://reviews.llvm.org/D45470

llvm-svn: 331379
2018-05-02 17:56:45 +00:00
Volodymyr Sapsai c0a278aada Emit an error when mixing <stdatomic.h> and <atomic>
Atomics in C and C++ are incompatible at the moment and mixing the
headers can result in confusing error messages.

Emit an error explicitly telling about the incompatibility. Introduce
the macro `__ALLOW_STDC_ATOMICS_IN_CXX__` that allows to choose in C++
between C atomics and C++ atomics.

rdar://problem/27435938

Reviewers: rsmith, EricWF, mclow.lists

Reviewed By: mclow.lists

Subscribers: jkorous-apple, christof, bumblebritches57, JonChesterfield, smeenai, cfe-commits

Differential Revision: https://reviews.llvm.org/D45470

llvm-svn: 331378
2018-05-02 17:50:43 +00:00
Alexey Bataev dcc815d015 [OPENMP] Do not emit warning for implicitly declared target functions.
Since upcoming OpenMP 5.0 functions can be mapped implicitly as declare
target and we should not emit warnings for such functions.

llvm-svn: 331377
2018-05-02 17:39:00 +00:00
Krzysztof Parzyszek 5e3aba8251 Add assertion to padding size calculation, NFC
The size of an object cannot be less than the emitted size of all the
contained elements. This would cause an overflow in padding size
calculation. Add an assert to catch this.

Patch by Suyog Sarda.

llvm-svn: 331376
2018-05-02 17:20:22 +00:00
Adrian Prantl 6e9f77126b Silence compiler warning.
llvm-svn: 331375
2018-05-02 17:11:43 +00:00
Pavel Labath 47776cbd2c Fix gdb-remote qMemoryRegionInfo unit tests for xml-enabled builds
In case we are building with xml enabled, the GetMemoryRegionInfo
function will send extra packets to query te extended memory map, which
the tests were not expecting.

Add an expectation for this to the test. Right now, it's just a basic
one which pretends we don't support the extension, however, it would be
also interesting the add a test which verifies the extension-enabled
case.

I also noticed that the test does a pretty lousy job of validating the
returned memory region info, so I add a couple of extra assertions to
improve that.

llvm-svn: 331374
2018-05-02 17:00:33 +00:00
Adrian Prantl d8f460e864 Enable AUTOBRIEF in doxygen configuration.
This brings the LLDB configuration closer to LLVM's and removes visual
clutter in the source code by removing the @brief commands from
comments.

This patch also reflows the paragraphs in all doxygen comments.

See also https://reviews.llvm.org/D46290.

Differential Revision: https://reviews.llvm.org/D46321

llvm-svn: 331373
2018-05-02 16:55:16 +00:00
Alexey Bataev 1ab3457319 [OPENMP] Enable c++ exceptions outside of the target constructs iff they are
enabled for the host.

If the compilation for the host enables C++ exceptions, but they are not
supported by the device, we still need to allow the code with the
exception handling constructs outside of the target regions.

llvm-svn: 331372
2018-05-02 16:52:07 +00:00
Farhana Aleen 150cb6d91a Revert "[AMDGPU] performAddCombine should run after DAG is legalized."
This reverts commit 6b97d2995566b4dddd6bf0d75579ff44501d4494.

llvm-svn: 331371
2018-05-02 16:48:52 +00:00
Jessica Paquette 8e71ee3c07 Add -foutline option to enable the MachineOutliner in AArch64
Since we've been working on productizing the MachineOutliner in AArch64, it
makes sense to provide a more user-friendly way to enable it.

This allows users of AArch64 to enable the outliner using -foutline instead
of -mllvm -enable-machine-outliner. Other, less mature implementations (e.g,
x86-64) can still enable the pass using the -mllvm option.

Also add a test to make sure it works.

llvm-svn: 331370
2018-05-02 16:42:51 +00:00
Simon Pilgrim a3a4df3708 [X86] Convert most remaining XOP uses of X86SchedWritePair scheduler classes to X86SchedWriteWidths.
llvm-svn: 331369
2018-05-02 16:25:41 +00:00
Farhana Aleen 2f4100f56e [AMDGPU] performAddCombine should run after DAG is legalized.
Summary: performAddCombine should run after DAG is legalized; Otherwise generic optimization
         in the DAGCombiner can optimize an addcarry+trunc into an addcarry instruction with
         illegal types.

Author: FarhanaAleen

Reviewed By: rampitec

Subscribers: llvm-commits, AMDGPU

Differential Revision: https://reviews.llvm.org/D46337

llvm-svn: 331368
2018-05-02 16:24:10 +00:00
Simon Pilgrim a53d330890 Fix line-endings. NFCI.
llvm-svn: 331367
2018-05-02 16:16:24 +00:00
Jan Vesely 616a38a693 clc_sqrt: Reuse unary_decl.inc
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Aaron Watry <awatry@gmail.com>
Tested-by: Aaron Watry <awatry@gmail.com>
llvm-svn: 331366
2018-05-02 16:06:52 +00:00
Alexey Bataev 6d94410914 [OPENMP] Support C++ member functions in the device constructs.
Added correct emission of the C++ member functions for the device
function when they are used in the device constructs.

llvm-svn: 331365
2018-05-02 15:45:28 +00:00
Philip Pfaffe f1fadea5ce Pass compiler arguments in the create_ll.sh script
Summary:
Occasionally you need an include or similar things to be configured
when making a new testcase. Allow passing these to the script and down to the
compiler calls.

Reviewers: grosser, Meinersbur, bollu

Reviewed By: Meinersbur

Subscribers: bollu, llvm-commits, pollydev

Differential Revision: https://reviews.llvm.org/D46359

llvm-svn: 331364
2018-05-02 15:27:32 +00:00
Philip Pfaffe e9ca17e9b6 Revert "[polly] [ScopInfo] Don't pre-compute the name of the Scop's region."
This reverts commit 0f9dc03765dc301fff7a52e2a0e1dd3e5f3130c5, r328666.

The change introduced a use-after-free, caused by the temporary name string
being destroyed after converting it to a StringRef.

llvm-svn: 331363
2018-05-02 14:55:39 +00:00
Clement Courbet d2ff5fb536 Re-land rL331357 "[X86] Fix scheduling info for VMPSADBWYrmi."
Without the rebase mess.

https://reviews.llvm.org/D46356

llvm-svn: 331362
2018-05-02 14:35:48 +00:00
Malcolm Parsons 099e4b2a92 [analyzer] Fix filename in cross-file HTML report
Summary:
The filename is currently taken from the start of the path, while the
line and column are taken from the end of the path.
This didn't matter until cross-file path reporting was added.

Reviewers: george.karpenkov, dcoughlin, vlad.tsyrklevich

Reviewed By: george.karpenkov, vlad.tsyrklevich

Subscribers: xazax.hun, szepet, a.sidorin, cfe-commits

Differential Revision: https://reviews.llvm.org/D45611

llvm-svn: 331361
2018-05-02 14:26:12 +00:00
Simon Pilgrim 86d9f23ded [X86] Cleanup WriteFMul scheduler classes with more common default values
Intel models were targeting x87 instead of packed sse.

llvm-svn: 331360
2018-05-02 14:25:32 +00:00
Simon Pilgrim f53ee8e640 Fix '32-bit shift implicitly converted to 64 bits' warning by using APInt::setBit instead.
llvm-svn: 331359
2018-05-02 14:22:30 +00:00
Alexey Bataev 18fa2323b6 [OPENMP] Emit names of the globals depending on target.
Some symbols are not allowed to be used as names on some targets. Patch
ries to unify the emission of the names of LLVM globals so they could be
used on different targets.

llvm-svn: 331358
2018-05-02 14:20:50 +00:00
Clement Courbet 0f1da8f365 Revert rL331355 "[X86] Fix scheduling info for VMPSADBWYrmi."
It contains unrelated changes.

llvm-svn: 331357
2018-05-02 13:54:38 +00:00
Clement Courbet a1a3095d88 [X86] Fix scheduling info for (V?)SQRTPDm on silvermont.
https://reviews.llvm.org/D46356

llvm-svn: 331356
2018-05-02 13:46:14 +00:00
Clement Courbet eeb2123a83 [X86] Fix scheduling info for VMPSADBWYrmi.
https://reviews.llvm.org/D46356

llvm-svn: 331355
2018-05-02 13:40:48 +00:00
Clement Courbet da54914cde [MIPS] Fix DIV/DIVU scheduling classes.
https://reviews.llvm.org/D46356.

llvm-svn: 331354
2018-05-02 13:37:28 +00:00
Simon Pilgrim a1f1a3bf94 [X86] Convert most remaining AVX512 uses of X86SchedWritePair scheduler classes to X86SchedWriteWidths.
We've dealt with the majority already.

llvm-svn: 331353
2018-05-02 13:32:56 +00:00
Sander de Smalen 659a48cd38 [AArch64][SVE] Asm: Support for LDR/STR fill and spill instructions.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar

Reviewed By: samparker

Differential Revision: https://reviews.llvm.org/D46270

llvm-svn: 331352
2018-05-02 13:32:39 +00:00
Simon Tatham 6a02604ee4 [TableGen] Don't quote variable name when printing !foreach.
An input !foreach expression such as !foreach(a, lst, !add(a, 1))
would be re-emitted by llvm-tblgen -print-records with the first
argument in quotes, giving !foreach("a", lst, !add(a, 1)), which isn't
valid TableGen input syntax.

Reviewers: nhaehnle

Reviewed By: nhaehnle

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D46352

llvm-svn: 331351
2018-05-02 13:17:26 +00:00
Pavel Labath e222d92707 Predicate.h: remove unused functions
The functions are unused, their comments are out of date with the
implementation, and the implementation is out of date with the rest of the code
base (it uses seconds(0) to mean infinite wait, whereas elsewhere we use the
Timeout class).

llvm-svn: 331350
2018-05-02 13:14:18 +00:00
Sander de Smalen 57da042e32 [AArch64][SVE] Asm: Support for scatter ST1 store instructions.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D46248

llvm-svn: 331349
2018-05-02 13:00:30 +00:00
Simon Dardis 694fde215e Revert "[mips] Correct the predicates of sign extension instructions"
I accidently committed this patch after asking for a review, but it has not
been reviewed yet.

This reverts r331346.

llvm-svn: 331348
2018-05-02 12:35:29 +00:00
Simon Pilgrim e8671ef434 [X86] Convert most remaining uses of X86SchedWritePair scheduler classes to X86SchedWriteWidths.
We've dealt with the majority already.

llvm-svn: 331347
2018-05-02 12:27:54 +00:00
Simon Dardis 7a36495bf7 [mips] Correct the predicates of sign extension instructions
And eliminate the duplication of those instructions for microMIPS32r6.

llvm-svn: 331346
2018-05-02 12:25:33 +00:00
Henry Wong e14e591c93 [analyzer] Add `TaintBugVisitor` to the ArrayBoundV2, DivideZero and VLASize.
Summary: Add `TaintBugVisitor` to the ArrayBoundV2, DivideZero, VLASize to be able to indicate where the taint information originated from.

Reviewers: NoQ, george.karpenkov, xazax.hun, a.sidorin

Reviewed By: NoQ

Subscribers: szepet, rnkovacs, cfe-commits, MTC

Differential Revision: https://reviews.llvm.org/D46007

llvm-svn: 331345
2018-05-02 12:11:22 +00:00
Peter Szecsi ef97252a2c [ASTImporter] Fix isa cast assert
Do early return if we can't import the found decl for a member expr.
This follows the pre-existing scheme, e.g with E->getMemberDecl().
E->getFoundDecl().getDecl() can be null when a member expression does
not involve lookup. It may involve a lookup in case of a using directive
which refers to a member function in a base class template.

We faced this assert during the CTU analysis of google::protobuf v3.5.2.
We tried hard to synthesize a minimal test example both by hand and by
executing creduce on multiple files. Unfortunately, we were unable to reduce
to such a minimal example, yet. Nevertheless, this fix solved the problem in
protobuf.

To reproduce the error one must execute the analyzer with
-Xclang -analyzer-config -Xclang experimental-enable-naive-ctu-analysis=true -Xclang -analyzer-config -Xclang ctu-dir=/path/to/ctu_dir

Patch by Gabor Marton!

Differential Revision: https://reviews.llvm.org/D46019

llvm-svn: 331344
2018-05-02 11:52:54 +00:00
Sander de Smalen 414d2358a4 [AArch64][SVE] Asm: Support for non-temporal, contiguous LDNT1/STNT1 load/store instructions.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar

Reviewed By: samparker

Differential Revision: https://reviews.llvm.org/D46269

llvm-svn: 331343
2018-05-02 11:48:49 +00:00
Florian Hahn 5912c667b0 [LoopInterchange] Update some loops to use range base for loops (NFC).
llvm-svn: 331342
2018-05-02 10:53:04 +00:00
Simon Dardis 6cfc9ba5e3 [mips] Correct the predicates for shifts.
Reviewers: smaksimovic, abeserminji, atanasyan

Differential Revision: https://reviews.llvm.org/D46123

llvm-svn: 331341
2018-05-02 09:55:49 +00:00
Simon Pilgrim e93fd5f1e4 [X86] Cleanup WriteFAdd/WriteFCmp scheduler classes with more common default values
Intel models were targeting x87 instead of packed sse.

Also fixes XOP's VFRCZ to use WriteFAdd/WriteFAddY.

llvm-svn: 331340
2018-05-02 09:18:49 +00:00
Sander de Smalen c1e44bdfc7 [AArch64][SVE] Asm: Support for LD1RQ load-and-replicate quad-word vector instructions.
Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, javed.absar

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D46250

llvm-svn: 331339
2018-05-02 08:49:08 +00:00
Piotr Padlewski f801205e48 Mark invariant.group.barrier as inaccessiblememonly
It turned out that readonly argmemonly is not enough.

  store 42, %p
  %b = barrier(%p)
  store 43, %b
the first store is dead, but because barrier was marked as
reading argument memory, it was considered alive. With
inaccessiblememonly it doesn't read the argument, but
it also can't be CSEd.

based on: https://reviews.llvm.org/D32006

llvm-svn: 331338
2018-05-02 08:22:07 +00:00
Bjorn Pettersson 1c5a05f32c [SelectionDAG] Selection of DBG_VALUE using a PHI node result (pt 2)
Summary:
This is a follow up to rL331182. A PHI node can be split up into
several MIR PHI nodes when being selected. When there is a
dbg.value intrinsic that uses the result of such a PHI node we
need to select several DBG_VALUE instructions, with fragment
expressions, in order to do a correct selection.

Reviewers: rnk, aprantl, vsk

Reviewed By: vsk

Subscribers: mattd, llvm-commits, JDevlieghere, aprantl, gbedwell, rnk

Tags: #debug-info

Differential Revision: https://reviews.llvm.org/D46329

llvm-svn: 331337
2018-05-02 06:56:38 +00:00
Matt Morehouse 7764a04af0 [libFuzzer] Don't short-circuit from CrashCallback.
Short-circuiting causes tests to fail on Mac since libFuzzer crashes
rather than exiting with an error code when an unexpected signal
happens.

llvm-svn: 331324
2018-05-02 02:55:28 +00:00