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Author SHA1 Message Date
Piotr Sobczak c48ceaf37b Revert "[AMDGPU] Set the CostPerUse value for vgpr registers." 
This reverts commit 728b878de6.

D76417 has caused vgpr count to go up significantly in real-world
graphics content.
 2020-04-20 22:47:31 +02:00
Jonathan Roelofs 17bc995388 [llvm] Fix more missing FileCheck directive colons 2020-04-13 10:16:29 -06:00
Jonathan Roelofs 7c5d2bec76 [llvm] Fix missing FileCheck directive colons 
https://reviews.llvm.org/D77352
 2020-04-06 09:59:08 -06:00
cdevadas 728b878de6 [AMDGPU] Set the CostPerUse value for vgpr registers. 
Apart from the argument registers, set the CostPerUse
value as per the ratio reg_index/allocation_granularity.
It is a pre-commit for introducing the scratch registers
in the ABI. This change should help in a balanced
register allocation.

Differential Revision: https://reviews.llvm.org/D76417
 2020-03-20 11:49:35 +05:30
Michael Liao 01a4b83154 [codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU. 
Summary:
- `dead-mi-elimination` assumes MIR in the SSA form and cannot be
  arranged after phi elimination or DeSSA. It's enhanced to handle the
  dead register definition by skipping use check on it. Once a register
  def is `dead`, all its uses, if any, should be `undef`.
- Re-arrange the DIE in RA phase for AMDGPU by placing it directly after
  `detect-dead-lanes`.
- Many relevant tests are refined due to different register assignment.

Reviewers: rampitec, qcolombet, sunfish

Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D72709
 2020-01-14 19:26:15 -05:00
Stanislav Mekhanoshin cd69e4c74c [AMDGPU] Fix bundle scheduling 
Bundles coming to scheduler considered free, i.e. zero latency.
Fixed.

Differential Revision: https://reviews.llvm.org/D72487
 2020-01-09 15:56:36 -08:00
Stanislav Mekhanoshin 450afcea39 [AMDGPU] Reserve all AGPRs on targets which do not have them 
Differential Revision: https://reviews.llvm.org/D65471

llvm-svn: 367347
 2019-07-30 19:29:33 +00:00
Stanislav Mekhanoshin 1dfae6fe50 [AMDGPU] use v32f32 for 3 mfma intrinsics 
These should really use v32f32, but were defined as v32i32
due to the lack of the v32f32 type.

Differential Revision: https://reviews.llvm.org/D64667

llvm-svn: 365972
 2019-07-12 22:42:01 +00:00
Stanislav Mekhanoshin 937ff6e701 [AMDGPU] gfx908 agpr spilling 
Differential Revision: https://reviews.llvm.org/D64594

llvm-svn: 365833
 2019-07-11 21:54:13 +00:00