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13 Commits

Author SHA1 Message Date
Stephen Lin f799e3f944 Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion. 
This was done with the following sed invocation to catch label lines demarking function boundaries:
    sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll
which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct.

llvm-svn: 186258
 2013-07-13 20:38:47 +00:00
Jim Grosbach 24e102a947 ARM: Improve codegen for generic vselect. 
Fall back to by-element insert rather than building it up on the stack.

rdar://14351991

llvm-svn: 185846
 2013-07-08 18:18:52 +00:00
Quentin Colombet 8e1fe84c3c Vext Lowering was missing opportunities 
llvm-svn: 167318
 2012-11-02 21:32:17 +00:00
Jim Grosbach 3e2c6f380c ARM VLDR/VSTR instructions don't need a size suffix. 
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.

llvm-svn: 144583
 2011-11-14 23:03:21 +00:00
Eli Friedman 74d1da5a05 Add missing correctness check to ARMTargetLowering::ReconstructShuffle. Fixes PR11129. 
llvm-svn: 142022
 2011-10-14 23:58:49 +00:00
Bill Wendling ebecb33307 Some minor cleanups based on feedback. 
llvm-svn: 127694
 2011-03-15 20:47:26 +00:00
Bill Wendling e1fd78f2bc Generate a VTBL instruction instead of a series of loads and stores when we 
can. As Nate pointed out, VTBL isn't super performant, but it *has* to be better
than this:

_shuf:
@ BB#0:       @ %entry
  push        {r4, r7, lr}
  add         r7, sp, #4
  sub         sp, #12
  mov         r4, sp
  bic         r4, r4, #7
  mov         sp, r4
  mov         r2, sp
  vmov        d16, r0, r1
  orr         r0, r2, #6
  orr         r3, r2, #7
  vst1.8      {d16[0]}, [r3]
  vst1.8      {d16[5]}, [r0]
  subs        r4, r7, #4
  orr         r0, r2, #5
  vst1.8      {d16[4]}, [r0]
  orr         r0, r2, #4
  vst1.8      {d16[4]}, [r0]
  orr         r0, r2, #3
  vst1.8      {d16[0]}, [r0]
  orr         r0, r2, #2
  vst1.8      {d16[2]}, [r0]
  orr         r0, r2, #1
  vst1.8      {d16[1]}, [r0]
  vst1.8      {d16[3]}, [r2]
  vldr.64     d16, [sp]
  vmov        r0, r1, d16
  mov         sp, r4
  pop         {r4, r7, pc}

The "illegal" testcase in vext.ll is no longer illegal.
<rdar://problem/9078775>

llvm-svn: 127630
 2011-03-14 23:02:38 +00:00
Bob Wilson 6f2b8966ca Lower some BUILD_VECTORS using VEXT+shuffle. 
Patch by Tim Northover.

llvm-svn: 123035
 2011-01-07 21:37:30 +00:00
Bob Wilson 411dfad981 Allow more cases of undef shuffle indices and add tests for them. 
llvm-svn: 111226
 2010-08-17 05:54:34 +00:00
Rafael Espindola 29dda21e96 Remove arm_apcscc from the test files. It is the default and doing this 
matches what llvm-gcc and clang now produce.

llvm-svn: 106221
 2010-06-17 15:18:27 +00:00
Dan Gohman c8054d90fb Eliminate more uses of llvm-as and llvm-dis. 
llvm-svn: 81293
 2009-09-09 00:09:15 +00:00
Bob Wilson f73af72d30 Add some tests for vext.16 and vext.32. 
llvm-svn: 79638
 2009-08-21 16:35:24 +00:00
Bob Wilson 32cd8550ce Add support for Neon VEXT (vector extract) shuffles. 
This is derived from a patch by Anton Korzh.  I modified it to recognize
the VEXT shuffles during legalization and lower them to a target-specific
DAG node.

llvm-svn: 79428
 2009-08-19 17:03:43 +00:00