Commit Graph

24983 Commits

Author SHA1 Message Date
Tom Stellard 34ed721af4 R600: Simplify assembly for KCache registers using the TableGen !add operator
Before:

MOV * T0.W, KC0[131-128].Y

After:

MOV * T0.W, KC0[3].Y

Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186917
2013-07-23 01:48:08 +00:00
Tom Stellard acfeebf883 R600: Use the same compute kernel calling convention for all GPUs
A side-effect of this is that now the compiler expects kernel arguments
to be 4-byte aligned.

Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186916
2013-07-23 01:48:05 +00:00
Tom Stellard 78e012969c R600: Use correct LoadExtType when lowering kernel arguments
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186915
2013-07-23 01:47:58 +00:00
Tom Stellard 33dd04bfbe R600: Clean up extended load patterns
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186914
2013-07-23 01:47:52 +00:00
Tom Stellard beed74af48 R600: Expand vector FNEG
llvm-svn: 186913
2013-07-23 01:47:46 +00:00
Craig Topper bf547cea0e Revert r186907 to fix bots.
llvm-svn: 186910
2013-07-23 01:29:37 +00:00
Craig Topper 80c310056c Don't let x86 asm printer use the no operand movsd alias. It should use the normal movsl instead.
llvm-svn: 186907
2013-07-23 01:21:36 +00:00
Craig Topper c15a9e4fa4 Add aliases to map 'imm, mem' form of x86 bts/btr/btc without a size suffix to their 32-bit forms.
This makes them consistent with 'bt' which already had this handling. gas has the same behavior. There have been discussions on the mailing list about determining size based on the immediate, but my goal here was just to remove the inconsistency.

llvm-svn: 186904
2013-07-23 00:56:15 +00:00
Craig Topper 001582833a Explicitly don't let the asm printer use the clrb/w/l aliases for xor %reg, %reg.
It only didn't use it before because it seems InstAlias handling in the asm printer fails to count tied operands so it tried to find an xor with 2 operands instead of the 3 it wfails to count tied.

llvm-svn: 186900
2013-07-23 00:15:19 +00:00
Craig Topper c638f0cd4f Suppress argumentless aliases for some x86 FP operations from being used by the asm writer. Prefer to use the explicit %st(1) form.
llvm-svn: 186897
2013-07-23 00:03:33 +00:00
Kevin Enderby 285da02094 Fix the move to/from accumulator register instructions that use a full 64-bit
absolute address encoded in the instruction.

rdar://8612627 and rdar://14299221

llvm-svn: 186878
2013-07-22 21:25:31 +00:00
Craig Topper 998bcf9534 Recommit r186813: More Intel syntax alias fixes. With the addition of suppressing some of the aliases from being emitted by the asm printer.
llvm-svn: 186869
2013-07-22 20:46:37 +00:00
Akira Hatanaka 4d2ea3c696 [mips] Fix MipsAsmParser::parseCCRRegs.
Enable parsing all 32 floating point control registers $0-31 and stop trying to
parse floating point condition code register $fcc0. Also, return ParseFail if
the operand being parsed is not in the expected format. 

llvm-svn: 186861
2013-07-22 19:30:38 +00:00
Akira Hatanaka 44ff81d4e3 [mips] Use ADDu instead of OR to copy general purpose registers. Also, delete
the InstAlias pattern which maps "move" to OR to resolve ambiguity in
MatchTable.

llvm-svn: 186855
2013-07-22 18:52:22 +00:00
Justin Holewinski 0b76dd85ea [NVPTX] Remove unused prototypes
llvm-svn: 186844
2013-07-22 17:04:40 +00:00
Mihai Popa 8a9da5b00c This adds range checking for "ldr Rn, [pc, #imm]" Thumb
instructions. With this patch:

1. ldr.n is recognized as mnemonic for the short encoding
2. ldr.w is recognized as menmonic for the long encoding
3. ldr will map to either short or long encodings depending on the size of the offset

llvm-svn: 186831
2013-07-22 15:49:36 +00:00
Justin Holewinski cd069e6dec [NVPTX] Use approximate FP ops when unsafe-fp-math is used, and append
.ftz to instructions if the nvptx-f32ftz attribute is set to "true"

llvm-svn: 186820
2013-07-22 12:18:04 +00:00
Tim Northover 1a9dafcd6f Revert "More Intel syntax alias fixes."
This reverts commit r186813, which broke the bots.

llvm-svn: 186818
2013-07-22 11:02:32 +00:00
Craig Topper b095c09330 Fix typo. Change %cl to CL in Intel pattern.
llvm-svn: 186815
2013-07-22 10:07:26 +00:00
Craig Topper 61da939a17 More Intel syntax alias fixes.
llvm-svn: 186814
2013-07-22 09:58:07 +00:00
Craig Topper 1b9e4e7e9d More Intel syntax alias fixes.
llvm-svn: 186813
2013-07-22 09:42:31 +00:00
Craig Topper 03db790dc6 Change %xmm0 to XMM0 in Intel side of asm strings for PBLENDVB.
llvm-svn: 186812
2013-07-22 09:22:49 +00:00
Craig Topper 8f9402a989 Add Intel variants to aliases for some FP instructions.
llvm-svn: 186811
2013-07-22 09:18:43 +00:00
Tim Northover eb5e4d532c ARM: remove now unneeded custom Asm converters
After Ulrich's r180677 (thanks!) TableGen is intelligent enough to
handle tied constraints involving complex operands properly, so
virtually all of the ARM custom converters are now unnecessary.

llvm-svn: 186810
2013-07-22 09:06:12 +00:00
Craig Topper d0ed3a417e Reverse operands for Intel syntax form of 'bt' alias.
llvm-svn: 186809
2013-07-22 07:47:51 +00:00
Richard Smith 70523c7926 Treat nothrow forms of ::operator delete and ::operator delete[] as
deallocation functions.

llvm-svn: 186798
2013-07-21 23:11:42 +00:00
Craig Topper 8956fe0dbc Mark that the _ftol2 function used by windows on x86 to handle fptoui modifies ECX.
llvm-svn: 186787
2013-07-21 07:28:13 +00:00
Lang Hames 24864fe150 Refactor AnalyzeBranch on ARM. The previous version did not always analyze
indirect branches correctly. Under some circumstances, this led to the deletion
of basic blocks that were the destination of indirect branches. In that case it
left indirect branches to nowhere in the code.

This patch replaces, and is more general than either of the previous fixes for
indirect-branch-analysis issues, r181161 and r186461.

For other branches (not indirect) this refactor should have *almost* identical
behavior to the previous version. There are some corner cases where this
refactor is able to analyze blocks that the previous version could not (e.g.
this necessitated the update to thumb2-ifcvt2.ll). 

<rdar://problem/14464830>

llvm-svn: 186735
2013-07-19 23:52:47 +00:00
Vincent Lejeune 8b8a7b5514 R600: Don't emit empty then clause and use alu_pop_after
llvm-svn: 186725
2013-07-19 21:45:15 +00:00
Vincent Lejeune 960a622ca6 R600: Simplify AMDILCFGStructurize by removing templates and assuming single exit
llvm-svn: 186724
2013-07-19 21:45:06 +00:00
Vincent Lejeune a8c38fedd6 R600: Replace legacy debug code in AMDILCFGStructurizer.cpp
llvm-svn: 186723
2013-07-19 21:44:56 +00:00
Joey Gouly f520d5e291 Add a line that got missed off somehow. Sorry about that!
llvm-svn: 186692
2013-07-19 16:45:16 +00:00
Richard Sandiford fac8b10a84 [SystemZ] Add ALRK, AGLRK, SLRK and SGLRK
Follows the same lines as r186686, but much more limited, since we only
use ADD LOGICAL for multi-i64 additions.

llvm-svn: 186689
2013-07-19 16:37:00 +00:00
Joey Gouly e860255850 [ARMv8] Implement the NEON instructions VRINT{N, X, A, Z, M, P}.
llvm-svn: 186688
2013-07-19 16:34:16 +00:00
Richard Sandiford 7d6a453623 [SystemZ] Add AHIK and AGHIK
I did these as a separate patch because it uses a slightly different
form of RIE layout.

llvm-svn: 186687
2013-07-19 16:32:12 +00:00
Richard Sandiford c575df6dcc [SystemZ] Add ARK, AGRK, SRK and SGRK
The testsuite changes follow the same lines as for r186683.

llvm-svn: 186686
2013-07-19 16:26:39 +00:00
Richard Sandiford c57e586792 [SystemZ] Add NGRK, OGRK and XGRK
Like r186683, but for 64 bits.

llvm-svn: 186685
2013-07-19 16:24:22 +00:00
Richard Sandiford 0175b4a353 [SystemZ] Add NRK, ORK and XRK
The atomic tests assume the two-operand forms, so I've restricted them to z10.

Running and-01.ll, or-01.ll and xor-01.ll for z196 as well as z10 shows why
using convertToThreeAddress() is better than exposing the three-operand forms
first and then converting back to two operands where possible (which is what
I'd originally tried).  Using the three-operand form first stops us from
taking advantage of NG, OG and XG for spills.

llvm-svn: 186683
2013-07-19 16:21:55 +00:00
Tilmann Scheller 34869503cb ARM: Add instruction aliases for the Thumb2 PLD/PLDW (literal) alternate form.
See A8.8.127 in ARM DDI 0406C.b.

Related to <rdar://problem/14403733>.

llvm-svn: 186682
2013-07-19 16:18:56 +00:00
Richard Sandiford ff6c5a5609 [SystemZ] Use SLLK, SRLK and SRAK for codegen
This patch uses the instructions added in r186680 for codegen.

llvm-svn: 186681
2013-07-19 16:12:08 +00:00
Richard Sandiford 27d1cfe3d4 [SystemZ] Start adding z196 and zEC12 support
This first step just adds definitions for SLLK, SRLK and SRAK.
The next patch will actually make use of them during codegen.

insn-bad.s tests that some form of error is reported when using these
instructions on z10.  More work is needed to get the "instruction requires:
distinct-ops" that we'd ideally like, so I've stubbed that part out for now.
I'll come back and make it mandatory once the necessary changes are in.

llvm-svn: 186680
2013-07-19 16:09:03 +00:00
Akira Hatanaka 5bcb2407a5 [mips] Delete MFC1_FT_CCR, MTC1_FT_CCR and MOVCCRToCCR.
No functionality change.

llvm-svn: 186642
2013-07-19 01:19:52 +00:00
Tilmann Scheller c8a06ff600 ARM: Make sure the instruction alias for PLI uses the right subtarget features.
PLI requires both the Thumb2 and the ARMv7 feature.

Related to <rdar://problem/14403733>.

llvm-svn: 186620
2013-07-18 22:19:59 +00:00
Tom Stellard 8374720aad R600/SI: Fix crash with VSELECT
https://bugs.freedesktop.org/show_bug.cgi?id=66175

llvm-svn: 186616
2013-07-18 21:43:53 +00:00
Tom Stellard adf732cfbc R600/SI: Add support for v2f32 loads
llvm-svn: 186615
2013-07-18 21:43:48 +00:00
Tom Stellard ed2f6149f3 R600/SI: Add support for v2f32 stores
llvm-svn: 186614
2013-07-18 21:43:42 +00:00
Tom Stellard 67ae4762ef R600: Expand VSELECT for all types
llvm-svn: 186613
2013-07-18 21:43:35 +00:00
Joey Gouly e25a86b082 Change 'n' to 'N' to keep consistent with other instructions.
llvm-svn: 186576
2013-07-18 12:00:25 +00:00
Joey Gouly 943dd59ed5 [ARMv8] Add NEON instructions VCVT{A, N, P, M}.
llvm-svn: 186574
2013-07-18 11:53:22 +00:00
Richard Sandiford 5109321042 [SystemZ] Use RNSBG
This should be the last of the R.SBG patches for now.

llvm-svn: 186573
2013-07-18 10:40:35 +00:00