Commit Graph

36831 Commits

Author SHA1 Message Date
Tim Northover 32b4d15e0a Move test to X86 directory: I think it depends on X86 TTI.
llvm-svn: 271019
2016-05-27 16:56:54 +00:00
Tim Northover 10a1e8b1fe Vectorizer: track non-fast FP instructions through phis when finding reductions.
When we traced through a phi node looking for floating-point reductions, we
forgot whether we'd ever seen an instruction without fast-math flags (that
would block vectorization). This propagates it through to the end.

llvm-svn: 271015
2016-05-27 16:40:27 +00:00
Dehao Chen 80b16d4135 Remove sample profile dependency to instcombine, which is not a analysis pass.
Summary: This patch removes dependency from sample profile pass to instcombine pass.

Reviewers: davidxl, dnovillo

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D20501

llvm-svn: 271009
2016-05-27 16:14:15 +00:00
Simon Pilgrim 7e67a22298 [X86][AVX] Removed some remains of old (pre-regeneration) filechecks
llvm-svn: 271007
2016-05-27 15:56:19 +00:00
Than McIntosh 4daf7f13b6 Disable lifetime-start-on-first-use analysis.
Summary:
Turn off lifetime-start-on-first-use enhancement for the moment
pending a fix for bug 27903.

Bug: 27903

Reviewers: tejohnson, wmi, qcolombet, gbiv

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D20731

llvm-svn: 271003
2016-05-27 15:27:51 +00:00
Simon Dardis 4ccda502d5 [mips] Weaken asm predicate for memory offsets
The isMemWithSimmOffset predicate rejects relocations which is incorrect
behaviour. Linkers and other tools should handle|warn|error when the
field overflows.

Reviewers: dsanders, vkalintiris

Differential Revision: http://reviews.llvm.org/D20727

llvm-svn: 270995
2016-05-27 13:56:36 +00:00
Igor Laevsky df9db45c94 [RewriteStatepointsForGC] All constant should have null base pointer
Currently we consider that each constant has itself as a base value. I.e "base(const) = const". 
This introduces couple of problems when we are trying to avoid reporting constants in statepoint live sets:

1. When querying "base( phi(const1, const2) )" we will get "phi(const1, const2)" as a base pointer. Since 
   it's not a constant we will record it in a stack map. However on practice we don't want this to happen
   (constant are never relocated).
2. base( phi(const, gc ptr) ) = phi( const, base(gc ptr) ). This particular case imposes challenge on our 
   runtime - we don't expect to see constant base pointers other than null. This problems can be avoided 
   by treating all constant as if they were derived from null pointer base. I.e in a first case we will 
   not include constant pointer in a stack map at all. In a second case we will get "phi(null, base(gc ptr))" 
   as a base pointer which is a lot more convenient.

Differential Revision: http://reviews.llvm.org/D20584

llvm-svn: 270993
2016-05-27 13:13:59 +00:00
George Rimar 7951fbf1a8 Attemp to fix build bot after r270987
It was: "Recommit 270977 - [llvm-mc] - Teach llvm-mc to generate zlib styled compression sections."

Fix:
since test requires no zlib available and r270987 changed the 
compression flag for llvm-mc to mandatory specify the compression style,
then just add 2 available styles to this test.

llvm-svn: 270992
2016-05-27 12:52:30 +00:00
Artem Tamazov 7da9b82e02 [AMDGPU][llvm-mc] Square-braced-syntax for registers - make ":expr2" optional.
Register numbers may be specified as assembly-time expressions.
This feature can be useful in macros and alike. However, expressions
are supported within sqare braces only.

Sqare braces were initially intended to support specifying of multiple
(pairs/quads...) registers. Syntax like v[8:8] which specifies single register
is also supported. That allows expressions but looks a bit unnatural.

This change supports syntax REG[EXPR].
Tests added.

Differential Revision: http://reviews.llvm.org/D20588

llvm-svn: 270990
2016-05-27 12:50:13 +00:00
George Rimar c91e38c5eb Recommit 270977 - [llvm-mc] - Teach llvm-mc to generate zlib styled compression sections.
Fix: updated clang code which was not updated by mistake.

Original commit message:
[llvm-mc] - Teach llvm-mc to generate zlib styled compression sections.

This patch is strongly based on previously reverted D20331.
(because of gnuutils < 2.26 does not support compressed debug sections in non zlib-gnu style)

Difference that this patch supports both zlib and zlib-gnu styles.

-compress-debug-sections option now supports next values:

-compress-debug-sections=zlib-gnu
-compress-debug-sections=zlib
-compress-debug-sections=none
Previously specifying -compress-debug-sections enabled zlib-gnu compression,
so anyone can put "-compress-debug-sections=zlib-gnu" to restore the behavior
that was before this patch for case when compression was enabled.

Differential revision: http://reviews.llvm.org/D20676

llvm-svn: 270987
2016-05-27 12:27:32 +00:00
George Rimar e79fc3efca Revert r270977 ([llvm-mc] - Teach llvm-mc to generate zlib styled compression sections.)
It broke buildbot:
http://lab.llvm.org:8011/builders/llvm-clang-lld-x86_64-scei-ps4-ubuntu-fast/builds/13585/steps/build/logs/stdio

Initial commit message:
[llvm-mc] - Teach llvm-mc to generate zlib styled compression sections.

This patch is strongly based on previously reverted D20331.
(because of gnuutils < 2.26 does not support compressed debug sections in non zlib-gnu style)

Difference that this patch supports both zlib and zlib-gnu styles.

-compress-debug-sections option now supports next values:

-compress-debug-sections=zlib-gnu
-compress-debug-sections=zlib
-compress-debug-sections=none
Previously specifying -compress-debug-sections enabled zlib-gnu compression,
so anyone can put "-compress-debug-sections=zlib-gnu" to restore the behavior
that was before this patch for case when compression was enabled.

Differential revision: http://reviews.llvm.org/D20676

llvm-svn: 270978
2016-05-27 10:06:16 +00:00
George Rimar 48dcd2b806 [llvm-mc] - Teach llvm-mc to generate zlib styled compression sections.
This patch is strongly based on previously reverted D20331.
(because of gnuutils < 2.26 does not support compressed debug sections in non zlib-gnu style)

Difference that this patch supports both zlib and zlib-gnu styles.

-compress-debug-sections option now supports next values:

-compress-debug-sections=zlib-gnu
-compress-debug-sections=zlib
-compress-debug-sections=none
Previously specifying -compress-debug-sections enabled zlib-gnu compression,
so anyone can put "-compress-debug-sections=zlib-gnu" to restore the behavior
that was before this patch for case when compression was enabled.

Differential revision: http://reviews.llvm.org/D20676

llvm-svn: 270977
2016-05-27 09:58:08 +00:00
Simon Pilgrim 4642a57fbf Revert: r270973 - [X86][SSE] Replace (V)PMOVSX and (V)PMOVZX integer extension intrinsics with generic IR (llvm)
llvm-svn: 270976
2016-05-27 09:02:25 +00:00
Simon Pilgrim c013e5737b [X86][SSE] Replace (V)PMOVSX and (V)PMOVZX integer extension intrinsics with generic IR (llvm)
This patch removes the llvm intrinsics VPMOVSX and (V)PMOVZX sign/zero extension intrinsics and auto-upgrades to SEXT/ZEXT calls instead. We already did this for SSE41 PMOVSX sometime ago so much of that implementation can be reused.

A companion patch (D20684) removes/auto-upgrade the clang intrinsics.

Differential Revision: http://reviews.llvm.org/D20686

llvm-svn: 270973
2016-05-27 08:49:15 +00:00
Peter Collingbourne 1eaa97f439 Linker: teach the IR mover to return llvm::Error.
This will be needed in order to consistently return an Error
to clients of the API being developed in D20268.

Differential Revision: http://reviews.llvm.org/D20550

llvm-svn: 270967
2016-05-27 05:21:35 +00:00
Pete Cooper 1929b5539a Form objc_storeStrong in the presence of bitcasts.
objc_storeStrong can be formed from a sequence such as

  %0 = tail call i8* @objc_retain(i8* %p) nounwind
  %tmp = load i8*, i8** @x, align 8
  store i8* %0, i8** @x, align 8
  tail call void @objc_release(i8* %tmp) nounwind

The code was already looking through bitcasts for most of the values
involved, but had missed one case where the pointer operand for the
store was a bitcast.  Ultimately the pointer for the load and store
have to be the same value, after stripping casts.

llvm-svn: 270955
2016-05-27 02:13:53 +00:00
Michael Zolotukhin 15e745133e [LoopUnrollAnalyzer] Bail out instead of dying with assert when facing huge index.
This fixes PR27902.

llvm-svn: 270946
2016-05-27 00:55:16 +00:00
Rui Ueyama 6816367a27 pdbdump: print out the name of the stream 0.
Differential Revision: http://reviews.llvm.org/D20712

llvm-svn: 270943
2016-05-27 00:32:07 +00:00
Rui Ueyama 9dc034dba1 pdbdump: Add -raw-all to enable all -raw-* flags.
Differential Revision: http://reviews.llvm.org/D20707

llvm-svn: 270937
2016-05-26 23:26:55 +00:00
Mitch Bodart 05aeeb5cf1 [CodeGen] Fix problem with X86 byte registers in CriticalAntiDepBreaker
CriticalAntiDepBreaker was not correctly tracking defs of the high X86 byte
registers, leading to incorrect use of a busy register to break an
antidependence.

Fixes pr27681, and its duplicates pr27580, pr27804.

Differential Revision: http://reviews.llvm.org/D20456

llvm-svn: 270935
2016-05-26 23:08:52 +00:00
Easwaran Raman 5fe04a1d8e Attach profile summary in IR based instrumentation pass.
Differential revision: http://reviews.llvm.org/D20655

llvm-svn: 270933
2016-05-26 22:57:11 +00:00
Michael Zolotukhin 1ecdedad8d [LoopUnrollAnalyzer] Fix a crash in analyzeLoopUnrollCost.
Condition might be simplified to a Constant, but it doesn't have to be
ConstantInt, so we should dyn_cast, instead of cast.

This fixes PR27886.

llvm-svn: 270924
2016-05-26 21:42:51 +00:00
Chris Bieneman 44474c48ac [obj2yaml][yaml2obj] Support for MachO lazy bindings
This adds support for YAML round tripping dyld info lazy bindings. The storage and format of these is the same as regular bind opcodes, they are just interpreted differently by dyld, and can have DONE opcodes in the middle of the opcode lists.

llvm-svn: 270920
2016-05-26 21:29:39 +00:00
Chris Bieneman 659b35a5d8 [obj2yaml][yaml2obj] Support for MachO weak bindings
This adds support for YAML round tripping dyld info weak bindings. The storage and format of these is the same as regular bind opcodes, they are just interpreted differently by dyld.

llvm-svn: 270911
2016-05-26 20:50:05 +00:00
Rafael Espindola 732eeaf2a9 coff: fix weak alias to local.
We were creating a weak external that tried to reference a static symbol. That
would always fail to link with link.exe.

We now create an external symbol in the same position as the local and refer
to that. This works with link.exe and matches what gas does.

llvm-svn: 270906
2016-05-26 20:31:00 +00:00
Chris Bieneman 524243d61e [obj2yaml][yaml2obj] Support for MachO bind opcodes
This adds support for YAML round tripping dyld info bind opcodes. Bind opcodes can have signed or unsigned LEB128 data, and they can have symbols associated with them.

llvm-svn: 270901
2016-05-26 20:06:14 +00:00
Krzysztof Parzyszek da0b9a959e [Hexagon] Enable the post-RA scheduler
The aggressive anti-dependency breaker can rename the restored callee-
saved registers. To prevent this, mark these registers are live on all
paths to the return/tail-call instructions, and add implicit use operands
for them to these instructions.

llvm-svn: 270898
2016-05-26 19:44:28 +00:00
Chad Rosier 14aa2ad1f4 [AArch64] Generate rev16/rev32 from bswap + srl when upper bits are known zero.
Canonicalize (srl (bswap i32 x), 16) to (rotr (bswap i32 x), 16), if the high
16-bits of x are zero. Similarly, canonicalize (srl (bswap i64 x), 32) to
(rotr (bswap i64 x), 32), if the high 32-bits of x are zero.

test_rev_w_srl16:            test_rev_w_srl16:
  and w8, w0, #0xffff          and     w8, w0, #0xffff
  rev w8, w8           --->    rev16   w0, w8
  lsr     w0, w8, 

test_rev_x_srl32:            test_rev_x_srl32:
  rev x8, x8           --->    rev32   x0, x8
  lsr x0, x8, 

llvm-svn: 270896
2016-05-26 19:41:33 +00:00
Changpeng Fang 71369b3a39 AMDGPU/SI: Enable load-store-opt by default.
Summary: Enable load-store-opt by default, and update LIT tests.

Reviewers: arsenm

Differential Revision: http://reviews.llvm.org/D20694

llvm-svn: 270894
2016-05-26 19:35:29 +00:00
Michael Kuperstein ae21491819 [BasicAA] Extend inbound GEP negative offset logic to GlobalVariables
r270777 improved the precision of alloca vs. inbounbds GEP alias queries: if
we have (a) an inbounds GEP and (b) a pointer based on an alloca, and the
beginning of the object the GEP points to would have a negative offset with
respect to the alloca, then the GEP can not alias pointer (b).

This makes the same logic fire when (b) is based on a GlobalVariable instead
of an alloca.

Differential Revision: http://reviews.llvm.org/D20652

llvm-svn: 270893
2016-05-26 19:30:49 +00:00
David Majnemer d99068d26d [MemCpyOpt] Don't perform callslot optimization across may-throw calls
An exception could prevent a store from occurring but MemCpyOpt's
callslot optimization would fire anyway, causing the store to occur.

This fixes PR27849.

llvm-svn: 270892
2016-05-26 19:24:24 +00:00
Rafael Espindola 30c080a085 coff: fix the section of weak symbols.
llvm-svn: 270889
2016-05-26 18:48:23 +00:00
Michael Kuperstein 9a81b62a01 [BBVectorize] Don't vectorize selects with a scalar condition and vector operands.
This fixes PR27879.

Differential Revision: http://reviews.llvm.org/D20659

llvm-svn: 270888
2016-05-26 18:43:57 +00:00
Krzysztof Parzyszek 729e7ad31f Add test/CodeGen/MIR/Hexagon/lit.local.cfg
Require that Hexagon is a registered target.

llvm-svn: 270887
2016-05-26 18:35:45 +00:00
Krzysztof Parzyszek 143f684a79 Do not rename registers that do not start an independent live range
llvm-svn: 270885
2016-05-26 18:22:53 +00:00
Rafael Espindola 6ddf5f4437 coff: fix the value of weak definitions.
It looks like this doesn't get a lot of use.

llvm-svn: 270883
2016-05-26 18:04:53 +00:00
David Majnemer 7f32420ed5 [CaptureTracking] Volatile operations capture their memory location
The memory location that corresponds to a volatile operation is very
special.  They are observed by the machine in ways which we cannot
reason about.

Differential Revision: http://reviews.llvm.org/D20555

llvm-svn: 270879
2016-05-26 17:36:22 +00:00
Artem Belevich 49e9a81236 [NVPTX] Added NVVMIntrRange pass
NVVMIntrRange adds !range metadata to calls of NVVM intrinsics
that return values within known limited range.

This allows LLVM to generate optimal code for indexing arrays
based on tid/ctaid which is a frequently used pattern in CUDA code.

Differential Revision: http://reviews.llvm.org/D20644

llvm-svn: 270872
2016-05-26 17:02:56 +00:00
Artem Tamazov 6edc135d0f [AMDGPU][llvm-mc] s_getreg/setreg* - hwreg - factor out strings/literals etc.
Hwreg(...) syntax implementation unified with sendmsg(...).
Common strings moved to Utils
MathExtras.h functionality utilized.
Added missing build dependency in Disassembler.

Differential Revision: http://reviews.llvm.org/D20381

llvm-svn: 270871
2016-05-26 17:00:33 +00:00
Simon Pilgrim cf340bd9c1 [X86][SSE] When lowering a 256-bit shuffle as PMOVZX, reduce the input vector to the lower 128-bit subvector.
Most often as not this is what it started out as, the extraction is zero-cost on AVX and the PMOVZX/PMOVSX folding logic is based around 128-bit loads.

llvm-svn: 270858
2016-05-26 15:40:36 +00:00
Diana Picus 81bc3170e8 [AMDGPU] Remove exit-on-error flag from test (PR27762)
Similar to r269948, but for argument lowering.

Fixes PR27762

Differential Revision: http://reviews.llvm.org/D20430

llvm-svn: 270856
2016-05-26 15:24:55 +00:00
Diana Picus 20a8d8e97e [BPF] Remove exit-on-error flag in test (PR27767)
The exit-on-error flag is needed to avoid an assert where
llvm::SelectionDAGISel::LowerArguments doesn't create enough arguments. Fill up
with zeroes to reach the right number of args.

Fixes PR27767.

Differential Revision: http://reviews.llvm.org/D20571

llvm-svn: 270855
2016-05-26 15:23:50 +00:00
Chad Rosier e5819e2732 [InstCombine] Catch more bswap cases missed due to zext and truncs.
Fixes PR27824.
Differential Revision: http://reviews.llvm.org/D20591.

llvm-svn: 270853
2016-05-26 14:58:51 +00:00
Simon Pilgrim 50c37ceb3b [X86][SSE] Added load_zext_16i8_to_8i32 test
Odd issue with input vector not being folded into pmovzx on AVX2+ targets

llvm-svn: 270852
2016-05-26 14:45:30 +00:00
Teresa Johnson 28c03b56ec [ThinLTO] Resolve LinkOnceAny
Summary:
Ensure we keep prevailing copy of LinkOnceAny by converting it to
WeakAny.

Rename odr_resolution test to the now more appropriate weak_resolution
(weak in the linker sense includes linkonce).

Reviewers: joker.eph

Subscribers: llvm-commits, joker.eph

Differential Revision: http://reviews.llvm.org/D20634

llvm-svn: 270850
2016-05-26 14:16:52 +00:00
Chad Rosier 816a67da49 [AArch64] Generate a BFI/BFXIL from 'or (and X, MaskImm), OrImm'.
If and only if the value being inserted sets only known zero bits.

This combine transforms things like

  and w8, w0, #0xfffffff0
  movz w9, 
  orr w0, w8, w9

into

  movz w8, 
  bfxil w0, w8, , 

The combine is tuned to make sure we always reduce the number of instructions.
We avoid churning code for what is expected to be performance neutral changes
(e.g., converted AND+OR to OR+BFI).

Differential Revision: http://reviews.llvm.org/D20387

llvm-svn: 270846
2016-05-26 13:27:56 +00:00
Rafael Espindola a224de06bc Use shouldAssumeDSOLocal on AArch64.
This reduces code duplication and now AArch64 also handles PIE.

llvm-svn: 270844
2016-05-26 12:42:55 +00:00
Igor Breger 8437bb70fd [AVX512] Fix intrinsic cmp{sd|ss} lowering.
Differential Revision: http://reviews.llvm.org/D20615

llvm-svn: 270843
2016-05-26 12:42:25 +00:00
Simon Pilgrim ab3809193c [X86][F16C] Added F16C fast-isel tests to match clang/test/CodeGen/f16c-builtins.c
llvm-svn: 270837
2016-05-26 10:26:56 +00:00
Simon Pilgrim 0e4fdc0842 [X86][AVX2] Added gather fast-isel tests to match clang/test/CodeGen/avx2-builtins.c
llvm-svn: 270835
2016-05-26 10:07:05 +00:00