Commit Graph

61683 Commits

Author SHA1 Message Date
Tom Stellard 3498e4ff1d R600: Fix the fetch limits for R600 generation GPUs
Reviewed-by: Vincent Lejeune <vljn@ovi.com>

https://bugs.freedesktop.org/show_bug.cgi?id=64257

llvm-svn: 183560
2013-06-07 20:28:55 +00:00
Tom Stellard 99792774a4 R600: Move Subtarget feature definitions into AMDGPU.td
This is the convention used by the other targets.

Reviewed-by: Vincent Lejeune <vljn@ovi.com>
llvm-svn: 183559
2013-06-07 20:28:49 +00:00
Tom Stellard b0804ec2ad R600: Remove unnecessary include
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
llvm-svn: 183558
2013-06-07 20:28:43 +00:00
Quentin Colombet 6baf581b93 Add a backend option to warn on a given stack size limit.
Option: -mllvm -warn-stack-size=<limit>
Output (if limit is exceeded):
warning: Stack size limit exceeded (<actual size>) in <functionName>.

The longer term plan is to hook that to a clang warning.
PR:4072
<rdar://problem/13987214>

llvm-svn: 183552
2013-06-07 20:18:12 +00:00
JF Bastien 06ce03d141 ARM FastISel integer sext/zext improvements
My recent ARM FastISel patch exposed this bug:
  http://llvm.org/bugs/show_bug.cgi?id=16178
The root cause is that it can't select integer sext/zext pre-ARMv6 and
asserts out.

The current integer sext/zext code doesn't handle other cases gracefully
either, so this patch makes it handle all sext and zext from i1/i8/i16
to i8/i16/i32, with and without ARMv6, both in Thumb and ARM mode. This
should fix the bug as well as make FastISel faster because it bails to
SelectionDAG less often. See fastisel-ext.patch for this.

fastisel-ext-tests.patch changes current tests to always use reg-imm AND
for 8-bit zext instead of UXTB. This simplifies code since it is
supported on ARMv4t and later, and at least on A15 both should perform
exactly the same (both have exec 1 uop 1, type I).

2013-05-31-char-shift-crash.ll is a bitcode version of the above bug
16178 repro.

fast-isel-ext.ll tests all sext/zext combinations that ARM FastISel
should now handle.

Note that my ARM FastISel enabling patch was reverted due to a separate
failure when dealing with MCJIT, I'll fix this second failure and then
turn FastISel on again for non-iOS ARM targets.

I've tested "make check-all" on my x86 box, and "lnt test-suite" on A15
hardware.

llvm-svn: 183551
2013-06-07 20:10:37 +00:00
Benjamin Kramer 705d841bb6 R600: Don't compare iterators of different maps.
Found be libstdc's debug mode.

llvm-svn: 183549
2013-06-07 19:59:34 +00:00
Quentin Colombet ba366011c8 Teach AsmPrinter how to print odd constants.
Fix an assertion when the compiler encounters big constants whose bit width is
not a multiple of 64-bits.
Although clang would never generate something like this, the backend should be
able to handle any legal IR.

<rdar://problem/13363576>

llvm-svn: 183544
2013-06-07 18:36:03 +00:00
Manman Ren 3c6acec02a DIBuilder: No functionality change.
Use the correct DIType when creating types in DIBuilder.

llvm-svn: 183543
2013-06-07 18:35:53 +00:00
Benjamin Kramer ebe0be9ca4 Vincent says the element is at most once in the vector, so we don't need a full std::remove.
llvm-svn: 183541
2013-06-07 18:18:12 +00:00
Rafael Espindola 8d477dc08f Use isxdigit.
Thanks to Benjamin Kramer for the suggestion.

llvm-svn: 183540
2013-06-07 18:05:03 +00:00
Roman Divacky 158d8069ad Fix a typo in asm string of BP* family of instructions. With this fix
I am able to compile/assemble/link/run /bin/echo from FreeBSD.

llvm-svn: 183537
2013-06-07 17:46:57 +00:00
Rafael Espindola aad6c24422 Support OpenBSD's native frame protection conventions.
OpenBSD's stack smashing protection differs slightly from other
platforms:

  1. The smash handler function is "__stack_smash_handler(const char
     *funcname)" instead of "__stack_chk_fail(void)".

  2. There's a hidden "long __guard_local" object that gets linked
     into each executable and DSO.

Patch by Matthew Dempsky.

llvm-svn: 183533
2013-06-07 16:35:57 +00:00
Benjamin Kramer a857fe115b R600: Fix a potential iterator invalidation issue.
As a bonus this reduces the loop from O(n^2) to O(n).

llvm-svn: 183532
2013-06-07 16:13:49 +00:00
Vincent Lejeune 931bb768fd R600: Remove an extra break in R600OptimizeVectorRegisters.cpp
llvm-svn: 183528
2013-06-07 15:44:53 +00:00
Benjamin Kramer f0ec199448 Fold variable that's only used in assert into the assert.
Avoids unused variable warnings in Release builds.

llvm-svn: 183512
2013-06-07 11:23:35 +00:00
Duncan Sands e0a607e376 Correct wrong register in this example, pointed out by Baoshan Pang.
llvm-svn: 183495
2013-06-07 08:30:55 +00:00
Bill Wendling 5e7656bf0c Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.

No functionality change intended.

llvm-svn: 183494
2013-06-07 07:55:53 +00:00
Bill Wendling ead89ef63e Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.

llvm-svn: 183493
2013-06-07 07:04:14 +00:00
Bill Wendling f535821364 Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.

llvm-svn: 183492
2013-06-07 06:30:15 +00:00
Bill Wendling 90bee83c38 Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.

llvm-svn: 183491
2013-06-07 06:26:43 +00:00
Bill Wendling 4a7a408eaa Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.

llvm-svn: 183490
2013-06-07 06:19:56 +00:00
Michael Gottesman 9e7261c874 [objc-arc] Ensure that the cfg path count does not overflow when we multiply TopDownPathCount/BottomUpPathCount.
rdar://12480535

llvm-svn: 183489
2013-06-07 06:16:49 +00:00
Bill Wendling f95178e679 Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.

llvm-svn: 183488
2013-06-07 05:54:19 +00:00
Bill Wendling 496dc33b9f Don't cache the instruction info and register info objects.
These objects are internal to the TargetMachine object and may change.

llvm-svn: 183485
2013-06-07 05:00:11 +00:00
Manman Ren 60711600da DIBuilder: No functionality change.
Use the correct DIType when creating vector types.

llvm-svn: 183484
2013-06-07 03:13:46 +00:00
Arnold Schwaighofer c5893da32d ARM sched model: Use the right resources for DIV
llvm-svn: 183477
2013-06-07 01:16:15 +00:00
Arnold Schwaighofer 5f0a2ce542 ARM sched model: Add VFP div instruction on Swift
Reapply 183271.

llvm-svn: 183472
2013-06-07 01:10:36 +00:00
Arnold Schwaighofer a30936a33b ARM sched model: Add SIMD/VFP load/store instructions on Swift
Reapply 183270 again (because three is a magic number).

This should now no longer seg fault after r183459.

llvm-svn: 183464
2013-06-07 00:04:28 +00:00
Venkatraman Govindaraju dc82ac0dcc [Sparc]: Use cmp instruction instead of subcc to compare integers.
llvm-svn: 183463
2013-06-07 00:03:36 +00:00
Jakub Staszak 96ff4d6d3b Simplify code. No functionality change.
llvm-svn: 183461
2013-06-06 23:34:59 +00:00
Vincent Lejeune 0030362ed9 R600: Rewrite an awkward loop in R600MachineScheduler
llvm-svn: 183458
2013-06-06 23:08:32 +00:00
Nadav Rotem 99e529ea3c Jeffrey Yasskin volunteered to benchmark the vectorizer on -O2 or -Os when compiling chrome. This patch adds a new flag to enable vectorization on all levels and not only on -O3. It should go away once we make a decision.
llvm-svn: 183456
2013-06-06 22:35:47 +00:00
David Blaikie b272a75328 Fix break in r183446 - helps to increment the iterator in a loop
llvm-svn: 183454
2013-06-06 22:28:26 +00:00
Arnold Schwaighofer e5f6a8f649 Revert "ARM sched model: Add SIMD/VFP load/store instructions on Swift"
Breaks linux build bots (I thought the problem was something else).

llvm-svn: 183447
2013-06-06 21:08:18 +00:00
David Blaikie 36d5d2f08d Debug Info: simplify parameter ordering preservation
Seems we emit the parameter ordering number (spuriously named 'arg
number') in the debug info, so there's no need to search through the
variable list to figure out the parameter ordering. This implementation
does 'always' do the work, even in non-optimized debug info (the
previous implementation checked the existence of the 'variables' list on
the subprogram which is only present in optimized builds).

No intended functionality change.

llvm-svn: 183446
2013-06-06 21:04:51 +00:00
Arnold Schwaighofer cfe830dc52 ARM sched model: Add SIMD/VFP load/store instructions on Swift
Reapply 183270.

llvm-svn: 183445
2013-06-06 21:02:18 +00:00
Arnold Schwaighofer eac54473dd ARM sched model: Add integer VFP/SIMD instructions on Swift
Reapply 183269.

llvm-svn: 183441
2013-06-06 20:26:18 +00:00
Jakub Staszak bddea11bc5 Re-apply "Use IRBuilder instead of ConstantInt methods." with the fixed issues.
llvm-svn: 183439
2013-06-06 20:18:46 +00:00
Arnold Schwaighofer dff8e4c488 ARM sched model: Add integer load/store instructions on Swift
Reapply 183268.

llvm-svn: 183438
2013-06-06 20:11:56 +00:00
Arnold Schwaighofer 41a7b06888 ARM sched model: Add integer arithmetic instructions on Swift
Reapply 183267.

llvm-svn: 183436
2013-06-06 19:49:46 +00:00
Arnold Schwaighofer 57142859e1 ARM sched model: Cortex A9 - More InstRW sched resources
Add more InstRW mappings.

Reapply 183266.

llvm-svn: 183435
2013-06-06 19:30:21 +00:00
Arnold Schwaighofer f1395b695e ARM sched model: Add branch thumb instructions
Reapply 183265.

llvm-svn: 183432
2013-06-06 18:51:01 +00:00
Arnold Schwaighofer 10ccc99c53 ARM sched model: Add branch thumb2 instructions
Reapply 183264.

llvm-svn: 183430
2013-06-06 18:42:09 +00:00
Arnold Schwaighofer 91d4ee3759 ARM sched model: Add branch instructions
Reapply 183263.

llvm-svn: 183428
2013-06-06 18:21:13 +00:00
Arnold Schwaighofer 577279778e ARM sched model: Add preload thumb2 instructions
Reapply 183262.

llvm-svn: 183427
2013-06-06 18:06:30 +00:00
Arnold Schwaighofer 1b41330460 ARM sched model: Add preload instructions
Reapply 183261.

llvm-svn: 183425
2013-06-06 17:26:12 +00:00
Kevin Enderby 273ae01b03 Teach llvm-objdump with the -macho parser how to use the data in code table
from the LC_DATA_IN_CODE load command.  And when disassembling print
the data in code formatted for the kind of data it and not disassemble those
bytes.

I added the format specific functionality to the derived class MachOObjectFile
since these tables only appears in Mach-O object files. This is my first
attempt to modify the libObject stuff so if folks have better suggestions
how to fit this in or suggestions on the implementation please let me know.

rdar://11791371

llvm-svn: 183424
2013-06-06 17:20:50 +00:00
Arnold Schwaighofer 654649dd0b ARM sched model: Add more ALU and CMP thumb instructions
Reapply of 183260.

llvm-svn: 183423
2013-06-06 17:03:13 +00:00
Rafael Espindola a7bbc0b740 Revert "Use IRBuilder instead of ConstantInt methods. It simplifies code a little bit."
This reverts commit 183328. It caused pr16244 and broke the bots.

llvm-svn: 183422
2013-06-06 17:03:05 +00:00
Arnold Schwaighofer 972ce4778f ARM sched model: Add more ALU and CMP thumb2 instructions
Reapply of 183259.

llvm-svn: 183421
2013-06-06 16:35:25 +00:00