5e9084207f
If the operand is marked M_OPTIONAL_DEF_OPERAND, then it's a def.
...
llvm-svn: 38496
2007-07-10 17:52:20 +00:00
ff6f279adf
When a node value is only used by a CopyToReg, use the user's dest. This should not be restricted to nodes that produce only a single value.
...
llvm-svn: 38485
2007-07-10 07:08:32 +00:00
642be16bbf
Change CalculateHeights and CalculateDepths to be non-recursive.
...
llvm-svn: 37934
2007-07-06 01:37:28 +00:00
a7644dd9b9
Pass a SelectionDAG into SDNode::dump everywhere it's used, in prepration
...
for needing the DAG node to print pre-legalize extended value types, and
to get better debug messages with target-specific nodes.
llvm-svn: 37656
2007-06-19 14:13:56 +00:00
1baf5c84ab
Fix some VC++ warnings.
...
llvm-svn: 35224
2007-03-20 20:43:18 +00:00
971aa18867
Code clean up.
...
llvm-svn: 35220
2007-03-20 20:09:03 +00:00
25878b45f5
CopyToReg source operand can be a physical register.
...
llvm-svn: 35213
2007-03-20 16:46:44 +00:00
56e5fea163
print target nodes nicely
...
llvm-svn: 34369
2007-02-17 06:38:37 +00:00
68dcec6fea
fix indentation
...
llvm-svn: 34307
2007-02-15 18:19:15 +00:00
21ebae3394
Apply B Scott Michel's patch for PR1184, which improves diagnostics in an
...
abort case.
llvm-svn: 34306
2007-02-15 18:17:56 +00:00
09575bac2e
For PR1195:
...
Change use of "packed" term to "vector" in comments, strings, variable
names, etc.
llvm-svn: 34300
2007-02-15 03:39:18 +00:00
19083a4671
switch the VRBaseMap in the scheduler from an std::map to a DenseMap. This
...
speeds up the isel pass from 2.5570s to 2.4722s on kc++ (3.4%).
llvm-svn: 33879
2007-02-04 08:47:20 +00:00
f9e5445ed4
Make LABEL a builtin opcode.
...
llvm-svn: 33537
2007-01-26 14:34:52 +00:00
f5c96fabf9
Renamed getTypeAlignmentShift() to getPreferredTypeAlignmentShift().
...
llvm-svn: 33482
2007-01-24 07:03:39 +00:00
be48a47d9d
Remove the DoubleTy special case.
...
llvm-svn: 33449
2007-01-22 23:13:55 +00:00
a8a0f2cf68
Compensate for loss of DerivedTypes.h in TargetLowering.h
...
llvm-svn: 33159
2007-01-12 23:31:12 +00:00
376c9c4c97
CopyToReg source operand can be a register as well. e.g. Copy from GlobalBaseReg.
...
llvm-svn: 32929
2007-01-05 20:59:06 +00:00
22e978a736
Removing even more <iostream> includes.
...
llvm-svn: 32320
2006-12-07 20:04:42 +00:00
67fc141db5
Match TargetInstrInfo changes.
...
llvm-svn: 32098
2006-12-01 21:52:58 +00:00
20350c4025
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
...
of opcode and number of operands.
llvm-svn: 31947
2006-11-27 23:37:22 +00:00
dbd3d294e6
Matches MachineInstr changes.
...
llvm-svn: 31712
2006-11-13 23:36:35 +00:00
979bbf48d5
Add methods to add implicit def use operands to a MI.
...
llvm-svn: 31675
2006-11-11 10:20:02 +00:00
8c9c6d71ed
Add implicit def / use operands to MachineInstr.
...
llvm-svn: 31633
2006-11-10 08:43:01 +00:00
fd2c5dd806
Changes to use operand constraints to process two-address instructions.
...
llvm-svn: 31453
2006-11-04 09:44:31 +00:00
1fd360e13a
handle global address constant sdnodes
...
llvm-svn: 31323
2006-10-31 20:01:56 +00:00
47fbeda5ce
Debug tweak.
...
llvm-svn: 30959
2006-10-14 08:34:06 +00:00
45fe3bc72c
Added support for machine specific constantpool values. These are useful for
...
representing expressions that can only be resolved at link time, etc.
llvm-svn: 30278
2006-09-12 21:00:35 +00:00
af23f9b5f6
Completely eliminate def&use operands. Now a register operand is EITHER a
...
def operand or a use operand.
llvm-svn: 30109
2006-09-05 02:31:13 +00:00
d86418ab20
switch the SUnit pred/succ sets from being std::sets to being smallvectors.
...
This reduces selectiondag time on kc++ from 5.43s to 4.98s (9%). More
significantly, this speeds up the default ppc scheduler from ~1571ms to 1063ms,
a 33% speedup.
llvm-svn: 29743
2006-08-17 00:09:56 +00:00
1640ae5a84
Reverse the FlaggedNodes after scanning up for flagged preds or else the order would be reversed.
...
llvm-svn: 29545
2006-08-07 22:12:12 +00:00
4e153f1b91
Use an enumeration to eliminate data relocations.
...
llvm-svn: 29249
2006-07-21 20:57:35 +00:00
f7300b2706
It was pointed out that DEBUG() is only available with -debug.
...
llvm-svn: 29106
2006-07-11 18:25:13 +00:00
c3d341ea98
Ensure that dump calls that are associated with asserts are removed from
...
non-debug build.
llvm-svn: 29105
2006-07-11 17:58:07 +00:00
55772ccfd6
Instructions with variable operands (variable_ops) can have a number required
...
operands. e.g.
def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
"call {*}$dst", [(X86call GR32:$dst)]>;
TableGen should emit operand informations for the "required" operands.
Added a target instruction info flag M_VARIABLE_OPS to indicate the target
instruction may have more operands in addition to the minimum required
operands.
llvm-svn: 28791
2006-06-15 07:22:16 +00:00
0c0996a97b
commuteInstruction() does not always create a new MI!
...
llvm-svn: 28592
2006-05-31 18:03:39 +00:00
9d91caa053
Eliminate a memory leak.
...
llvm-svn: 28585
2006-05-31 07:13:03 +00:00
d8e2f6ebc1
lib/Target/Target.td
...
llvm-svn: 28386
2006-05-18 20:42:07 +00:00
957cb6733a
Move function-live-in-handling code from the sdisel code to the scheduler.
...
This code should be emitted after legalize, so it can't be in sdisel.
Note that the EmitFunctionEntryCode hook should be updated to operate on the
DAG. The X86 backend is the only one currently using this hook.
llvm-svn: 28315
2006-05-16 06:10:58 +00:00
99f2f79e2f
Fixing 2006-05-01-SchedCausingSpills.ll; some clean up
...
llvm-svn: 28279
2006-05-13 08:22:24 +00:00
8c2c1e90c4
Refactor a bunch of includes so that TargetMachine.h doesn't have to include
...
TargetData.h. This should make recompiles a bit faster with my current
TargetData tinkering.
llvm-svn: 28238
2006-05-12 06:33:49 +00:00
095c9d9b7f
Duh. That could take a long time.
...
llvm-svn: 28235
2006-05-12 06:05:18 +00:00
afed73eebe
Add capability to scheduler to commute nodes for profit.
...
If a two-address code whose first operand has uses below, it should be commuted
when possible.
llvm-svn: 28230
2006-05-12 01:58:24 +00:00
d38c22bdd3
Refactor scheduler code. Move register-reduction list scheduler to a
...
separate file. Added an initial implementation of top-down register pressure
reduction list scheduler.
llvm-svn: 28226
2006-05-11 23:55:42 +00:00
469647bf38
Remove and simplify some more machineinstr/machineoperand stuff.
...
llvm-svn: 28105
2006-05-04 18:16:01 +00:00
10b71c0d08
Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling.
...
llvm-svn: 28104
2006-05-04 18:05:43 +00:00
940cc978ef
Remove a bunch more SparcV9 specific stuff
...
llvm-svn: 28093
2006-05-04 01:15:02 +00:00
20a631fde7
Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference.
...
This fixes PR 759.
llvm-svn: 28074
2006-05-03 01:29:57 +00:00
4ca2ea5b43
JumpTable support! What this represents is working asm and jit support for
...
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.
llvm-svn: 27947
2006-04-22 18:53:45 +00:00
87b1dddb1c
fix spello
...
llvm-svn: 27053
2006-03-24 07:15:07 +00:00
6b20104410
TargetData doesn't know the alignment of vectors :(
...
llvm-svn: 26884
2006-03-20 01:51:46 +00:00
a5b93b8c6d
Move some simple-sched-specific instance vars to the simple scheduler.
...
llvm-svn: 26690
2006-03-10 07:42:02 +00:00
e015178de1
prune #includes
...
llvm-svn: 26689
2006-03-10 07:37:35 +00:00
4b70ff7876
move some simple scheduler methods into the simple scheduler
...
llvm-svn: 26688
2006-03-10 07:35:21 +00:00
dc2f135f5c
Make EmitNode take a SDNode instead of a NodeInfo*
...
llvm-svn: 26687
2006-03-10 07:28:36 +00:00
b9d8fa0342
Move the VRBase field from NodeInfo to being a separate, explicit, map.
...
llvm-svn: 26686
2006-03-10 07:25:12 +00:00
2f8c7c3d55
Push PrepareNodeInfo/IdentifyGroups down the inheritance hierarchy
...
llvm-svn: 26682
2006-03-10 06:34:51 +00:00
543832d39d
Change the interface for getting a target HazardRecognizer to be more clean.
...
llvm-svn: 26608
2006-03-08 04:25:59 +00:00
2d945ba4c7
When a hazard recognizer needs noops to be inserted, do so. This represents
...
noops as null pointers in the instruction sequence.
llvm-svn: 26564
2006-03-05 23:51:47 +00:00
ed169db8a5
Added an offset field to ConstantPoolSDNode.
...
llvm-svn: 26371
2006-02-25 09:54:52 +00:00
5af3fdec12
Pass all the flags to the asm printer, not just the # operands.
...
llvm-svn: 26362
2006-02-24 19:50:58 +00:00
2f8a794b13
rename NumOps -> NumVals to avoid shadowing a NumOps var in an outer scope.
...
Add support for addressing modes.
llvm-svn: 26361
2006-02-24 19:18:20 +00:00
86c51000db
Refactor operand adding out to a new AddOperand method
...
llvm-svn: 26358
2006-02-24 18:54:03 +00:00
571d9647c6
Record all of the expanded registers in the DAG and machine instr, fixing
...
several bugs in inline asm expanded operands.
llvm-svn: 26332
2006-02-23 19:21:04 +00:00
4576bb74d5
Make MachineConstantPool entries alignments explicit
...
llvm-svn: 26071
2006-02-09 02:23:13 +00:00
95ae171d5b
Fix VC++ warning.
...
llvm-svn: 25975
2006-02-04 16:20:31 +00:00
f9adce90bf
Get rid of some memory leaks identified by Valgrind
...
llvm-svn: 25960
2006-02-04 06:49:00 +00:00
3b48431333
Add initial support for immediates. This allows us to compile this:
...
int %rlwnm(int %A, int %B) {
%C = call int asm "rlwnm $0, $1, $2, $3, $4", "=r,r,r,n,n"(int %A, int %B, int 4, int 17)
ret int %C
}
into:
_rlwnm:
or r2, r3, r3
or r3, r4, r4
rlwnm r2, r2, r3, 4, 17 ;; note the immediates :)
or r3, r2, r2
blr
llvm-svn: 25955
2006-02-04 02:26:14 +00:00
32be2dc0af
Allow the specification of explicit alignments for constant pool entries.
...
llvm-svn: 25855
2006-01-31 22:23:14 +00:00
2e56e89452
Handle physreg input/outputs. We now compile this:
...
int %test_cpuid(int %op) {
%B = alloca int
%C = alloca int
%D = alloca int
%A = call int asm "cpuid", "=eax,==ebx,==ecx,==edx,eax"(int* %B, int* %C, int* %D, int %op)
%Bv = load int* %B
%Cv = load int* %C
%Dv = load int* %D
%x = add int %A, %Bv
%y = add int %x, %Cv
%z = add int %y, %Dv
ret int %z
}
to this:
_test_cpuid:
sub %ESP, 16
mov DWORD PTR [%ESP], %EBX
mov %EAX, DWORD PTR [%ESP + 20]
cpuid
mov DWORD PTR [%ESP + 8], %ECX
mov DWORD PTR [%ESP + 12], %EBX
mov DWORD PTR [%ESP + 4], %EDX
mov %ECX, DWORD PTR [%ESP + 12]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 8]
add %EAX, %ECX
mov %ECX, DWORD PTR [%ESP + 4]
add %EAX, %ECX
mov %EBX, DWORD PTR [%ESP]
add %ESP, 16
ret
... note the proper register allocation. :)
it is unclear to me why the loads aren't folded into the adds.
llvm-svn: 25827
2006-01-31 02:03:41 +00:00
4df279cfda
Teach the scheduler to emit the appropriate INLINEASM MachineInstr for an
...
ISD::INLINEASM node.
llvm-svn: 25668
2006-01-26 23:28:04 +00:00
1880f8db02
No need to keep track of top and bottom nodes in a group since the vector is
...
already in order. Thanks Jim for pointing it out.
llvm-svn: 25608
2006-01-25 18:54:24 +00:00
fbc88a624a
Keep track of bottom / top element of a set of flagged nodes.
...
llvm-svn: 25600
2006-01-25 09:13:41 +00:00
c1e1d9724d
Factor out more instruction scheduler code to the base class.
...
llvm-svn: 25532
2006-01-23 07:01:07 +00:00
739a6a456e
Do some code refactoring on Jim's scheduler in preparation of the new list
...
scheduler.
llvm-svn: 25493
2006-01-21 02:32:06 +00:00
fb6a914ca7
purity++
...
llvm-svn: 25041
2005-12-29 05:59:19 +00:00
9e296bee9a
Disengage DEBUG_LOC from non-PPC targets.
...
llvm-svn: 24919
2005-12-21 20:51:37 +00:00
9b9688aeb8
Amend comment.
...
llvm-svn: 24861
2005-12-19 16:32:26 +00:00
ce23987e6b
Create a strong dependency for loads following stores. This will leave a
...
latency period between the two.
llvm-svn: 24860
2005-12-19 16:30:13 +00:00
c7cb351aac
Keep VC++ happy.
...
llvm-svn: 24835
2005-12-18 22:20:05 +00:00
c97b7d0be9
Fix a bug Sabre was having where the DAG root was a group. The group dominator
...
needed to be added to the ordering list, not the first member of the group.
llvm-svn: 24816
2005-12-18 04:40:52 +00:00
e220821deb
Groups were not emitted if the dominator node and the node in the ordering list
...
were not the same node. Ultimately the test was bogus.
llvm-svn: 24815
2005-12-18 03:59:21 +00:00
cf12118965
Simplify code
...
llvm-svn: 24806
2005-12-18 01:03:46 +00:00
006bb04f3a
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
...
work. This change has no effect on generated code.
llvm-svn: 24563
2005-12-01 04:51:06 +00:00
0e0de2f3f0
Added an index field to GlobalAddressSDNode so it can represent X+12, etc.
...
llvm-svn: 24523
2005-11-30 02:04:11 +00:00
bf4f233214
Switch the allnodes list from a vector of pointers to an ilist of nodes.This eliminates the vector, allows constant time removal of a node froma graph, and makes iteration over the all nodes list stable when adding
...
nodes to the graph.
llvm-svn: 24263
2005-11-09 23:47:37 +00:00
3ba38cba64
Explicitly initialize some instance vars
...
llvm-svn: 24247
2005-11-08 21:54:57 +00:00
1d2f26adcc
Let's try ignoring resource utilization on the backward pass.
...
llvm-svn: 24231
2005-11-07 19:08:53 +00:00
904dbb4a27
Fix logic bug in finding retry slot in tally.
...
llvm-svn: 24188
2005-11-05 00:01:25 +00:00
ded4759d81
Fix a warning
...
llvm-svn: 24187
2005-11-04 18:26:02 +00:00
e682b677c1
Scheduling now uses itinerary data.
...
llvm-svn: 24180
2005-11-04 04:05:35 +00:00
5ce0538253
1. Embed and not inherit vector for NodeGroup.
...
2. Iterate operands and not uses (performance.)
3. Some long pending comment changes.
llvm-svn: 24119
2005-10-31 12:49:09 +00:00
dd5663dfa0
Reduce the number of copies emitted as machine instructions by
...
generating results in vregs that will need them. In the case of something
like this: CopyToReg((add X, Y), reg1024), we no longer emit code like
this:
reg1025 = add X, Y
reg1024 = reg 1025
Instead, we emit:
reg1024 = add X, Y
Whoa! :)
llvm-svn: 24111
2005-10-30 18:54:27 +00:00
5d7a50ac44
Inhibit instructions from being pushed before function calls. This will
...
minimize unnecessary spilling.
llvm-svn: 23710
2005-10-13 16:44:00 +00:00
63b1419b74
Finally committing to the new scheduler. Still -sched=none by default.
...
llvm-svn: 23702
2005-10-12 18:29:35 +00:00
0832f2635a
When emiting a CopyFromReg and the source is already a vreg, do not bother
...
creating a new vreg and inserting a copy: just use the input vreg directly.
This speeds up the compile (e.g. about 5% on mesa with a debug build of llc)
by not adding a bunch of copies and vregs to be coallesced away. On mesa,
for example, this reduces the number of intervals from 168601 to 129040
going into the coallescer.
llvm-svn: 23671
2005-10-09 05:58:56 +00:00
327d4298e1
Reverting to version - until problem isolated.
...
llvm-svn: 23622
2005-10-04 16:41:51 +00:00
409a6b204e
Refactor gathering node info and emission.
...
llvm-svn: 23610
2005-10-03 12:30:32 +00:00
7f718e61e8
silence a bogus warning
...
llvm-svn: 23595
2005-10-02 16:30:51 +00:00
704d97f8b2
Add assertions to the trivial scheduler to check that the value types match
...
up between defs and uses.
llvm-svn: 23590
2005-10-02 07:10:55 +00:00
a038d901fb
Codegen CopyFromReg using the regclass that matches the valuetype of the
...
destination vreg.
llvm-svn: 23586
2005-10-02 06:34:16 +00:00
Evan Cheng